diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-11-23 16:14:23 -0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-10 23:13:32 +0100 |
| commit | 4cfa939c693b20ca213f054c1dfe5583d966beb4 (patch) | |
| tree | 3713797ca6ba5add9d7c4128ee820da32479405e /drivers | |
| parent | 5bc7cf898751aa8aa4d19692354244b7a3510476 (diff) | |
gpio: mxc: clear interrupt mask/status optionally
Add a kernel parameter ("gpio-mxc.noclearirq") to disable
unconditional interrupt mask/clearing. This is useful when a
second CPU (the Cortex-M4) is accessing the same GPIO bank.
Using the same GPIO bank from the Cortex-A7 and M4 sounds risky,
but it seems to work quite well. Most registers are write only
(e.g. interrupt status register can be cleared with a single
write), which makes them safe for concurrent access. However,
sharing a single GPIO bank between two cores does not allow to
use the Resource Domain Controller. Hence for secure applications
assigning a dedicated GPIO bank is still preferable.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/gpio-mxc.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 9f7446a7ac64..53ee7a8dcc5a 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -35,6 +35,10 @@ #include <linux/module.h> #include <asm-generic/bug.h> +static bool noclearirq = false; +module_param(noclearirq, bool, 0); +MODULE_PARM_DESC(noclearirq, "do not clear IRQ mask/status on probe"); + enum mxc_gpio_hwtype { IMX1_GPIO, /* runs on i.mx1 */ IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ @@ -425,8 +429,10 @@ static int mxc_gpio_probe(struct platform_device *pdev) return port->irq; /* disable the interrupt and clear the status */ - writel(0, port->base + GPIO_IMR); - writel(~0, port->base + GPIO_ISR); + if (!noclearirq) { + writel(0, port->base + GPIO_IMR); + writel(~0, port->base + GPIO_ISR); + } if (mxc_gpio_hwtype == IMX21_GPIO) { /* |