diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-03-02 20:42:04 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-01-29 10:14:57 +0000 |
| commit | 0ab7aefc4d43a6dee26c891b41ef9c7a67d2379b (patch) | |
| tree | 4a627b7079979ad43b08cef297b2a6eb78d0a78e /include/asm-mips/cpu-info.h | |
| parent | 92b1e6a64a8d9d5ed3ec8797eed8b36e2164a410 (diff) | |
[MIPS] MT: Scheduler support for SMT
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-info.h')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index ed5c02c6afbb..0c5a358863f3 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -55,6 +55,7 @@ struct cpuinfo_mips { struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ + int core; /* physical core number */ #if defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered @@ -63,8 +64,10 @@ struct cpuinfo_mips { * to all TCs within the same VPE. */ int vpe_id; /* Virtual Processor number */ - int tc_id; /* Thread Context number */ #endif /* CONFIG_MIPS_MT */ +#ifdef CONFIG_MIPS_MT_SMTC + int tc_id; /* Thread Context number */ +#endif void *data; /* Additional data */ } __attribute__((aligned(SMP_CACHE_BYTES))); |