MLK-19252-6 drm/bridge: sec-dsim: improve DPHY TIMING configs

The SEC provides a table to guide the DPHY TIMINGS config based
on the PLL output bit clock frequency for DSIM. So create the
table which is used by SEC LN14LPP DPHY with HS Timing v1.2 and
this table will be used by the SEC DSIM Bridge driver to help to
config the corresponding DPHY Timings correctly for each display
mode. Along with the table, a DPHY TIMING table entry 'compare'
method is implemented for the binary search when lookup the
suitable DPHY TIMING entry.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit eb899b434be6127db26c370bf200d8072eaf01c4)
(cherry picked from commit 3b23233dafd65d6ea8c1fa12e8992c58ebc412bc)

1 files changed, 55 insertions, 0 deletions

diff --git a/include/drm/bridge/sec_mipi_dsim.h b/include/drm/bridge/sec_mipi_dsim.h
index 911513ac9c51..44842184cff2 100644
--- a/include/drm/bridge/sec_mipi_dsim.h
+++ b/include/drm/bridge/sec_mipi_dsim.h
@@ -16,15 +16,70 @@
 #define __SEC_MIPI_DSIM_H__
 
 #include <drm/drmP.h>
+#include <linux/bsearch.h>
+
+struct sec_mipi_dsim_dphy_timing;
 
 struct sec_mipi_dsim_plat_data {
 	uint32_t version;
 	uint32_t max_data_lanes;
 	uint64_t max_data_rate;
+	const struct sec_mipi_dsim_dphy_timing *dphy_timing;
+	uint32_t num_dphy_timing;
+	int (*dphy_timing_cmp)(const void *key, const void *elt);
 	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 					   struct drm_display_mode *mode);
 };
 
+/* DPHY timings structure */
+struct sec_mipi_dsim_dphy_timing {
+	uint32_t bit_clk;	/* MHz */
+
+	uint32_t clk_prepare;
+	uint32_t clk_zero;
+	uint32_t clk_post;
+	uint32_t clk_trail;
+
+	uint32_t hs_prepare;
+	uint32_t hs_zero;
+	uint32_t hs_trail;
+
+	uint32_t lpx;
+	uint32_t hs_exit;
+};
+
+#define DSIM_DPHY_TIMING(bclk, cpre, czero, cpost, ctrail,	\
+			 hpre, hzero, htrail, lp, hexit)	\
+	.bit_clk	= bclk,					\
+	.clk_prepare	= cpre,					\
+	.clk_zero	= czero,				\
+	.clk_post	= cpost,				\
+	.hs_prepare	= hpre,					\
+	.hs_zero	= hzero,				\
+	.hs_trail	= htrail,				\
+	.lpx		= lp,					\
+	.hs_exit	= hexit
+
+static inline int dphy_timing_default_cmp(const void *key, const void *elt)
+{
+	const struct sec_mipi_dsim_dphy_timing *_key = key;
+	const struct sec_mipi_dsim_dphy_timing *_elt = elt;
+
+	/* find an element whose 'bit_clk' is equal to the
+	 * the key's 'bit_clk' value or, the difference
+	 * between them is less than 5.
+	 */
+	if (abs((int)(_elt->bit_clk - _key->bit_clk)) <= 5)
+		return 0;
+
+	if (_key->bit_clk < _elt->bit_clk)
+		/* search bottom half */
+		return 1;
+	else
+		/* search top half */
+		return -1;
+}
+
 int sec_mipi_dsim_check_pll_out(void *driver_private,
 				const struct drm_display_mode *mode);
 int sec_mipi_dsim_bind(struct device *dev, struct device *master, void *data,