diff options
| author | Leonard Crestez <leonard.crestez@nxp.com> | 2019-03-08 15:07:33 +0200 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2019-03-11 13:41:36 +0200 |
| commit | 176f72cb5dc0ed96d0ca9e9fa847df362ab55754 (patch) | |
| tree | ac930c9801653967049ecaab4c5e4426df967898 /include/dt-bindings | |
| parent | 9b73c0b4f802c9493995c4ab96a9f58f2aa46964 (diff) | |
MLK-21051 dt-bindings: pinctrl: Sync SCFW header to commit ef4a5057
Replace manually added pads with defines from SCFW export package.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 21dc9c9834783b13999fcdd1d9dbe50c4ae730ae)
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qm.h | 32 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qxp.h | 28 |
2 files changed, 52 insertions, 8 deletions
diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h index 1fef028285f9..1115b3ec10d5 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qm.h +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -969,10 +969,34 @@ #define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 #define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 #define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 - /*@}*/ -#endif /* SC_PADS_H */ +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO_PAD SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 +/*@}*/ +#endif /* SC_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h index 53c943236bf9..5fc77a03c21c 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qxp.h +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -326,7 +326,6 @@ #define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1 #define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 #define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 #define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 #define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1 #define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 @@ -349,7 +348,6 @@ #define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 #define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 #define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2 @@ -421,7 +419,6 @@ #define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2 #define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3 #define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 #define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 #define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 #define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 @@ -769,5 +766,28 @@ #define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 /*@}*/ -#endif /* SC_PADS_H */ +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +/*@}*/ +#endif /* SC_PADS_H */ |