diff options
author | Fugang Duan <b38611@freescale.com> | 2015-02-06 16:42:46 +0800 |
---|---|---|
committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 10:55:08 -0600 |
commit | daca9a1919958371c6b59ed45664d1f8751da973 (patch) | |
tree | 6515943245a69df449c67045d39b841375bdd885 /include/linux/mfd | |
parent | 0da36fc0ef6086a5ad40074ddda481cf2554c5bf (diff) |
MLK-10463-1 ARM: imx: init ENET RGMII tx clock source
Init ENET RGMII tx clock source, set GPR5[9] to select clock from
internal PLL_enet. And set phy VDDIO to 1.8V that get better signal
quality.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: d7a171fcf5218166f558428610ca8e9cb9f7e830)
Diffstat (limited to 'include/linux/mfd')
-rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d16f4c82c568..99baeb6b84e8 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -242,6 +242,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) |