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authorMyron Stowe <mstowe@redhat.com>2011-10-28 15:48:38 -0600
committerJesse Barnes <jbarnes@virtuousgeek.org>2012-01-06 12:10:42 -0800
commit96c5590058d7fded14f43af2ab521436cecf3125 (patch)
tree673577f86b1ee8886c27cc86333fdfdc6cc783ac /include/linux/pci.h
parent9cdce18d6f0baae53f012fb3f50e66e7ff24c509 (diff)
PCI: Pull PCI 'latency timer' setup up into the core
The 'latency timer' of PCI devices, both Type 0 and Type 1, is setup in architecture-specific code [see: 'pcibios_set_master()']. There are two approaches being taken by all the architectures - check if the 'latency timer' is currently set between 16 and 255 and if not bring it within bounds, or, do nothing (and then there is the gratuitously different PA-RISC implementation). There is nothing architecture-specific about PCI's 'latency timer' so this patch pulls its setup functionality up into the PCI core by creating a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. No functional change. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include/linux/pci.h')
-rw-r--r--include/linux/pci.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 569341d2d527..4c16a5788998 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -795,8 +795,11 @@ static inline int pci_is_managed(struct pci_dev *pdev)
}
void pci_disable_device(struct pci_dev *dev);
+
+extern unsigned int pcibios_max_latency;
void pci_set_master(struct pci_dev *dev);
void pci_clear_master(struct pci_dev *dev);
+
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
int pci_set_cacheline_size(struct pci_dev *dev);
#define HAVE_PCI_SET_MWI