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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2014-12-19 17:15:53 +0900
committerMark Brown <broonie@kernel.org>2014-12-24 12:31:17 +0000
commit3110628d89f80fbafa085fd62e75afcb39fb764c (patch)
treeebab30303fbc275e5ab4f7dbb5d49e829435bdd1 /include/linux/spi
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
spi: sh-msiof: Configure MSIOF sync signal timing in device tree
The MSIOF controller has DTDL and SYNCDL in SITMDR1 register. So, this patch adds new properties like the following commit: d0fb47a5237d8b9576113568bacfd27892308b62 (spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT) Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/spi')
-rw-r--r--include/linux/spi/sh_msiof.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/spi/sh_msiof.h b/include/linux/spi/sh_msiof.h
index 88a14d81c49e..b087a85f5f72 100644
--- a/include/linux/spi/sh_msiof.h
+++ b/include/linux/spi/sh_msiof.h
@@ -7,6 +7,8 @@ struct sh_msiof_spi_info {
u16 num_chipselect;
unsigned int dma_tx_id;
unsigned int dma_rx_id;
+ u32 dtdl;
+ u32 syncdl;
};
#endif /* __SPI_SH_MSIOF_H__ */