diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:34:11 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:34:11 -0700 |
| commit | 66a77d1a7cd19a6b913c30ab97870761016b0793 (patch) | |
| tree | 0973ede2c4b911bc2e55581940f6adfc690f8669 /include/uapi | |
| parent | a282f75dcc661760220a3d9ad2afb65cd0601a08 (diff) | |
| parent | b58ef08071b8bd9b65b4e24f54f3387c9803224c (diff) | |
Merge branch 'buckets/serial' into after-buckets
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/serial_reg.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index e6322605b138..8303853fd1dd 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -2,10 +2,10 @@ * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. - * - * Redistribution of this file is permitted under the terms of the GNU + * + * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) - * + * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). @@ -90,7 +90,7 @@ #define UART_LCR 3 /* Out: Line Control Register */ /* - * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ @@ -114,8 +114,10 @@ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_HW_RTS 0x40 /* Enable hw control of RTS (Tegra UART) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_HW_CTS 0x20 /* Enable HW based CTS control (Tegra UART)*/ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ |