MLK-10258-3 IMX7D: EPXP: the initial driver for the new PXP module on 7D board

This is the initial EPXP driver which can support dithering
and reagle/-D features besides the legacy pxp features.

Signed-off-by: Fancy Fang <chen.fang@freescale.com>

2 files changed, 125 insertions, 5 deletions

diff --git a/include/linux/pxp_dma.h b/include/linux/pxp_dma.h
index 0961753726aa..61e38a71d511 100644
--- a/include/linux/pxp_dma.h
+++ b/include/linux/pxp_dma.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -30,6 +30,7 @@ struct pxp_tx_desc {
 		struct pxp_layer_param s0_param;
 		struct pxp_layer_param out_param;
 		struct pxp_layer_param ol_param;
+		struct pxp_layer_param processing_param;
 	} layer_param;
 	struct pxp_proc_data proc_data;
 
@@ -45,11 +46,12 @@ struct pxp_channel {
 	void *client;		/* Only one client per channel */
 	unsigned int n_tx_desc;
 	struct pxp_tx_desc *desc;	/* allocated tx-descriptors */
+	struct list_head active_list;	/* active tx-descriptors */
+	struct list_head free_list;	/* free tx-descriptors */
 	struct list_head queue;	/* queued tx-descriptors */
 	struct list_head list;	/* track queued channel number */
-	spinlock_t lock;	/* protects sg[0,1], queue,
-				 * status, cookie, free_list
-				 */
+	spinlock_t lock;	/* protects sg[0,1], queue */
+	struct mutex chan_mutex;	/* protects status, cookie, free_list */
 	int active_buffer;
 	unsigned int eof_irq;
 	char eof_name[16];	/* EOF IRQ name for request_irq()  */
@@ -68,5 +70,13 @@ void unregister_pxp_device(void);
 int register_pxp_device(void) { return 0; }
 void unregister_pxp_device(void) {}
 #endif
+void pxp_fill(
+        u32 bpp,
+        u32 value,
+        u32 width,
+        u32 height,
+        u32 output_buffer,
+        u32 output_pitch);
 
+void m4_process(void);
 #endif
diff --git a/include/uapi/linux/pxp_dma.h b/include/uapi/linux/pxp_dma.h
index be31c47a4927..6aa013906c39 100644
--- a/include/uapi/linux/pxp_dma.h
+++ b/include/uapi/linux/pxp_dma.h
@@ -87,8 +87,27 @@ typedef unsigned char bool;
 #define PXP_LUT_BLACK_WHITE		0x2
 #define PXP_LUT_USE_CMAP		0x4
 
+/* dithering modes enum */
+#define PXP_DITHER_PASS_THROUGH 0
+#define PXP_DITHER_FLOYD	1
+#define PXP_DITHER_ATKINSON	2
+#define PXP_DITHER_ORDERED	3
+#define PXP_DITHER_QUANT_ONLY	4
+
 #define NR_PXP_VIRT_CHANNEL	16
 
+#define PXP_IOC_MAGIC  'P'
+
+#define PXP_IOC_GET_CHAN      _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc)
+#define PXP_IOC_PUT_CHAN      _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc)
+#define PXP_IOC_CONFIG_CHAN   _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc)
+#define PXP_IOC_START_CHAN    _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc)
+#define PXP_IOC_GET_PHYMEM    _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc)
+#define PXP_IOC_PUT_PHYMEM    _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc)
+#define PXP_IOC_WAIT4CMPLT    _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc)
+
+#define PXP_IOC_FILL_DATA    _IOWR(PXP_IOC_MAGIC, 7, struct pxp_mem_desc)
+
 /* Order significant! */
 enum pxp_channel_status {
 	PXP_CHANNEL_FREE,
@@ -96,6 +115,43 @@ enum pxp_channel_status {
 	PXP_CHANNEL_READY,
 };
 
+enum pxp_working_mode {
+	PXP_MODE_LEGACY			= 0x1,
+	PXP_MODE_STANDARD		= 0x2,
+	PXP_MODE_ADVANCED		= 0x4,
+};
+
+enum pxp_buffer_flag {
+	PXP_BUF_FLAG_WFE_A_FETCH0	= 0x0001,
+	PXP_BUF_FLAG_WFE_A_FETCH1	= 0x0002,
+	PXP_BUF_FLAG_WFE_A_STORE0	= 0x0004,
+	PXP_BUF_FLAG_WFE_A_STORE1	= 0x0008,
+	PXP_BUF_FLAG_WFE_B_FETCH0	= 0x0010,
+	PXP_BUF_FLAG_WFE_B_FETCH1	= 0x0020,
+	PXP_BUF_FLAG_WFE_B_STORE0	= 0x0040,
+	PXP_BUF_FLAG_WFE_B_STORE1	= 0x0080,
+	PXP_BUF_FLAG_DITHER_FETCH0	= 0x0100,
+	PXP_BUF_FLAG_DITHER_FETCH1	= 0x0200,
+	PXP_BUF_FLAG_DITHER_STORE0	= 0x0400,
+	PXP_BUF_FLAG_DITHER_STORE1	= 0x0800,
+};
+
+enum pxp_engine_ctrl {
+	PXP_ENABLE_ROTATE0		= 0x001,
+	PXP_ENABLE_ROTATE1		= 0x002,
+	PXP_ENABLE_LUT			= 0x004,
+	PXP_ENABLE_CSC2			= 0x008,
+	PXP_ENABLE_ALPHA_B		= 0x010,
+	PXP_ENABLE_INPUT_FETCH_SOTRE	= 0x020,
+	PXP_ENABLE_WFE_B		= 0x040,
+	PXP_ENABLE_WFE_A		= 0x080,
+	PXP_ENABLE_DITHER		= 0x100,
+	PXP_ENABLE_PS_AS_OUT		= 0x200,
+	PXP_ENABLE_COLLISION_DETECT     = 0x400,
+	PXP_ENABLE_HANDSHAKE		= 0x1000,
+	PXP_ENABLE_DITHER_BYPASS	= 0x2000,
+};
+
 struct rect {
 	int top;		/* Upper left coordinate of rectangle */
 	int left;
@@ -104,11 +160,14 @@ struct rect {
 };
 
 struct pxp_layer_param {
+	unsigned short left;
+	unsigned short top;
 	unsigned short width;
 	unsigned short height;
 	unsigned short stride; /* aka pitch */
 	unsigned int pixel_fmt;
 
+	unsigned int flag;
 	/* layers combining parameters
 	 * (these are ignored for S0 and output
 	 * layers, and only apply for OL layer)
@@ -122,10 +181,20 @@ struct pxp_layer_param {
 	unsigned char global_alpha;
 	bool alpha_invert;
 	bool local_alpha_enable;
+	int comp_mask;
 
 	dma_addr_t paddr;
 };
 
+struct pxp_collision_info {
+	unsigned int pixel_cnt;
+	unsigned int rect_min_x;
+	unsigned int rect_min_y;
+	unsigned int rect_max_x;
+	unsigned int rect_max_y;
+	unsigned int victim_luts[2];
+};
+
 struct pxp_proc_data {
 	/* S0 Transformation Info */
 	int scaling;
@@ -156,12 +225,54 @@ struct pxp_proc_data {
 	unsigned char *lut_map; /* 256 entries */
 	bool lut_map_updated; /* Map recently changed */
 	bool combine_enable;
+
+	/* the mode pxp's working against */
+	enum pxp_working_mode working_mode;
+	enum pxp_engine_ctrl engine_enable;
+
+	/* wfe */
+/*
+ * partial:
+ *         0 - full update
+ *         1 - partial update
+ * alpha_en:
+ *         0 - upd is {Y4[3:0],4'b0000} format
+ *         1 - upd is {Y4[3:0],3'b000,alpha} format
+ * reagl_en:
+ *         0 - use normal waveform algorithm
+ *         1 - enable reagl/-d waveform algorithm
+ * detection_only:
+ *         0 - write working buffer
+ *         1 - do no write working buffer, detection only
+ * lut:
+ *         valid value 0-63
+ *         set to the lut used for next update
+ */
+	bool partial_update;
+	bool alpha_en;
+	bool lut_update;
+	bool reagl_en;		/* enable reagl/-d */
+	bool reagl_d_en;	/* enable reagl or reagl-d */
+	bool detection_only;
+	int lut;
+	unsigned int lut_status_1;
+	unsigned int lut_status_2;
+
+	/* Dithering specific data */
+	int dither_mode;
+	unsigned int quant_bit;
 };
 
 struct pxp_config_data {
 	struct pxp_layer_param s0_param;
 	struct pxp_layer_param ol_param[8];
 	struct pxp_layer_param out_param;
+	struct pxp_layer_param wfe_a_fetch_param[2];
+	struct pxp_layer_param wfe_a_store_param[2];
+	struct pxp_layer_param wfe_b_fetch_param[2];
+	struct pxp_layer_param wfe_b_store_param[2];
+	struct pxp_layer_param dither_fetch_param[2];
+	struct pxp_layer_param dither_store_param[2];
 	struct pxp_proc_data proc_data;
 	int layer_nr;
 
@@ -169,5 +280,4 @@ struct pxp_config_data {
 	int handle;
 };
 
-
 #endif