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authorAnson Huang <b20788@freescale.com>2015-04-23 19:00:46 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-09-17 09:22:42 -0500
commit4c5b51e3fb0d5b29f1101605693ed03f04d20660 (patch)
tree7d34da948a2deca4bde3b54e922c5a294e1e2d64 /include
parent6e65fc4d6b49a106169448c57867786bfe1ba81e (diff)
MLK-10724-4 ARM: imx: add i.mx6ul msl support
i.MX6UL is a new SOC, add MSL support, including timer, clk tree and cpu etc.. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index af0dba7bf437..5e84b9815a74 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -465,4 +465,11 @@
#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
+
+/* For imx6ul iomux gpr register field define */
+#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
+#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18)
+
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */