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authorLi Jun <jun.li@freescale.com>2015-05-20 14:59:23 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-09-17 09:23:05 -0500
commitc6e1a46c521e4a1370cdd8cf1763bf891f206715 (patch)
tree7b7310385c13e3500dcc3850fd0004bd10a840a1 /include
parentab55ea181247df477aea24f6c4e555989f881b98 (diff)
MLK-10930-3 usb: chipidea: add delay if phy-clkgate-delay-us property is present
For some platforms, time delay is requried between putting PHY into low power mode and gate PHY clock. Signed-off-by: Li Jun <jun.li@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/usb/chipidea.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index 97f0b5c61bac..d1f8f550766f 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -49,6 +49,7 @@ struct ci_hdrc_platform_data {
bool tpl_support;
u32 ahbburst_config;
u32 burst_length;
+ u32 phy_clkgate_delay_us;
};
/* Default offset of capability registers */