diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-08-10 20:28:59 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-08-10 16:04:20 -0700 |
| commit | 219f2250a35ae6590268943a83508da8370085a2 (patch) | |
| tree | 8b11b0b53a45d6ad1c956b43abb23349f4fdd3e6 /include | |
| parent | fa1a2809608379d9c839700c83c2b3cce4c83392 (diff) | |
mmc: sdio: Adding SDIO 3.0 support
Adding SDIO 3.0 support. Adding support for
voltage switch, bus speed mode selection,
8 bit buswidth support and frequency tuning.
Bug 853800
Change-Id: Ie778b7d67f2f09a9840cc8576d1dc750f18c7978
Reviewed-on: http://git-master/r/46388
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mmc/card.h | 7 | ||||
| -rw-r--r-- | include/linux/mmc/sdio.h | 12 |
2 files changed, 17 insertions, 2 deletions
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 832e494296c3..9ef70d49296b 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -80,9 +80,13 @@ struct sdio_cccr { unsigned int multi_block:1, low_speed:1, wide_bus:1, + wide_8bitbus:1, high_power:1, high_speed:1, - disable_cd:1; + disable_cd:1, + uhs_sdr104:1, + uhs_sdr50:1, + uhs_ddr50:1; }; struct sdio_cis { @@ -123,6 +127,7 @@ struct mmc_card { /* (missing CIA registers) */ #define MMC_QUIRK_INAND_CMD38 (1<<3) /* iNAND devices have broken CMD38 */ + unsigned char bus_width; /* bus width configured */ unsigned char bus_speed; /* bus speed mode */ unsigned int erase_size; /* erase size in sectors */ unsigned int erase_shift; /* if erase unit is power 2 */ diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 245cdacee544..afb03af2153f 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -71,12 +71,14 @@ #define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */ #define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */ -#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */ +#define SDIO_CCCR_REV_2_00 2 /* CCCR/FBR Version 1.20 */ +#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 1.20 */ #define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */ #define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */ #define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */ #define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */ +#define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */ #define SDIO_CCCR_SD 0x01 @@ -96,6 +98,8 @@ #define SDIO_BUS_WIDTH_1BIT 0x00 #define SDIO_BUS_WIDTH_4BIT 0x02 +#define SDIO_BUS_WIDTH_8BIT 0x03 +#define SDIO_CCCR_IF_CAP_8BIT 0x04 #define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */ #define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */ @@ -134,6 +138,12 @@ #define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */ #define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */ +#define SDIO_CCCR_UHS_SUPPORT 0x14 +#define SDIO_UHS_SUPPORT_SDR50 0x01 +#define SDIO_UHS_SUPPORT_SDR104 0x02 +#define SDIO_UHS_SUPPORT_DDR50 0x04 +#define SDIO_UHS_SUPPORT_MASK 0x0E + /* * Function Basic Registers (FBR) */ |