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authorIgor Nabirushkin <inabirushkin@nvidia.com>2014-10-20 00:22:32 +0400
committerWinnie Hsu <whsu@nvidia.com>2015-01-29 22:02:49 -0800
commitcd2cd13dc3161d4b3362c2a94dc2442d7e1631fa (patch)
tree16b28b80500b2d832df652b79cb18f79f2222722 /include
parentd075eb663ba4bd87b64cfba88a79c01c92049619 (diff)
misc: tegra-profiler: use mmap for samples
Tegra Profiler: send samples via memory mapping areas to the user space. Bug 1566270 Bug 1598009 Change-Id: I19aae4ca1f8d6a3ae7c36e99fb018d8fcd2152d3 Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com> Reviewed-on: http://git-master/r/559124 (cherry picked from commit 1a53b2fc3f15aeed1eee0f9aa6e259ae476acb82) Reviewed-on: http://git-master/r/672026 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/tegra_profiler.h53
1 files changed, 51 insertions, 2 deletions
diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h
index 5434d58ceae4..affbec553a69 100644
--- a/include/linux/tegra_profiler.h
+++ b/include/linux/tegra_profiler.h
@@ -1,7 +1,7 @@
/*
* include/linux/tegra_profiler.h
*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -20,7 +20,7 @@
#include <linux/ioctl.h>
#define QUADD_SAMPLES_VERSION 30
-#define QUADD_IO_VERSION 13
+#define QUADD_IO_VERSION 14
#define QUADD_IO_VERSION_DYNAMIC_RB 5
#define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
@@ -31,6 +31,7 @@
#define QUADD_IO_VERSION_UNWIND_MIXED 11
#define QUADD_IO_VERSION_EXTABLES_MMAP 12
#define QUADD_IO_VERSION_ARCH_TIMER_OPT 13
+#define QUADD_IO_VERSION_DATA_MMAP 14
#define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
#define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
@@ -45,6 +46,8 @@
#define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29
#define QUADD_SAMPLE_VERSION_HDR_ARCH_TIMER 30
+#define QUADD_MMAP_HEADER_VERSION 1
+
#define QUADD_MAX_COUNTERS 32
#define QUADD_MAX_PROCESS 64
@@ -91,6 +94,11 @@
*/
#define IOCTL_SET_EXTAB _IOW(QUADD_IOCTL, 6, struct quadd_extables)
+/*
+ * Send ring buffer mmap info
+ */
+#define IOCTL_SET_MMAP_RB _IOW(QUADD_IOCTL, 7, struct quadd_mmap_rb_info)
+
#define QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP (1 << 29) /* LP CPU */
#define QUADD_CPUMODE_THUMB (1 << 30) /* thumb mode */
@@ -395,6 +403,7 @@ enum {
#define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED (1 << 6)
#define QUADD_COMM_CAP_EXTRA_UNW_ENTRY_TYPE (1 << 7)
#define QUADD_COMM_CAP_EXTRA_ARCH_TIMER (1 << 8)
+#define QUADD_COMM_CAP_EXTRA_RB_MMAP_OP (1 << 9)
struct quadd_comm_cap {
u32 pmu:1,
@@ -458,6 +467,46 @@ struct quadd_extables {
u32 reserved[4]; /* reserved fields for future extensions */
};
+struct quadd_mmap_rb_info {
+ u32 cpu_id;
+
+ u64 vm_start;
+ u64 vm_end;
+
+ u32 reserved[4]; /* reserved fields for future extensions */
+};
+
+#define QUADD_MMAP_HEADER_MAGIC 0x33445566
+
+struct quadd_mmap_header {
+ u32 magic;
+ u32 version;
+
+ u32 cpu_id;
+ u32 samples_version;
+
+ u32 reserved[4]; /* reserved fields for future extensions */
+} __aligned(8);
+
+enum {
+ QUADD_RB_STATE_NONE = 0,
+ QUADD_RB_STATE_ACTIVE,
+ QUADD_RB_STATE_STOPPED,
+};
+
+struct quadd_ring_buffer_hdr {
+ u32 state;
+ u32 size;
+
+ u32 pos_read;
+ u32 pos_write;
+
+ u32 max_fill_count;
+ u32 skipped_samples;
+
+ u32 reserved[4]; /* reserved fields for future extensions */
+} __aligned(8);
+
#pragma pack(pop)
#ifdef __KERNEL__