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authorMichel Dänzer <michel.daenzer@amd.com>2013-09-18 18:23:51 +0200
committerAlex Deucher <alexander.deucher@amd.com>2013-09-20 17:33:40 -0400
commit42baf21d91d4f52f5b9a4d11dc8e7b1e3b93de7c (patch)
tree78f1c6e6a17ddf080afe7a6c30ab0415a959c83c /include
parenta537314e0b539e22934d3cffeb0b1f476e56491c (diff)
drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces
CIK uses a different index for 1D DST surfaces compared to SI. Expose the new index so libdrm_radeon can use it properly for userspace drivers. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/drm/radeon_drm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index fa8b3adf9ffb..46d41e8b0dcc 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -1007,4 +1007,6 @@ struct drm_radeon_info {
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
+#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
+
#endif