ENGR00065563 Driver and MSL updates for 2.6.24

14 files changed, 456 insertions, 794 deletions

diff --git a/include/asm-arm/arch-mxc/arc_otg.h b/include/asm-arm/arch-mxc/arc_otg.h
index f896d4d3289d..cade9521ddb1 100644
--- a/include/asm-arm/arch-mxc/arc_otg.h
+++ b/include/asm-arm/arch-mxc/arc_otg.h
@@ -209,16 +209,6 @@
 #define  OTGSC_INTERRUPT_STATUS_BITS_MASK	OTGSC_IS_MASK
 #endif
 
-/* x_USBMODE */
-#define USBMODE_SDIS		(1 << 4)	/* stream disable mode */
-#define USBMODE_SLOM		(1 << 3)	/* setup lockout mode */
-#define USBMODE_ES		(1 << 2)	/* (big) endian select */
-#define USBMODE_CM_MASK		(3 << 0)	/* controller mode mask */
-#define USBMODE_CM_HOST		(3 << 0)	/* host */
-#define USBMODE_CM_DEVICE	(2 << 0)	/* device */
-#define USBMODE_CM_reserved	(1 << 0)	/* reserved */
-#define USBMODE_CM_IDLE		(0 << 0)	/* idle */
-
 /* USBCTRL */
 #define UCTRL_OWIR		(1 << 31)	/* OTG wakeup intr request received */
 #define UCTRL_OSIC_MASK		(3 << 29)	/* OTG  Serial Interface Config: */
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
index 65e639d51d2b..41997e6c8bfe 100644
--- a/include/asm-arm/arch-mxc/dma.h
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -12,10 +12,244 @@
 #define __ASM_ARCH_MXC_DMA_H__
 
 /*!
- * @file dma.h
+ * @file arch-mxc/dma.h
  * @brief This file contains Unified DMA API for all MXC platforms.
  * The API is platform independent.
  *
  * @ingroup SDMA
  */
+#define MXC_DMA_DYNAMIC_CHANNEL   255
+
+#define MXC_DMA_DONE		  0x0
+#define MXC_DMA_REQUEST_TIMEOUT   0x1
+#define MXC_DMA_TRANSFER_ERROR    0x2
+
+/*! This defines the list of device ID's for DMA */
+typedef enum mxc_dma_device {
+	MXC_DMA_UART1_RX,
+	MXC_DMA_UART1_TX,
+	MXC_DMA_UART2_RX,
+	MXC_DMA_UART2_TX,
+	MXC_DMA_UART3_RX,
+	MXC_DMA_UART3_TX,
+	MXC_DMA_UART4_RX,
+	MXC_DMA_UART4_TX,
+	MXC_DMA_UART5_RX,
+	MXC_DMA_UART5_TX,
+	MXC_DMA_UART6_RX,
+	MXC_DMA_UART6_TX,
+	MXC_DMA_MMC1_WIDTH_1,
+	MXC_DMA_MMC1_WIDTH_4,
+	MXC_DMA_MMC2_WIDTH_1,
+	MXC_DMA_MMC2_WIDTH_4,
+	MXC_DMA_SSI1_8BIT_RX0,
+	MXC_DMA_SSI1_8BIT_TX0,
+	MXC_DMA_SSI1_16BIT_RX0,
+	MXC_DMA_SSI1_16BIT_TX0,
+	MXC_DMA_SSI1_24BIT_RX0,
+	MXC_DMA_SSI1_24BIT_TX0,
+	MXC_DMA_SSI1_8BIT_RX1,
+	MXC_DMA_SSI1_8BIT_TX1,
+	MXC_DMA_SSI1_16BIT_RX1,
+	MXC_DMA_SSI1_16BIT_TX1,
+	MXC_DMA_SSI1_24BIT_RX1,
+	MXC_DMA_SSI1_24BIT_TX1,
+	MXC_DMA_SSI2_8BIT_RX0,
+	MXC_DMA_SSI2_8BIT_TX0,
+	MXC_DMA_SSI2_16BIT_RX0,
+	MXC_DMA_SSI2_16BIT_TX0,
+	MXC_DMA_SSI2_24BIT_RX0,
+	MXC_DMA_SSI2_24BIT_TX0,
+	MXC_DMA_SSI2_8BIT_RX1,
+	MXC_DMA_SSI2_8BIT_TX1,
+	MXC_DMA_SSI2_16BIT_RX1,
+	MXC_DMA_SSI2_16BIT_TX1,
+	MXC_DMA_SSI2_24BIT_RX1,
+	MXC_DMA_SSI2_24BIT_TX1,
+	MXC_DMA_FIR_RX,
+	MXC_DMA_FIR_TX,
+	MXC_DMA_CSPI1_RX,
+	MXC_DMA_CSPI1_TX,
+	MXC_DMA_CSPI2_RX,
+	MXC_DMA_CSPI2_TX,
+	MXC_DMA_CSPI3_RX,
+	MXC_DMA_CSPI3_TX,
+	MXC_DMA_ATA_RX,
+	MXC_DMA_ATA_TX,
+	MXC_DMA_MEMORY,
+	MXC_DMA_DSP_PACKET_DATA0_RD,
+	MXC_DMA_DSP_PACKET_DATA0_WR,
+	MXC_DMA_DSP_PACKET_DATA1_RD,
+	MXC_DMA_DSP_PACKET_DATA1_WR,
+	MXC_DMA_DSP_LOG0_CHNL,
+	MXC_DMA_DSP_LOG1_CHNL,
+	MXC_DMA_DSP_LOG2_CHNL,
+	MXC_DMA_DSP_LOG3_CHNL,
+	MXC_DMA_CSI_RX,
+	MXC_DMA_TEST_RAM2D2RAM,
+	MXC_DMA_TEST_RAM2RAM2D,
+	MXC_DMA_TEST_RAM2D2RAM2D,
+	MXC_DMA_TEST_RAM2RAM,
+	MXC_DMA_TEST_HW_CHAINING,
+	MXC_DMA_TEST_SW_CHAINING
+} mxc_dma_device_t;
+
+/*! This defines the prototype of callback funtion registered by the drivers */
+typedef void (*mxc_dma_callback_t) (void *arg, int error_status,
+				    unsigned int count);
+
+/*! This defines the type of DMA transfer requested */
+typedef enum mxc_dma_mode {
+	MXC_DMA_MODE_READ,
+	MXC_DMA_MODE_WRITE,
+} mxc_dma_mode_t;
+
+/*! This defines the DMA channel parameters */
+typedef struct mxc_dma_channel {
+	unsigned int active:1;	/*!< When there has a active tranfer, it is set to 1 */
+	unsigned int lock;	/*!< Defines the channel is allocated or not */
+	int curr_buf;		/*!< Current buffer */
+	mxc_dma_mode_t mode;	/*!< Read or Write */
+	unsigned int channel;	/*!< Channel info */
+	unsigned int dynamic:1;	/*!< Channel not statically allocated when 1 */
+	char *dev_name;		/*!< Device name */
+	void *private;		/*!< Private structure for platform */
+	mxc_dma_callback_t cb_fn;	/*!< The callback function */
+	void *cb_args;		/*!< The argument of callback function */
+} mxc_dma_channel_t;
+
+/*! This structure contains the information about a dma transfer */
+typedef struct mxc_dma_requestbuf {
+	dma_addr_t src_addr;	/*!< source address */
+	dma_addr_t dst_addr;	/*!< destination address */
+	int num_of_bytes;	/*!< the length of this transfer : bytes */
+} mxc_dma_requestbuf_t;
+
+#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX21)
+#include <asm/arch/mx2_dma.h>
+#else
+#include <asm/arch/sdma.h>
+#endif
+
+/*!
+ * This function is generally called by the driver at open time.
+ * The DMA driver would do any initialization steps that is required
+ * to get the channel ready for data transfer.
+ *
+ * @param channel_id   a pre-defined id. The peripheral driver would specify
+ *                     the id associated with its peripheral. This would be
+ *                     used by the DMA driver to identify the peripheral
+ *                     requesting DMA and do the necessary setup on the
+ *                     channel associated with the particular peripheral.
+ *                     The DMA driver could use static or dynamic DMA channel
+ *                     allocation.
+ * @param dev_name     module name or device name
+ * @return returns a negative number on error if request for a DMA channel did not
+ *         succeed, returns the channel number to be used on success.
+ */
+extern int mxc_dma_request(mxc_dma_device_t channel_id, char *dev_name);
+
+/*!
+ * This function is generally called by the driver at close time. The DMA
+ * driver would do any cleanup associated with this channel.
+ *
+ * @param channel_num  the channel number returned at request time. This
+ *                     would be used by the DMA driver to identify the calling
+ *                     driver and do the necessary cleanup on the channel
+ *                     associated with the particular peripheral
+ * @return returns a negative number on error or 0 on success
+ */
+extern int mxc_dma_free(int channel_num);
+
+/*!
+ * This function would just configure the buffers specified by the user into
+ * dma channel. The caller must call mxc_dma_enable to start this transfer.
+ *
+ * @param channel_num  the channel number returned at request time. This
+ *                     would be used by the DMA driver to identify the calling
+ *                     driver and do the necessary cleanup on the channel
+ *                     associated with the particular peripheral
+ * @param dma_buf      an array of physical addresses to the user defined
+ *                     buffers. The caller must guarantee the dma_buf is
+ *                     available until the transfer is completed.
+ * @param num_buf      number of buffers in the array
+ * @param mode         specifies whether this is READ or WRITE operation
+ * @return This function returns a negative number on error if buffer could not be
+ *         added with DMA for transfer. On Success, it returns 0
+ */
+extern int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t * dma_buf,
+			  int num_buf, mxc_dma_mode_t mode);
+
+/*!
+ * This function would just configure the scatterlist specified by the
+ * user into dma channel. This is a slight variation of mxc_dma_config(),
+ * it is provided for the convenience of drivers that have a scatterlist
+ * passed into them. It is the calling driver's responsibility to have the
+ * correct physical address filled in the "dma_address" field of the
+ * scatterlist.
+ *
+ * @param channel_num  the channel number returned at request time. This
+ *                     would be used by the DMA driver to identify the calling
+ *                     driver and do the necessary cleanup on the channel
+ *                     associated with the particular peripheral
+ * @param sg           a scatterlist of buffers. The caller must guarantee
+ *                     the dma_buf is available until the transfer is
+ *                     completed.
+ * @param num_buf      number of buffers in the array
+ * @param num_of_bytes total number of bytes to transfer. If set to 0, this
+ *                     would imply to use the length field of the scatterlist
+ *                     for each DMA transfer. Else it would calculate the size
+ *                     for each DMA transfer.
+ * @param mode         specifies whether this is READ or WRITE operation
+ * @return This function returns a negative number on error if buffer could not
+ *         be added with DMA for transfer. On Success, it returns 0
+ */
+extern int mxc_dma_sg_config(int channel_num, struct scatterlist *sg,
+			     int num_buf, int num_of_bytes,
+			     mxc_dma_mode_t mode);
+
+/*!
+ * This function is provided if the driver would like to set/change its
+ * callback function.
+ *
+ * @param channel_num  the channel number returned at request time. This
+ *                     would be used by the DMA driver to identify the calling
+ *                     driver and do the necessary cleanup on the channel
+ *                     associated with the particular peripheral
+ * @param callback     a callback function to provide notification on transfer
+ *                     completion, user could specify NULL if he does not wish
+ *                     to be notified
+ * @param arg          an argument that gets passed in to the callback
+ *                     function, used by the user to do any driver specific
+ *                     operations.
+ * @return this function returns a negative number on error if the callback
+ *         could not be set for the channel or 0 on success
+ */
+extern int mxc_dma_callback_set(int channel_num, mxc_dma_callback_t callback,
+				void *arg);
+
+/*!
+ * This stops the DMA channel and any ongoing transfers. Subsequent use of
+ * mxc_dma_enable() will restart the channel and restart the transfer.
+ *
+ * @param channel_num  the channel number returned at request time. This
+ *                     would be used by the DMA driver to identify the calling
+ *                     driver and do the necessary cleanup on the channel
+ *                     associated with the particular peripheral
+ * @return returns a negative number on error or 0 on success
+ */
+extern int mxc_dma_disable(int channel_num);
+
+/*!
+ * This starts DMA transfer. Or it restarts DMA on a stopped channel
+ * previously stopped with mxc_dma_disable().
+ *
+ * @param channel_num  the channel number returned at request time. This
+ *                     would be used by the DMA driver to identify the calling
+ *                     driver and do the necessary cleanup on the channel
+ *                     associated with the particular peripheral
+ * @return returns a negative number on error or 0 on success
+ */
+extern int mxc_dma_enable(int channel_num);
+
 #endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
index f0f34adf24f0..23ae035e60bf 100644
--- a/include/asm-arm/arch-mxc/entry-macro.S
+++ b/include/asm-arm/arch-mxc/entry-macro.S
@@ -9,6 +9,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <asm/hardware.h>
+
 	@ this macro disables fast irq (not implemented)
 	.macro	disable_fiq
 	.endm
diff --git a/include/asm-arm/arch-mxc/fsl_usb.h b/include/asm-arm/arch-mxc/fsl_usb.h
deleted file mode 100644
index ec50f1895108..000000000000
--- a/include/asm-arm/arch-mxc/fsl_usb.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <asm/arch/arc_otg.h>
-
-/* ehci_arc_hc_driver.flags value */
-#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY)
-
-static inline int fsl_platform_verify(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static inline void fsl_platform_usb_setup(struct usb_hcd *hcd)
-{
-}
-
-static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
-{
-	unsigned int temp;
-	struct fsl_usb2_platform_data *pdata;
-
-	pdata =
-	    (struct fsl_usb2_platform_data *)hcd->self.controller->
-	    platform_data;
-
-	if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
-		pdata->xcvr_ops->set_host();
-
-	/* set host mode */
-	temp = readl(hcd->regs + 0x1a8);
-	writel(temp | USBMODE_CM_HOST, hcd->regs + 0x1a8);
-}
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index 23dead106242..531afd775b9c 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -29,8 +29,8 @@
 
 #define MXC_IRQ_TO_EXPIO(irq)	(irq - MXC_EXP_IO_BASE)
 
-#define MXC_IRQ_TO_GPIO(irq)	(irq - MXC_GPIO_BASE)
-#define MXC_GPIO_TO_IRQ(x)	(MXC_GPIO_BASE + x)
+#define MXC_IRQ_TO_GPIO(irq)	(irq - MXC_GPIO_INT_BASE)
+#define MXC_GPIO_TO_IRQ(x)	(MXC_GPIO_INT_BASE + x)
 
 /*!
  * Number of normal interrupts
diff --git a/include/asm-arm/arch-mxc/mx21.h b/include/asm-arm/arch-mxc/mx21.h
index 4e332c81aa93..85c7fcb236f7 100644
--- a/include/asm-arm/arch-mxc/mx21.h
+++ b/include/asm-arm/arch-mxc/mx21.h
@@ -188,61 +188,61 @@
 /*
  *  MX21 ADS Interrupt numbers
  */
-#define INT_CSPI3 	            6
-#define INT_GPIO                    8
-#define INT_FIRI                    9
-#define INT_SDHC2                   10
-#define INT_SDHC1                   11
-#define INT_I2C                     12
-#define INT_SSI2                    13
-#define INT_SSI1                    14
-#define INT_CSPI2                   15
-#define INT_CSPI1              	    16
-#define INT_UART4                   17
-#define INT_UART3                   18
-#define INT_UART2                   19
-#define INT_UART1                   20
-#define INT_KPP                     21
-#define INT_RTC		            22
-#define INT_PWM                     23
-#define INT_GPT3                    24
-#define INT_GPT2                    25
-#define INT_GPT1                    26
-#define INT_GPT                     INT_GPT1
-#define INT_WDOG                    27
-#define INT_PCMCIA                  28
-#define INT_NANDFC                  29
-#define INT_BMI                     30
-#define INT_CSI                     31
-#define INT_DMACH0                  32
-#define INT_DMACH1                  33
-#define INT_DMACH2                  34
-#define INT_DMACH3                  35
-#define INT_DMACH4                  36
-#define INT_DMACH5                  37
-#define INT_DMACH6                  38
-#define INT_DMACH7                  39
-#define INT_DMACH8                  40
-#define INT_DMACH9                  41
-#define INT_DMACH10                 42
-#define INT_DMACH11                 43
-#define INT_DMACH12                 44
-#define INT_DMACH13                 45
-#define INT_DMACH14                 46
-#define INT_DMACH15                 47
-#define INT_EMMAENC                 49
-#define INT_EMMADEC                 50
-#define INT_EMMAPRP                 51
-#define INT_EMMAPP                  52
-#define INT_USBWKUP                 53
-#define INT_USBDMA                  54
-#define INT_USBHOST                 55
-#define INT_USBFUNC                 56
-#define INT_USBHNP                  57
-#define INT_USBCTRL                 58
-#define INT_SAHARA                  59
-#define INT_SLCDC                   60
-#define INT_LCDC                    61
+#define MXC_INT_CSPI3 	            6
+#define MXC_INT_GPIO                    8
+#define MXC_INT_FIRI                    9
+#define MXC_INT_SDHC2                   10
+#define MXC_INT_SDHC1                   11
+#define MXC_INT_I2C                     12
+#define MXC_INT_SSI2                    13
+#define MXC_INT_SSI1                    14
+#define MXC_INT_CSPI2                   15
+#define MXC_INT_CSPI1              	    16
+#define MXC_INT_UART4                   17
+#define MXC_INT_UART3                   18
+#define MXC_INT_UART2                   19
+#define MXC_INT_UART1                   20
+#define MXC_INT_KPP                     21
+#define MXC_INT_RTC		            22
+#define MXC_INT_PWM                     23
+#define MXC_INT_GPT3                    24
+#define MXC_INT_GPT2                    25
+#define MXC_INT_GPT1                    26
+#define MXC_INT_GPT                     INT_GPT1
+#define MXC_INT_WDOG                    27
+#define MXC_INT_PCMCIA                  28
+#define MXC_INT_NANDFC                  29
+#define MXC_INT_BMI                     30
+#define MXC_INT_CSI                     31
+#define MXC_INT_DMACH0                  32
+#define MXC_INT_DMACH1                  33
+#define MXC_INT_DMACH2                  34
+#define MXC_INT_DMACH3                  35
+#define MXC_INT_DMACH4                  36
+#define MXC_INT_DMACH5                  37
+#define MXC_INT_DMACH6                  38
+#define MXC_INT_DMACH7                  39
+#define MXC_INT_DMACH8                  40
+#define MXC_INT_DMACH9                  41
+#define MXC_INT_DMACH10                 42
+#define MXC_INT_DMACH11                 43
+#define MXC_INT_DMACH12                 44
+#define MXC_INT_DMACH13                 45
+#define MXC_INT_DMACH14                 46
+#define MXC_INT_DMACH15                 47
+#define MXC_INT_EMMAENC                 49
+#define MXC_INT_EMMADEC                 50
+#define MXC_INT_EMMAPRP                 51
+#define MXC_INT_EMMAPP                  52
+#define MXC_INT_USBWKUP                 53
+#define MXC_INT_USBDMA                  54
+#define MXC_INT_USBHOST                 55
+#define MXC_INT_USBFUNC                 56
+#define MXC_INT_USBHNP                  57
+#define MXC_INT_USBCTRL                 58
+#define MXC_INT_SAHARA                  59
+#define MXC_INT_SLCDC                   60
+#define MXC_INT_LCDC                    61
 
 #define MXC_MAX_INT_LINES       64
 #define MXC_MAX_EXT_LINES       0
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
index 7dc37ea0ab1f..0bb3752be5f2 100644
--- a/include/asm-arm/arch-mxc/mx27.h
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -65,7 +65,7 @@
  *  Register offests.
  */
 #define AIPI_BASE_ADDR          0x10000000
-#define AIPI_BASE_ADDR_VIRT     0xD4000000
+#define AIPI_BASE_ADDR_VIRT     0xFC000000
 #define AIPI_SIZE               SZ_1M
 
 #define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
@@ -130,7 +130,7 @@
 #define AVIC_BASE_ADDR          0x10040000
 
 #define SAHB1_BASE_ADDR         0x80000000
-#define SAHB1_BASE_ADDR_VIRT    0xD4100000
+#define SAHB1_BASE_ADDR_VIRT    0xFC100000
 #define SAHB1_SIZE              SZ_1M
 
 #define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
@@ -140,7 +140,7 @@
  * NAND, SDRAM, WEIM, M3IF, EMI controllers
  */
 #define X_MEMC_BASE_ADDR        0xD8000000
-#define X_MEMC_BASE_ADDR_VIRT   0xD4200000
+#define X_MEMC_BASE_ADDR_VIRT   0xFC200000
 #define X_MEMC_SIZE             SZ_1M
 
 #define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
@@ -160,7 +160,7 @@
 #define CS2_BASE_ADDR           0xD0000000
 #define CS3_BASE_ADDR           0xD2000000
 #define CS4_BASE_ADDR           0xD4000000
-#define CS4_BASE_ADDR_VIRT      0xEB000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
 #define CS4_SIZE                SZ_1M
 #define CS5_BASE_ADDR           0xD6000000
 #define PCMCIA_MEM_BASE_ADDR    0xDC000000
@@ -204,76 +204,76 @@
 /*
  *  MX27 ADS Interrupt numbers
  */
-#define INT_CCM                 63
-#define INT_IIM                 62
-#define INT_LCDC                61
-#define INT_SLCDC               60
-#define INT_SAHARA              59
-#define INT_SCC_SCM             58
-#define INT_SCC_SMN             57
-#define INT_USB3                56
-#define INT_USB2                55
-#define INT_USB1                54
-#define INT_VPU                53
-#define INT_EMMAPP              52
-#define INT_EMMAPRP             51
-#define INT_FEC                 50
-#define INT_UART5               49
-#define INT_UART6               48
-#define INT_DMACH15             47
-#define INT_DMACH14             46
-#define INT_DMACH13             45
-#define INT_DMACH12             44
-#define INT_DMACH11             43
-#define INT_DMACH10             42
-#define INT_DMACH9              41
-#define INT_DMACH8              40
-#define INT_DMACH7              39
-#define INT_DMACH6              38
-#define INT_DMACH5              37
-#define INT_DMACH4              36
-#define INT_DMACH3              35
-#define INT_DMACH2              34
-#define INT_DMACH1              33
-#define INT_DMACH0              32
-#define INT_CSI                 31
-#define INT_ATA                 30
-#define INT_NANDFC              29
-#define INT_PCMCIA              28
-#define INT_WDOG                27
-#define INT_GPT1                26
-#define INT_GPT2                25
-#define INT_GPT3                24
-#define INT_GPT                 INT_GPT1
-#define INT_PWM                 23
-#define INT_RTC                 22
-#define INT_KPP                 21
-#define INT_UART1               20
-#define INT_UART2               19
-#define INT_UART3               18
-#define INT_UART4               17
-#define INT_CSPI1               16
-#define INT_CSPI2               15
-#define INT_SSI1                14
-#define INT_SSI2                13
-#define INT_I2C                 12
-#define INT_SDHC1               11
-#define INT_SDHC2               10
-#define INT_SDHC3               9
-#define INT_GPIO                8
-#define INT_SDHC                7
-#define INT_CSPI3               6
-#define INT_RTIC                5
-#define INT_GPT4                4
-#define INT_GPT5                3
-#define INT_GPT6                2
-#define INT_I2C2                1
+#define MXC_INT_CCM                 63
+#define MXC_INT_IIM                 62
+#define MXC_INT_LCDC                61
+#define MXC_INT_SLCDC               60
+#define MXC_INT_SAHARA              59
+#define MXC_INT_SCC_SCM             58
+#define MXC_INT_SCC_SMN             57
+#define MXC_INT_USB3                56
+#define MXC_INT_USB2                55
+#define MXC_INT_USB1                54
+#define MXC_INT_VPU                53
+#define MXC_INT_EMMAPP              52
+#define MXC_INT_EMMAPRP             51
+#define MXC_INT_FEC                 50
+#define MXC_INT_UART5               49
+#define MXC_INT_UART6               48
+#define MXC_INT_DMACH15             47
+#define MXC_INT_DMACH14             46
+#define MXC_INT_DMACH13             45
+#define MXC_INT_DMACH12             44
+#define MXC_INT_DMACH11             43
+#define MXC_INT_DMACH10             42
+#define MXC_INT_DMACH9              41
+#define MXC_INT_DMACH8              40
+#define MXC_INT_DMACH7              39
+#define MXC_INT_DMACH6              38
+#define MXC_INT_DMACH5              37
+#define MXC_INT_DMACH4              36
+#define MXC_INT_DMACH3              35
+#define MXC_INT_DMACH2              34
+#define MXC_INT_DMACH1              33
+#define MXC_INT_DMACH0              32
+#define MXC_INT_CSI                 31
+#define MXC_INT_ATA                 30
+#define MXC_INT_NANDFC              29
+#define MXC_INT_PCMCIA              28
+#define MXC_INT_WDOG                27
+#define MXC_INT_GPT1                26
+#define MXC_INT_GPT2                25
+#define MXC_INT_GPT3                24
+#define MXC_INT_GPT                 MXC_INT_GPT1
+#define MXC_INT_PWM                 23
+#define MXC_INT_RTC                 22
+#define MXC_INT_KPP                 21
+#define MXC_INT_UART1               20
+#define MXC_INT_UART2               19
+#define MXC_INT_UART3               18
+#define MXC_INT_UART4               17
+#define MXC_INT_CSPI1               16
+#define MXC_INT_CSPI2               15
+#define MXC_INT_SSI1                14
+#define MXC_INT_SSI2                13
+#define MXC_INT_I2C                 12
+#define MXC_INT_SDHC1               11
+#define MXC_INT_SDHC2               10
+#define MXC_INT_SDHC3               9
+#define MXC_INT_GPIO                8
+#define MXC_INT_SDHC                7
+#define MXC_INT_CSPI3               6
+#define MXC_INT_RTIC                5
+#define MXC_INT_GPT4                4
+#define MXC_INT_GPT5                3
+#define MXC_INT_GPT6                2
+#define MXC_INT_I2C2                1
 
 #define MXC_MAX_INT_LINES       64
 #define MXC_MAX_EXT_LINES       0
 
 #define MXC_MUX_GPIO_INTERRUPTS 1
-#define MXC_GPIO_BASE           (MXC_MAX_INT_LINES)
+#define MXC_GPIO_INT_BASE	(MXC_MAX_INT_LINES)
 
 /*!
  * Number of GPIO port as defined in the IC Spec
@@ -335,10 +335,4 @@
 
 #define NFMS_BIT 5
 
-/*
- * GPT clock source mask and offset bit definition
- */
-#define GPT_CTRL_MASK           0xFFFFFFF1
-#define GPT_CTRL_OFFSET	    	1
-
 #endif				/* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 46be9d54d71b..c77228443b50 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -377,7 +377,7 @@
 #define MXC_INT_IIM		19
 #define MXC_INT_SIM2		20
 #define MXC_INT_SIM1		21
-#define MXC_INT_RNGA		22
+#define MXC_INT_RNG		22
 #define MXC_INT_EVTMON		23
 #define MXC_INT_KPP		24
 #define MXC_INT_RTC		25
@@ -427,7 +427,7 @@
 /*!
  * Interrupt Number for ARM11 PMU
  */
-#define ARM11_PMU_IRQ		INT_EVTMON
+#define ARM11_PMU_IRQ		MXC_INT_EVTMON
 
 /*!
  * Number of GPIO port as defined in the IC Spec
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 81760e742a8f..4872b64a43ad 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -92,7 +92,7 @@ int mxc_snoop_get_status(u32 num, u32 * statl, u32 * stath);
 #endif				/* __ASSEMBLY__ */
 
 #define IOMUX_TO_GPIO(pin) 	((((unsigned int)pin >> MUX_IO_P) * GPIO_NUM_PIN) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) -1)))
-#define IOMUX_TO_IRQ(pin)	(MXC_GPIO_BASE + IOMUX_TO_GPIO(pin))
+#define IOMUX_TO_IRQ(pin)	(MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
 #define GPIO_TO_PORT(n)		(n / GPIO_NUM_PIN)
 #define GPIO_TO_INDEX(n)	(n % GPIO_NUM_PIN)
 
diff --git a/include/asm-arm/arch-mxc/mxc91321.h b/include/asm-arm/arch-mxc/mxc91321.h
index be1c15a4dd0d..a39da0c87548 100644
--- a/include/asm-arm/arch-mxc/mxc91321.h
+++ b/include/asm-arm/arch-mxc/mxc91321.h
@@ -26,7 +26,7 @@
  * @ingroup MSL_MXC91321
  */
 /*!
- * defines the OS clock tick rate
+ * defines the hardware clock tick rate
  */
 #define CLOCK_TICK_RATE         16625000
 
@@ -59,7 +59,7 @@
  * IRAM
  */
 #define IRAM_BASE_ADDR          0x1FFFC000
-#define IRAM_BASE_ADDR_VIRT     0xD0000000
+#define IRAM_BASE_ADDR_VIRT     0xF8000000
 #define IRAM_SIZE               SZ_16K
 
 /*
@@ -71,22 +71,23 @@
  * SMC
  */
 #define SMC_BASE_ADDR          0x40000000
-#define SMC_BASE_ADDR_VIRT     0xD2000000
+#define SMC_BASE_ADDR_VIRT     0xF5000000
 #define SMC_SIZE               SZ_16M
 
 /*
  * SiRF
  */
 #define SIRF_BASE_ADDR          0x42000000
-#define SIRF_BASE_ADDR_VIRT     0xD3000000
+#define SIRF_BASE_ADDR_VIRT     0xF6000000
 #define SIRF_SIZE               SZ_16M
 
 /*
  * AIPS 1
  */
 #define AIPS1_BASE_ADDR         0x43F00000
-#define AIPS1_BASE_ADDR_VIRT    0xD4000000
+#define AIPS1_BASE_ADDR_VIRT    0xFC000000
 #define AIPS1_SIZE              SZ_1M
+
 #define MAX_BASE_ADDR           0x43F04000
 #define EVTMON_BASE_ADDR        0x43F08000
 #define CLKCTL_BASE_ADDR        0x43F0C000
@@ -107,7 +108,7 @@
  * SPBA
  */
 #define SPBA0_BASE_ADDR         0x50000000
-#define SPBA0_BASE_ADDR_VIRT    0xD4100000
+#define SPBA0_BASE_ADDR_VIRT    0xFC100000
 #define SPBA0_SIZE              SZ_1M
 #define IOMUXC_BASE_ADDR        0x50000000
 #define MMC_SDHC1_BASE_ADDR     0x50004000
@@ -185,7 +186,7 @@
  * AIPS 2
  */
 #define AIPS2_BASE_ADDR         0x53F00000
-#define AIPS2_BASE_ADDR_VIRT    0xD4200000
+#define AIPS2_BASE_ADDR_VIRT    0xFC200000
 #define AIPS2_SIZE              SZ_1M
 #define CRM_MCU_BASE_ADDR       0x53F80000
 #define ECT_MCU_CTI_BASE_ADDR   0x53F84000
@@ -211,18 +212,18 @@
  * ROMP and AVIC
  */
 #define ROMP_BASE_ADDR          0x60000000
-#define ROMP_BASE_ADDR_VIRT     0xD4300000
+#define ROMP_BASE_ADDR_VIRT     0xFC500000
 #define ROMP_SIZE               SZ_1M
 
 #define AVIC_BASE_ADDR          0x68000000
-#define AVIC_BASE_ADDR_VIRT     0xD4400000
+#define AVIC_BASE_ADDR_VIRT     0xFC400000
 #define AVIC_SIZE               SZ_1M
 
 /*
  * NAND, SDRAM, WEIM, M3IF, EMI controllers
  */
 #define X_MEMC_BASE_ADDR        0xB8000000
-#define X_MEMC_BASE_ADDR_VIRT   0xD4500000
+#define X_MEMC_BASE_ADDR_VIRT   0xFC600000
 #define X_MEMC_SIZE             SZ_1M
 
 #define NFC_BASE_ADDR           X_MEMC_BASE_ADDR
@@ -239,11 +240,9 @@
 #define CS0_BASE_ADDR           0xA0000000
 #define CS1_BASE_ADDR           0xA8000000
 #define CS2_BASE_ADDR           0xB0000000
-#define CS2_BASE_ADDR_VIRT      0xEA000000
-#define CS2_SIZE                SZ_16M
 #define CS3_BASE_ADDR           0xB2000000
 #define CS4_BASE_ADDR           0xB4000000
-#define CS4_BASE_ADDR_VIRT      0xEB000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
 #define CS4_SIZE                SZ_16M
 #define CS5_BASE_ADDR           0xB6000000
 
@@ -262,7 +261,6 @@
         ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
         ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
         ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
-        ((x >= CS2_BASE_ADDR) && (x < (CS2_BASE_ADDR + CS2_SIZE))) ? CS2_IO_ADDRESS(x):\
         ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
         ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
         0xDEADBEEF)
@@ -295,9 +293,6 @@
 #define AVIC_IO_ADDRESS(x)  \
         (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
 
-#define CS2_IO_ADDRESS(x)   \
-        (((x) - CS2_BASE_ADDR) + CS2_BASE_ADDR_VIRT)
-
 #define CS4_IO_ADDRESS(x)   \
         (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
 
@@ -345,77 +340,77 @@
 /*
  * Interrupt numbers
  */
-#define INT_RESV0               0
-#define INT_GEM                 1
-#define INT_HAC                 2
-#define INT_SAHARA              2
-#define INT_MU3                 3
-#define INT_MU2                 4
-#define INT_MU1                 5
-#define INT_MU0                 6
-#define INT_ELIT2               7
-#define INT_MMC_SDHC2           8
-#define INT_MMC_SDHC1           9
-#define INT_I2C                 10
-#define INT_SSI2                11
-#define INT_SSI1                12
-#define INT_CSPI2               13
-#define INT_CSPI1               14
-#define INT_EXT_INT7            15
-#define INT_UART3               16
-#define INT_RESV17              17
-#define INT_CCM_MCU_DVFS        17
-#define INT_RESV18              18
-#define INT_ECT                 19
-#define INT_SIM_DATA            20
-#define INT_SIM_GENERAL         21
-#define INT_RNGA                22
-#define INT_RTR                 23
-#define INT_KPP                 24
-#define INT_RTC                 25
-#define INT_PWM                 26
-#define INT_EPIT2               27
-#define INT_EPIT1               28
-#define INT_GPT                 29
-#define INT_UART2               30
-#define INT_DVFS                31
-#define INT_RESV32              32
-#define INT_NANDFC              33
-#define INT_SDMA                34
-#define INT_USBOTG_GRP_ASYNC    35
-#define INT_USBOTG_MNP          36
-#define INT_USBOTG_HOST         37
-#define INT_USBOTG_FUNC         38
-#define INT_USBOTG_DMA          39
-#define INT_USBOTG_CTRL         40
-#define INT_ELIT1               41
-#define INT_IPU                 42
-#define INT_UART1               43
-#define INT_RESV44              44
-#define INT_RESV45              45
-#define INT_IIM                 46
-#define INT_MU_RX_OR            47
-#define INT_MU_TX_OR            48
-#define INT_SCC_SCM             49
-#define INT_EXT_INT6            50
-#define INT_GPIOMCU             51
-#define INT_GPIO1               INT_GPIOMCU
-#define INT_GPIOSDMA            52
-#define INT_GPIO2               INT_GPIOSDMA
-#define INT_CCM                 53
-#define INT_UART4_FIRI_OR       54
-#define INT_WDOG2               55
-#define INT_SIRF_EXT_INT5_OR    56
-#define INT_EXT_INT5            56
-#define INT_SIRF_EXT_INT4_OR    57
-#define INT_EXT_INT4            57
-#define INT_EXT_INT3            58
-#define INT_RTIC                59
-#define INT_MPEG4_ENC           60
-#define INT_HANTRO              60
-#define INT_EXT_INT0            61
-#define INT_EXT_INT1            62
-#define INT_EXT_INT2            63
+#define MXC_INT_RESV0               0
+#define MXC_INT_GEM                 1
+#define MXC_INT_HAC                 2
+#define MXC_INT_SAHARA              2
+#define MXC_INT_MU3                 3
+#define MXC_INT_MU2                 4
+#define MXC_INT_MU1                 5
+#define MXC_INT_MU0                 6
+#define MXC_INT_ELIT2               7
+#define MXC_INT_MMC_SDHC2           8
+#define MXC_INT_MMC_SDHC1           9
+#define MXC_INT_I2C                 10
+#define MXC_INT_SSI2                11
+#define MXC_INT_SSI1                12
+#define MXC_INT_CSPI2               13
+#define MXC_INT_CSPI1               14
+#define MXC_INT_EXT_INT7            15
+#define MXC_INT_UART3               16
+#define MXC_INT_RESV17              17
+#define MXC_INT_CCM_MCU_DVFS        17
+#define MXC_INT_RESV18              18
+#define MXC_INT_ECT                 19
+#define MXC_INT_SIM_DATA            20
+#define MXC_INT_SIM_GENERAL         21
+#define MXC_INT_RNGA                22
+#define MXC_INT_RTR                 23
+#define MXC_INT_KPP                 24
+#define MXC_INT_RTC                 25
+#define MXC_INT_PWM                 26
+#define MXC_INT_EPIT2               27
+#define MXC_INT_EPIT1               28
+#define MXC_INT_GPT                 29
+#define MXC_INT_UART2               30
+#define MXC_INT_DVFS                31
+#define MXC_INT_RESV32              32
+#define MXC_INT_NANDFC              33
+#define MXC_INT_SDMA                34
+#define MXC_INT_USBOTG_GRP_ASYNC    35
+#define MXC_INT_USBOTG_MNP          36
+#define MXC_INT_USBOTG_HOST         37
+#define MXC_INT_USBOTG_FUNC         38
+#define MXC_INT_USBOTG_DMA          39
+#define MXC_INT_USBOTG_CTRL         40
+#define MXC_INT_ELIT1               41
+#define MXC_INT_IPU                 42
+#define MXC_INT_UART1               43
+#define MXC_INT_RESV44              44
+#define MXC_INT_RESV45              45
+#define MXC_INT_IIM                 46
+#define MXC_INT_MU_RX_OR            47
+#define MXC_INT_MU_TX_OR            48
+#define MXC_INT_SCC_SCM             49
+#define MXC_INT_EXT_INT6            50
+#define MXC_INT_GPIOMCU             51
+#define MXC_INT_GPIO1               MXC_INT_GPIOMCU
+#define MXC_INT_GPIOSDMA            52
+#define MXC_INT_GPIO2               MXC_INT_GPIOSDMA
+#define MXC_INT_CCM                 53
+#define MXC_INT_UART4_FIRI_OR       54
+#define MXC_INT_WDOG2               55
+#define MXC_INT_SIRF_EXT_INT5_OR    56
+#define MXC_INT_EXT_INT5            56
+#define MXC_INT_SIRF_EXT_INT4_OR    57
+#define MXC_INT_EXT_INT4            57
+#define MXC_INT_EXT_INT3            58
+#define MXC_INT_RTIC                59
+#define MXC_INT_MPEG4_ENC           60
+#define MXC_INT_HANTRO              60
+#define MXC_INT_EXT_INT0            61
+#define MXC_INT_EXT_INT1            62
+#define MXC_INT_EXT_INT2            63
 
 #define MXC_MAX_INT_LINES       64
 #define MXC_MAX_EXT_LINES       8
@@ -423,9 +418,9 @@
 /*!
  * Interrupt Number for ARM11 PMU
  */
-#define ARM11_PMU_IRQ           INT_RESV0
+#define ARM11_PMU_IRQ           MXC_INT_RESV0
 
-#define MXC_GPIO_BASE           (MXC_MAX_INT_LINES)
+#define MXC_GPIO_INT_BASE	(MXC_MAX_INT_LINES)
 
 /*!
  * Number of GPIO port as defined in the IC Spec
@@ -436,29 +431,10 @@
  */
 #define GPIO_NUM_PIN            32
 
-#define WEIM_CTRL_CS0           WEIM_BASE_ADDR
-#define CSCRU                   0x00
-#define CSCRL                   0x04
-#define CSCRA                   0x08
-
-/*
- * Used for 1-Wire
- */
-#define owire_read(a) (__raw_readb(a))
-#define owire_write(v,a) (__raw_writeb(v,a))
-
 /*!
  * NFMS bit in CSCR register for pagesize of nandflash
  */
 #define NFMS (*((volatile u32 *)IO_ADDRESS(CRM_MCU_BASE_ADDR+0xc)))
 #define NFMS_BIT 18
 
-/*
- * PWM control register used in clock API for
- * finding clock source for the module
- */
-#define MXC_PWM_PWMCTRL		IO_ADDRESS(PWM_BASE_ADDR)
-#define PWM_CTRL_MASK           0xFFFCFFFF
-#define PWM_CTRL_OFFSET	    	16
-
 #endif				/* __ASM_ARCH_MXC_MXC91321_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_scc.h b/include/asm-arm/arch-mxc/mxc_scc.h
index 3116e60dc157..12108ddb8df7 100644
--- a/include/asm-arm/arch-mxc/mxc_scc.h
+++ b/include/asm-arm/arch-mxc/mxc_scc.h
@@ -34,12 +34,12 @@
 /*!
  *  This must be the interrupt line number of the SCM interrupt.
  */
-#define INT_SCM         INT_SCC_SCM
+#define INT_SCM         MXC_INT_SCC_SCM
 
 /*!
  *  if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of
  *  the SMN interrupt.
  */
-#define INT_SMN         INT_SCC_SMN
+#define INT_SMN         MXC_INT_SCC_SMN
 
 #endif
diff --git a/include/asm-arm/arch-mxc/pmic_external.h b/include/asm-arm/arch-mxc/pmic_external.h
index f24cbf871836..3a7287ff9e35 100644
--- a/include/asm-arm/arch-mxc/pmic_external.h
+++ b/include/asm-arm/arch-mxc/pmic_external.h
@@ -128,8 +128,6 @@ typedef struct {
 #define PMIC_ALL_BITS           0xFFFFFF
 #define PMIC_MAX_EVENTS		48
 
-#ifdef CONFIG_MXC_PMIC_MC13783
-
 #define PMIC_ARBITRATION	"NULL"
 /*!
  * This is the enumeration of register names of MC13783
@@ -805,498 +803,6 @@ typedef struct {
 	 */
 	bool sense_clks;
 } t_sensor_bits;
-#endif
-
-#ifdef CONFIG_MXC_PMIC_SC55112
-
-#define PMIC_ARBITRATION	"spi2.0"
-/*!
- * This is the enumeration of register names of SC55112
- */
-typedef enum {
-	/*!
-	 * REG_ISR
-	 */
-	REG_ISR = 0,
-	/*!
-	 * REG_IMR
-	 */
-	REG_IMR,
-	/*!
-	 * REG_PSTAT
-	 */
-	REG_PSTAT,
-	/*!
-	 * REG_INT_SEL
-	 */
-	REG_INT_SEL,
-	/*!
-	 * REG_SWCTRL
-	 */
-	REG_SWCTRL,
-	/*!
-	 * REG_VREG
-	 */
-	REG_VREG,
-	/*!
-	 * REG_IRQ_TEST
-	 */
-	REG_IRQ_TEST,
-	/*!
-	 * REG_TMOD_TRIM_3
-	 */
-	REG_TMOD_TRIM_3,
-	/*!
-	 * REG_BATT_DAC
-	 */
-	REG_BATT_DAC,
-	/*!
-	 * REG_ADC1
-	 */
-	REG_ADC1,
-	/*!
-	 * REG_ADC2
-	 */
-	REG_ADC2,
-	/*!
-	 * REG_AUD_CODEC
-	 */
-	REG_AUD_CODEC,
-	/*!
-	 * REG_RX_AUD_AMPS
-	 */
-	REG_RX_AUD_AMPS,
-	/*!
-	 * REG_ST_DAC
-	 */
-	REG_ST_DAC,
-	/*!
-	 * REG_RTC_TOD
-	 */
-	REG_RTC_TOD,
-	/*!
-	 * REG_RTC_TODA
-	 */
-	REG_RTC_TODA,
-	/*!
-	 * REG_RTC_DAY
-	 */
-	REG_RTC_DAY,
-	/*!
-	 * REG_RTC_DAYA
-	 */
-	REG_RTC_DAYA,
-	/*!
-	 * REG_RTC_CAL
-	 */
-	REG_RTC_CAL,
-	/*!
-	 * REG_PWRCTRL
-	 */
-	REG_PWRCTRL,
-	/*!
-	 * REG_BUSCTRL
-	 */
-	REG_BUSCTRL,
-	/*!
-	 * REG_BACKLIGHT_1
-	 */
-	REG_BACKLIGHT_1,
-	/*!
-	 * REG_BACKLIGHT_2
-	 */
-	REG_BACKLIGHT_2,
-	/*!
-	 * REG_TC_CONTROL1
-	 */
-	REG_TC_CONTROL1,
-	/*!
-	 * REG_TC_CONTROL2
-	 */
-	REG_TC_CONTROL2,
-	/*!
-	 * REG_ARB_REG
-	 */
-	REG_ARB_REG,
-	/*!
-	 * REG_TX_AUD_AMPS
-	 */
-	REG_TX_AUD_AMPS,
-	/*!
-	 * REG_GP_REG
-	 */
-	REG_GP_REG,
-	/*!
-	 * REG_TEST
-	 */
-	REG_TEST,
-	/*!
-	 * REG_TMOD_CTRL_1
-	 */
-	REG_TMOD_CTRL_1,
-	/*!
-	 * REG_TMOD_CTRL_2
-	 */
-	REG_TMOD_CTRL_2,
-	/*!
-	 * REG_TMOD_CTRL_3
-	 */
-	REG_TMOD_CTRL_3,
-	/*!
-	 * REG_RX_STATIC1
-	 */
-	REG_RX_STATIC1,
-	/*!
-	 * REG_RX_STATIC2
-	 */
-	REG_RX_STATIC2,
-	/*!
-	 * REG_RX_STATIC3
-	 */
-	REG_RX_STATIC3,
-	/*!
-	 * REG_RX_STATIC4
-	 */
-	REG_RX_STATIC4,
-	/*!
-	 * REG_RX_DYNAMIC
-	 */
-	REG_RX_DYNAMIC,
-	/*!
-	 * REG_TX_DYNAMIC
-	 */
-	REG_TX_DYNAMIC,
-	/*!
-	 * REG_TX_DYNAMIC2
-	 */
-	REG_TX_DYNAMIC2,
-	/*!
-	 * REG_TX_STATIC1
-	 */
-	REG_TX_STATIC1,
-	/*!
-	 * REG_TX_STATIC2
-	 */
-	REG_TX_STATIC2,
-	/*!
-	 * REG_TX_STATIC3
-	 */
-	REG_TX_STATIC3,
-	/*!
-	 * REG_TX_STATIC4
-	 */
-	REG_TX_STATIC4,
-	/*!
-	 * REG_TX_STATIC5
-	 */
-	REG_TX_STATIC5,
-	/*!
-	 * REG_TX_STATIC6
-	 */
-	REG_TX_STATIC6,
-	/*!
-	 * REG_TX_STATIC7
-	 */
-	REG_TX_STATIC7,
-	/*!
-	 * REG_TX_STATIC8
-	 */
-	REG_TX_STATIC8,
-	/*!
-	 * REG_TX_STATIC9
-	 */
-	REG_TX_STATIC9,
-	/*!
-	 * REG_TX_STATIC10
-	 */
-	REG_TX_STATIC10,
-	/*!
-	 * REG_TX_STATIC11
-	 */
-	REG_TX_STATIC11,
-	/*!
-	 * REG_TX_STATIC12
-	 */
-	REG_TX_STATIC12,
-	/*!
-	 * REG_TX_STATIC13
-	 */
-	REG_TX_STATIC13,
-	/*!
-	 * REG_TX_STATIC14
-	 */
-	REG_TX_STATIC14,
-	/*!
-	 * REG_TX_STATIC15
-	 */
-	REG_TX_STATIC15,
-	/*!
-	 * REG_TX_STATIC16
-	 */
-	REG_TX_STATIC16,
-	/*!
-	 * REG_TX_STATIC17
-	 */
-	REG_TX_STATIC17,
-	/*!
-	 * REG_TX_STATIC18
-	 */
-	REG_TX_STATIC18,
-	/*!
-	 * REG_TONE_GEN
-	 */
-	REG_TONE_GEN,
-	/*!
-	 * REG_GPS_REG
-	 */
-	REG_GPS_REG,
-	/*!
-	 * REG_TMODE_TRIM_1
-	 */
-	REG_TMODE_TRIM_1,
-	/*!
-	 * REG_TMODE_TRIM_2
-	 */
-	REG_TMODE_TRIM_2,
-	/*!
-	 * REG_T_RD_ERROR
-	 */
-	REG_T_RD_ERROR,
-	/*!
-	 * REG_T_RD_NPCOUNT
-	 */
-	REG_T_RD_NPCOUNT,
-	/*!
-	 * REG_ADC2_ALL
-	 */
-	REG_ADC2_ALL,
-	/*!
-	 * REG_NB
-	 */
-	REG_NB
-} pmic_reg;
-
-/*!
- * This is event list of sc55112 interrupt
- */
-
-typedef enum {
-	/*!
-	 * completion of the 7 programmed A/D conversions in standard
-	 * operation
-	 */
-	EVENT_ADCDONEI = 0,
-	/*!
-	 * touchscreen press
-	 */
-	EVENT_TSI = 1,
-	/*!
-	 * interrupt is from the 1Hz output.
-	 */
-	EVENT_1HZI = 2,
-	/*!
-	 * A/D word read in ADC digital comparison mode exceeding the
-	 * WHIGH[5:0] word.
-	 */
-	EVENT_WHI = 3,
-	/*!
-	 * A/D word read in ADC digital comparison mode reading below
-	 * the WLOW[5:0] word.
-	 */
-	EVENT_WLI = 4,
-	/*!
-	 * RTC_TOD = RTC_TODA; RTC_DAY = RTC_DAYA
-	 */
-	EVENT_TODAI = 5,
-	/*!
-	 * occurs on rising and falling debounced edges of USBDET_4.4V.
-	 */
-	EVENT_USB_44VI = 6,
-	/*!
-	 * ON/OFF button was pressed.
-	 */
-	EVENT_ONOFFI = 7,
-	/*!
-	 * ON/OFF2 button was pressed.
-	 */
-	EVENT_ONOFF2I = 8,
-	/*!
-	 * interrupt occurs on rising and falling edges of USBDET_0.8V
-	 */
-	EVENT_USB_08VI = 9,
-	/*!
-	 * interrupt occurs on rising and falling debounced edges of
-	 * MOBPORTB (EXT B+).
-	 */
-	EVENT_MOBPORTI = 10,
-	/*!
-	 * Interrupt linked to PTT_DET , to be debounced on both edges.
-	 */
-	EVENT_PTTI = 11,
-	/*!
-	 * Triggered on debounced transition of A1_INT
-	 */
-	EVENT_A1I = 12,
-	/*!
-	 * Power Cut transition occurred when PCEN=1 and B+ was
-	 * re-applied before the Power Cut timer expired
-	 */
-	EVENT_PCI = 14,
-	/*!
-	 * warm start to the MCU
-	 */
-	EVENT_WARMI = 15,
-	/*!
-	 * End of Life (low battery shut off)
-	 */
-	EVENT_EOLI = 16,
-	/*!
-	 * positive or negative edge of CLK_STAT
-	 */
-	EVENT_CLKI = 17,
-	/*!
-	 * interrupt occurs on rising and falling debounced edges of
-	 * USBDET_2.0V.
-	 */
-	EVENT_USB_20VI = 18,
-	/*!
-	 * Interrupt generated from the de-bounced output of the USB
-	 * ID-detect comparator.
-	 */
-	EVENT_AB_DETI = 19,
-	/*!
-	 * completion of the 7 programmed A/D conversions in standard
-	 * operation.
-	 */
-	EVENT_ADCDONE2I = 20,
-	/*!
-	 * Will be set (1) only if SYS_RST_MODE bits = 10 and (2) the
-	 * BATT_DET_IN/SYS_RESTART input was asserted for the minimum
-	 * debounce time.
-	 */
-	EVENT_SOFT_RESETI = 21,
-	/*!
-	 * Number of events.
-	 */
-	EVENT_NB,
-} type_event;
-
-/*!
- * This enumeration all senses of sc55112.
- */
-typedef enum {
-	/*!
-	 * Status of USB 4.4V Comparator
-	 */
-	SENSOR_USBDET_44V = 0,
-	/*!
-	 * The logic output of ONOFFSNS
-	 */
-	SENSOR_ONOFFSNS,
-	/*!
-	 * The logic output of ONOFFSNS2
-	 */
-	SENSOR_ONOFFSNS2,
-	/*!
-	 * Status of USB 0.8V Comparator
-	 */
-	SENSOR_USBDET_08V,
-	/*!
-	 * The power up state of the radio
-	 */
-	SENSOR_MOBSNSB,
-	/*!
-	 * Status of PTT_DET pin
-	 */
-	SENSOR_PTTSNS,
-	/*!
-	 * Status of A1_INT pin
-	 */
-	SENSOR_A1SNS,
-	/*!
-	 * Status of USB 2.0V Comparator
-	 */
-	SENSOR_USBDET_20V,
-	/*!
-	 * Current state of EOL comparator output
-	 */
-	SENSOR_EOL_STAT,
-	/*!
-	 * 32 kHz external oscillation
-	 */
-	SENSOR_CLK_STAT,
-	/*!
-	 * System reset
-	 */
-	SENSOR_SYS_RST,
-	/*!
-	 * Warm system reset
-	 */
-	SENSOR_WARM_SYS_RST,
-	/*!
-	 * State of the BATT_DET_IN/SYS_RST input
-	 */
-	SENSOR_BATT_DET_IN_SNS,
-} t_sensor;
-
-/*!
- * This structure is used to read all sense bits of sc55112.
- */
-typedef struct {
-	/*!
-	 * Status of USB 4.4V Comparator
-	 */
-	bool usbdet_44v;
-	/*!
-	 * The logic output of ONOFFSNS
-	 */
-	bool onoffsns;
-	/*!
-	 * The logic output of ONOFFSNS2
-	 */
-	bool onoffsns2;
-	/*!
-	 * Status of USB 0.8V Comparator
-	 */
-	bool usbdet_08v;
-	/*!
-	 * The power up state of the radio
-	 */
-	bool mobsnsb;
-	/*!
-	 * Status of PTT_DET pin
-	 */
-	bool pttsns;
-	/*!
-	 * Status of A1_INT pin
-	 */
-	bool a1sns;
-	/*!
-	 * Status of USB 2.0V Comparator
-	 */
-	bool usbdet_20v;
-	/*!
-	 * Current state of EOL comparator output
-	 */
-	bool eol_stat;
-	/*!
-	 * 32 kHz external oscillation
-	 */
-	bool clk_stat;
-	/*!
-	 * System reset
-	 */
-	bool sys_rst;
-	/*!
-	 * Warm system reset
-	 */
-	bool warm_sys_rst;
-	/*!
-	 * State of the BATT_DET_IN/SYS_RST input
-	 */
-	bool batt_det_in_sns;
-} t_sensor_bits;
-#endif
 
 /* EXPORTED FUNCTIONS */
 #ifdef __KERNEL__
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
index 42cc0cb3fefd..b10d7cdc983b 100644
--- a/include/asm-arm/arch-mxc/uncompress.h
+++ b/include/asm-arm/arch-mxc/uncompress.h
@@ -27,6 +27,8 @@
 
 #include <asm/hardware.h>
 
+unsigned int system_rev;
+
 #define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
 
 #define USR2 0x98
diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h
index 2cbe806ce442..f706c22a97aa 100644
--- a/include/asm-arm/ide.h
+++ b/include/asm-arm/ide.h
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_ARCH_MXC
 #define IDE_ARCH_ACK_INTR
-#define ide_ack_intr(hwif)      ((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1)
+#define ide_ack_intr(hwif)      ((hwif)->ack_intr ? (hwif)->ack_intr(hwif) : 1)
 #endif /* CONFIG_ARCH_MXC */
 
 #endif /* __KERNEL__ */