diff options
| author | Igor Nabirushkin <inabirushkin@nvidia.com> | 2014-03-25 13:42:02 +0400 |
|---|---|---|
| committer | Gabby Lee <galee@nvidia.com> | 2014-04-24 18:15:57 -0700 |
| commit | 8a7242d2941ab51d2204eaeccece839b9f6484a9 (patch) | |
| tree | 9ce46d3d95385864ef7a4d4f5f56bd9a140748cf /include | |
| parent | 1dd6fa692bed0e1902213808581187ad9ea86c33 (diff) | |
misc: tegra-profiler: add mixed unwinding mode
Tegra Profiler: do not break the chains for mixed code -
code with exception-handling tables and code with frame pointers
Bug 1487488
Change-Id: I4fdc6708ef2b4e86b354e5a9daeaa19689abb2dd
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/386241
(cherry picked from commit 320dd2b8dced7d3d4a34ddf696907459c3e1a0a8)
Reviewed-on: http://git-master/r/398140
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Maxim Morin <mmorin@nvidia.com>
Reviewed-by: Gabby Lee <galee@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/tegra_profiler.h | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h index ef5b7f1494c3..2d885de6eb4d 100644 --- a/include/linux/tegra_profiler.h +++ b/include/linux/tegra_profiler.h @@ -19,8 +19,8 @@ #include <linux/ioctl.h> -#define QUADD_SAMPLES_VERSION 24 -#define QUADD_IO_VERSION 10 +#define QUADD_SAMPLES_VERSION 25 +#define QUADD_IO_VERSION 11 #define QUADD_IO_VERSION_DYNAMIC_RB 5 #define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6 @@ -28,6 +28,7 @@ #define QUADD_IO_VERSION_BT_KERNEL_CTX 8 #define QUADD_IO_VERSION_GET_MMAP 9 #define QUADD_IO_VERSION_BT_UNWIND_TABLES 10 +#define QUADD_IO_VERSION_UNWIND_MIXED 11 #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17 #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18 @@ -35,6 +36,7 @@ #define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22 #define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23 #define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24 +#define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25 #define QUADD_MAX_COUNTERS 32 #define QUADD_MAX_PROCESS 64 @@ -142,6 +144,7 @@ enum quadd_cpu_mode { enum { QUADD_UNW_METHOD_FP = 0, QUADD_UNW_METHOD_EHT, + QUADD_UNW_METHOD_MIXED, }; #define QUADD_SAMPLE_URC_SHIFT 1 @@ -162,7 +165,10 @@ enum { QUADD_URC_UNSUPPORTED_PR, }; -#define QUADD_SAMPLE_ED_IP64 (1 << 0) +#define QUADD_SED_IP64 (1 << 0) + +#define QUADD_SED_UNW_METHOD_SHIFT 1 +#define QUADD_SED_UNW_METHOD_MASK (0x07 << QUADD_SED_UNW_METHOD_SHIFT) struct quadd_sample_data { u64 ip; @@ -297,6 +303,7 @@ enum { #define QUADD_PARAM_EXTRA_GET_MMAP (1 << 0) #define QUADD_PARAM_EXTRA_BT_FP (1 << 1) #define QUADD_PARAM_EXTRA_BT_UNWIND_TABLES (1 << 2) +#define QUADD_PARAM_EXTRA_BT_MIXED (1 << 3) struct quadd_parameters { u32 freq; @@ -345,6 +352,7 @@ enum { #define QUADD_COMM_CAP_EXTRA_BT_UNWIND_TABLES (1 << 3) #define QUADD_COMM_CAP_EXTRA_SUPPORT_AARCH64 (1 << 4) #define QUADD_COMM_CAP_EXTRA_SPECIAL_ARCH_MMAP (1 << 5) +#define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED (1 << 6) struct quadd_comm_cap { u32 pmu:1, |