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authorShawn Guo <shawn.guo@freescale.com>2014-05-28 13:26:33 +0800
committerShawn Guo <shawn.guo@freescale.com>2014-06-25 21:17:20 +0800
commitc7b8e407591afb7d8976bb9fc3128f921282b7c6 (patch)
tree69ac912afd1e85198f9341fc76171c2258870a57 /include
parent44e694116235a6f69d9e3391f2d6b561708d93c7 (diff)
ENGR00318063-3: ARM: imx6sx: fix ocram_sels mux setting
The current imx6sx clock driver combines two mux clocks ocram_alt_sel and ocram_sel into one, while ocram_alt_sel is a glitchy mux and ocram_sel is a glitchless one. Fix it to match the clock tree in Reference Manual. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy ocram_alt_sel only when ocram_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on ocram_alt_sel and get propagated into the divider ocram_podf. In that case, ocram_podf gets locked up and ocram clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/imx6sx-clock.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 421d8bb76f2f..0e3710cdd5f6 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -251,6 +251,7 @@
#define IMX6SX_CLK_SAI2_IPG 238
#define IMX6SX_CLK_ESAI_IPG 239
#define IMX6SX_CLK_ESAI_MEM 240
-#define IMX6SX_CLK_CLK_END 241
+#define IMX6SX_CLK_OCRAM_ALT_SEL 241
+#define IMX6SX_CLK_CLK_END 242
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */