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authorMichael Grzeschik <m.grzeschik@pengutronix.de>2013-06-13 17:59:56 +0300
committerJason Liu <r64343@freescale.com>2013-08-23 07:29:56 +0800
commit262112d7cde729eceaf7d6294cef5685a839190b (patch)
treea85a7133a074100bd22e940b7c2a8a566f91ba2c /include
parent536efd9af7c004e842b00c6e2dc0998256591a5c (diff)
usb: chipidea: add PTW, PTS and STS handling
This patch makes it possible to configure the PTW, PTS and STS bits inside the portsc register for host and device mode before the driver starts and the phy can be addressed as hardware implementation is designed. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include')
-rw-r--r--include/linux/usb/chipidea.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index 544825dde823..1a2aa1848804 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -14,6 +14,7 @@ struct ci13xxx_platform_data {
uintptr_t capoffset;
unsigned power_budget;
struct usb_phy *phy;
+ enum usb_phy_interface phy_mode;
unsigned long flags;
#define CI13XXX_REGS_SHARED BIT(0)
#define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)