diff options
| author | Nicolin Chen <b42378@freescale.com> | 2013-09-12 14:56:36 +0800 |
|---|---|---|
| committer | Nicolin Chen <b42378@freescale.com> | 2013-09-12 17:49:22 +0800 |
| commit | 48a3a338f1e30774a43a6c9fb4e50e3f3edc70a6 (patch) | |
| tree | 525caaba0fb0248ae333f0c34c29b1d8cabd93ce /include | |
| parent | d5a503b1c2f0ae52264b1b51bcf28a8f8f540908 (diff) | |
ENGR00279368-3 mxc: asrc: Add missing clock control
* Add missing clock control
* Set ASRC clock to 7.5MHz as 3.0.35 does
* Use the same divisor for ideal ratio mode as 3.0.35 does
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mxc_asrc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/mxc_asrc.h b/include/linux/mxc_asrc.h index 9f742a9da80e..ecee963193af 100644 --- a/include/linux/mxc_asrc.h +++ b/include/linux/mxc_asrc.h @@ -30,7 +30,7 @@ /* Ideal Ratio mode doesn't care the outclk frequency, so be fixed */ -#define ASRC_PRESCALER_IDEAL_RATIO 7 +#define ASRC_PRESCALER_IDEAL_RATIO 5 /* SPDIF rxclk pulse rate is 128 * samplerate, so 2 ^ 7 */ #define ASRC_PRESCALER_SPDIF_RX 7 /* SPDIF txclk pulse rate is 64 * samplerate, so 2 ^ 6 */ |