tty: serial: fsl_lpuart: avoid TX FIFO overflow

In some rare cases, the TX DMA gets started while there are still
data in the TX FIFO and the Transmit Data Register Empty Flag
(TDRE) is asserted. In this case, the DMA writes data and overflows
the TX FIFO. It is not quite clear why the TDRE is asserted in this
case, reading the status register which should clear the flag did
not alleviate the problem. It seems that the switching between
DMA and interrupt mode leads to this glitches.

Avoid TX FIFO overrun by using a burst size of 1, which allows to
transfer all data using DMA and avoid switching between DMA and
interrupt mode entirely.

0 files changed, 0 insertions, 0 deletions