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| author | Andrey Zhizhikin <andrey.z@gmail.com> | 2020-08-20 14:26:04 +0000 |
|---|---|---|
| committer | Andrey Zhizhikin <andrey.z@gmail.com> | 2020-08-20 14:26:04 +0000 |
| commit | b66890eae17a10b50a94472de6ed095ff8ebd315 (patch) | |
| tree | 27a2be46771b907d0f6bc78825ad9d1e8b72477b /sound/soc/fsl | |
| parent | 397a487c917f91e3fbca6c9a1a5bffb779d42e76 (diff) | |
| parent | f61e1c3638dddaa1a1f3bb59d2bc288d9f0f1b5b (diff) | |
Merge tag 'v5.4.59' into 5.4-2.1.x-imx
This is the 5.4.59 stable release
Conflicts (manual resolve):
drivers/gpu/drm/imx/dw_hdmi-imx.c:
drivers/gpu/drm/imx/imx-ldb.c:
drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c:
Port changes from upstream commit [1a279871012d3], which extends
component lifetime by moving drm structures allocation/free from
bind() to probe().
sound/soc/fsl/fsl_sai.c:
Apply patch [b8ae2bf5ccc66] from upstream, which uses FIFO watermark
mask macro.
Signed-off-by: Andrey Zhizhikin <andrey.z@gmail.com>
Diffstat (limited to 'sound/soc/fsl')
| -rw-r--r-- | sound/soc/fsl/fsl_sai.c | 4 | ||||
| -rw-r--r-- | sound/soc/fsl/fsl_sai.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 6508e2d2bf05..74e63f2e8d6a 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -997,10 +997,10 @@ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) unsigned char offset = sai->soc->reg_offset; regmap_update_bits(sai->regmap, FSL_SAI_TCR1(offset), - sai->soc->fifo_depth - 1, + FSL_SAI_CR1_RFW_MASK(sai->soc->fifo_depth), sai->soc->fifo_depth - FSL_SAI_MAXBURST_TX); regmap_update_bits(sai->regmap, FSL_SAI_RCR1(offset), - sai->soc->fifo_depth - 1, + FSL_SAI_CR1_RFW_MASK(sai->soc->fifo_depth), FSL_SAI_MAXBURST_RX - 1); snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 91e153e88ae2..e59ba6c9c01f 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -110,7 +110,7 @@ #define FSL_SAI_CSR_FRDE BIT(0) /* SAI Transmit and Receive Configuration 1 Register */ -#define FSL_SAI_CR1_RFW_MASK 0x1f +#define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1) /* SAI Transmit and Receive Configuration 2 Register */ #define FSL_SAI_CR2_SYNC BIT(30) |