diff options
| author | Sumit Bhattacharya <sumitb@nvidia.com> | 2011-09-28 22:18:46 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:16 -0800 |
| commit | d7e091608521465c0484d12052e24b59c5f28235 (patch) | |
| tree | de7226adcd1e4f94f2da5717574a46aa246a03e5 /sound/soc/tegra/tegra20_i2s.c | |
| parent | 1bdb0af1054890a367f73899c163944c1a40aaba (diff) | |
ASoC: Tegra: Modifiy I2s and AHUB clock management
Remove redundant ref counting for I2s and AHUB clocks.
For Tegra30 enable AHUB clocks before I2s registers are accessed.
Disable clocks when they are not in use.
Bug 872652
Change-Id: I7ec4e45cecd0391d0b5a2765214d6c03fa5cc339
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/55005
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Rebase-Id: R886c4a1a472c6b68240f2899a0b0be94c7ac9966
Diffstat (limited to 'sound/soc/tegra/tegra20_i2s.c')
| -rw-r--r-- | sound/soc/tegra/tegra20_i2s.c | 28 |
1 files changed, 6 insertions, 22 deletions
diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c index 38116a75d53e..6117ed02c46f 100644 --- a/sound/soc/tegra/tegra20_i2s.c +++ b/sound/soc/tegra/tegra20_i2s.c @@ -57,22 +57,6 @@ static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg) return __raw_readl(i2s->regs + reg); } -static void tegra20_i2s_inc_clock_ref(struct tegra20_i2s *i2s) -{ - i2s->clk_refs++; - if (i2s->clk_refs == 1) - clk_enable(i2s->clk_i2s); -} - -static void tegra20_i2s_dec_clock_ref(struct tegra20_i2s *i2s) -{ - BUG_ON(!i2s->clk_refs); - - i2s->clk_refs--; - if (!i2s->clk_refs) - clk_enable(i2s->clk_i2s); -} - #ifdef CONFIG_DEBUG_FS static int tegra20_i2s_show(struct seq_file *s, void *unused) { @@ -95,14 +79,14 @@ static int tegra20_i2s_show(struct seq_file *s, void *unused) struct tegra20_i2s *i2s = s->private; int i; - tegra20_i2s_inc_clock_ref(i2s); + clk_enable(i2s->clk_i2s); for (i = 0; i < ARRAY_SIZE(regs); i++) { u32 val = tegra20_i2s_read(i2s, regs[i].offset); seq_printf(s, "%s = %08x\n", regs[i].name, val); } - tegra20_i2s_dec_clock_ref(i2s); + clk_disable(i2s->clk_i2s); return 0; } @@ -242,7 +226,7 @@ static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, if (i2sclock % (2 * srate)) reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE; - tegra20_i2s_inc_clock_ref(i2s); + clk_enable(i2s->clk_i2s); tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg); @@ -250,7 +234,7 @@ static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); - tegra20_i2s_dec_clock_ref(i2s); + clk_disable(i2s->clk_i2s); return 0; } @@ -288,7 +272,7 @@ static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd, case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: case SNDRV_PCM_TRIGGER_RESUME: - tegra20_i2s_inc_clock_ref(i2s); + clk_enable(i2s->clk_i2s); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) tegra20_i2s_start_playback(i2s); else @@ -301,7 +285,7 @@ static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd, tegra20_i2s_stop_playback(i2s); else tegra20_i2s_stop_capture(i2s); - tegra20_i2s_dec_clock_ref(i2s); + clk_disable(i2s->clk_i2s); break; default: return -EINVAL; |