diff options
| author | Sumit Bhattacharya <sumitb@nvidia.com> | 2011-10-31 18:21:56 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:51 -0800 |
| commit | 0d4fbfce61e987643280cd75ac341a58315a4f83 (patch) | |
| tree | bf85e59ec2c1d984104b288289c4d85d1c0bfd80 /sound/soc/tegra/tegra20_i2s.h | |
| parent | e616d388496d5fd5bd7fd21e5be3bae44a271b55 (diff) | |
asoc: tegra: Add support for Tegra20 I2s PCM mode
Add support for Tegra20 I2s PCM mode which is required for playback or
record through BT SCO interface.
Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: Ia4ba1fc308f2e8adb3697ae600a1664aa14467e9
Reviewed-on: http://git-master/r/61232
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R058f7951f0d4bdb5cfe4d997326a2456cc8b105c
Diffstat (limited to 'sound/soc/tegra/tegra20_i2s.h')
| -rw-r--r-- | sound/soc/tegra/tegra20_i2s.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/sound/soc/tegra/tegra20_i2s.h b/sound/soc/tegra/tegra20_i2s.h index 198c02345dbb..b2d3ef710599 100644 --- a/sound/soc/tegra/tegra20_i2s.h +++ b/sound/soc/tegra/tegra20_i2s.h @@ -152,6 +152,31 @@ #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) +/* Fields in TEGRA20_I2S_PCM_CTRL */ + +#define TEGRA20_I2S_PCM_TX_POS_EDGE_NO_HIGHZ 0 +#define TEGRA20_I2S_PCM_TX_POS_EDGE_HIGHZ 1 +#define TEGRA20_I2S_PCM_TX_NEG_EDGE_NO_HIGHZ 2 +#define TEGRA20_I2S_PCM_TX_NEG_EDGE_HIGHZ 3 + +#define TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_SHIFT 9 +#define TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_MASK (0x3 << TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_SHIFT) +#define TEGRA20_I2S_PCM_CTRL_TX_POS_EDGE_NO_HIGHZ (TEGRA20_I2S_PCM_TX_POS_EDGE_NO_HIGHZ << TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_SHIFT) +#define TEGRA20_I2S_PCM_CTRL_TX_POS_EDGE_HIGHZ (TEGRA20_I2S_PCM_TX_POS_EDGE_HIGHZ << TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_SHIFT) +#define TEGRA20_I2S_PCM_CTRL_TX_NEG_EDGE_NO_HIGHZ (TEGRA20_I2S_PCM_TX_NEG_EDGE_NO_HIGHZ << TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_SHIFT) +#define TEGRA20_I2S_PCM_CTRL_TX_NEG_EDGE_HIGHZ (TEGRA20_I2S_PCM_TX_NEG_EDGE_HIGHZ << TEGRA20_I2S_PCM_CTRL_TX_EDGE_CTRL_SHIFT) + +#define TEGRA20_I2S_PCM_CTRL_TX_MASK_BITS_SHIFT 6 +#define TEGRA20_I2S_PCM_CTRL_TX_MASK_BITS_MASK (0x7 << TEGRA20_I2S_PCM_CTRL_TX_MASK_BITS_SHIFT) + +#define TEGRA20_I2S_PCM_CTRL_FSYNC_LONG (1 << 5) +#define TEGRA20_I2S_PCM_CTRL_TRM_MODE_EN (1 << 4) + +#define TEGRA20_I2S_PCM_CTRL_RX_MASK_BITS_SHIFT 1 +#define TEGRA20_I2S_PCM_CTRL_RX_MASK_BITS_MASK (0x7 << TEGRA20_I2S_PCM_CTRL_RX_MASK_BITS_SHIFT) + +#define TEGRA20_I2S_PCM_CTRL_RCV_MODE_EN (1 << 0) + struct tegra20_i2s { struct clk *clk_i2s; struct tegra_pcm_dma_params capture_dma_data; |