ASoC: Tegra SPDIF: Set ch status and fifo attn bits

Add code to enable channel status transmit and set channel
status bits according to pcm stream sample rate. Set
transmit attention level to 4-slot and remove redundant
spdif clock refcounting code.

Bug 872652

Change-Id: I1bb1928e263c033993fa1f4db7609b373976da62
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/53976
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Reaf4877ab3f05cd6c6e37908fc284bb93315f17f

1 files changed, 76 insertions, 1 deletions

diff --git a/sound/soc/tegra/tegra20_spdif.h b/sound/soc/tegra/tegra20_spdif.h
index 7281c0e1ba6a..1938aa67917f 100644
--- a/sound/soc/tegra/tegra20_spdif.h
+++ b/sound/soc/tegra/tegra20_spdif.h
@@ -434,7 +434,83 @@
  */
 
 /* Fields in TEGRA20_SPDIF_CH_STA_TX_A */
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_22050			0x4
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_24000			0x6
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_32000			0x3
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_44100			0x0
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_48000			0x2
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_88200			0x8
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_96000			0xA
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_176400			0xC
+#define TEGRA20_SPDIF_CH_STA_TX_A_SF_192000			0xE
+
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT		24
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK		\
+		(0xF                                 << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_22050	\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_22050  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_24000		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_24000  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_32000  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_44100  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_48000  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_88200  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_96000  << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_176400 << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000		\
+		(TEGRA20_SPDIF_CH_STA_TX_A_SF_192000 << TEGRA20_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+
 /* Fields in TEGRA20_SPDIF_CH_STA_TX_B */
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_8000			0x6
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_11025			0xA
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_12000			0x2
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_16000			0x8
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_22050			0xB
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_24000			0x9
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_32000			0xC
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_44100			0xF
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_48000			0xD
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_88200			0x7
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_96000			0x5
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_176400			0x3
+#define TEGRA20_SPDIF_CH_STA_TX_B_SF_192000			0x1
+
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT		4
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK		\
+		(0xF                                 << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_8000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_8000   << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_11025		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_11025  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_12000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_12000  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_16000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_16000  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_22050		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_22025  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_24000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_24000  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_32000  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_44100  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_48000  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_88200  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_96000  << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_176400 << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000		\
+		(TEGRA20_SPDIF_CH_STA_TX_B_SF_192000 << TEGRA20_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+
 /* Fields in TEGRA20_SPDIF_CH_STA_TX_C */
 /* Fields in TEGRA20_SPDIF_CH_STA_TX_D */
 /* Fields in TEGRA20_SPDIF_CH_STA_TX_E */
@@ -462,7 +538,6 @@
 
 struct tegra20_spdif {
 	struct clk *clk_spdif_out;
-	int clk_refs;
 	struct tegra_pcm_dma_params capture_dma_data;
 	struct tegra_pcm_dma_params playback_dma_data;
 	void __iomem *regs;