diff options
| author | Nikesh Oswal <noswal@nvidia.com> | 2011-09-29 20:29:26 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:08 -0800 |
| commit | 0ddaa4829766aae4fb295d4a263bfb9c16aa83e8 (patch) | |
| tree | f73e4bf8a43bf9ded9b8096b8715af6f25be4795 /sound/soc/tegra/tegra30_ahub.c | |
| parent | a784179ec57beb47d491db0fa1aec1f986aed4f7 (diff) | |
asoc: tegra: fix register settings in ahub driver
Change-Id: I68d6425e0f5c82762e34ec0033f571be22ca5413
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/55232
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Reb05fe9c08d23665c2190fe057c0587ebc800d5b
Diffstat (limited to 'sound/soc/tegra/tegra30_ahub.c')
| -rw-r--r-- | sound/soc/tegra/tegra30_ahub.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c index 002014bea57f..78836091875d 100644 --- a/sound/soc/tegra/tegra30_ahub.c +++ b/sound/soc/tegra/tegra30_ahub.c @@ -222,15 +222,15 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, reg = TEGRA30_AHUB_CHANNEL_CTRL + (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); val = tegra30_apbif_read(reg); - val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | - ~TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK; + val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | + TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK); val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN | TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16; tegra30_apbif_write(reg, val); reg = TEGRA30_AHUB_CIF_RX_CTRL + - (channel * TEGRA30_AHUB_CIF_RX_CTRL); + (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | @@ -309,15 +309,15 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, reg = TEGRA30_AHUB_CHANNEL_CTRL + (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); val = tegra30_apbif_read(reg); - val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | - ~TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK; + val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | + TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK); val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN | TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16; tegra30_apbif_write(reg, val); reg = TEGRA30_AHUB_CIF_TX_CTRL + - (channel * TEGRA30_AHUB_CIF_TX_CTRL); + (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | |