diff options
author | Nikesh Oswal <noswal@nvidia.com> | 2012-01-30 11:40:40 +0530 |
---|---|---|
committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-02-03 05:42:38 -0800 |
commit | 1b7fa17ed4f4c3ca29e5eef43a7ac5e294e8da53 (patch) | |
tree | 654b69a374eb15d30fb7766279c92b3c6fcf52ce /sound/soc/tegra | |
parent | 5a0a5bf298d0ab9782cbba670319a7be59ca57a8 (diff) |
asoc: tegra: set proper bit clk for I2S in slave DSP mode
Bug: 919350
Reviewed-on: http://git-master/r/77989
Change-Id: I9a8d9a1a4d029f1b312405200fcb485de0fc5767
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78704
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'sound/soc/tegra')
-rw-r--r-- | sound/soc/tegra/tegra30_i2s.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c index 9a0ed5a762ed..02d1038ea36e 100644 --- a/sound/soc/tegra/tegra30_i2s.c +++ b/sound/soc/tegra/tegra30_i2s.c @@ -338,6 +338,10 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream, } else { i2sclock = srate * params_channels(params) * sample_size; + /* Additional "* 2" is needed for FSYNC mode */ + if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) + i2sclock *= 2; + ret = clk_set_rate(i2s->clk_i2s_sync, i2sclock); if (ret) { dev_err(dev, "Can't set I2S sync clock rate\n"); |