path: root/sound/soc/tegra
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authorLaxman Dewangan <>2012-05-23 19:08:23 +0530
committerSimone Willett <>2012-05-23 18:42:46 -0700
commit9ef3e8ecc0f1c9a3bfad7c9f4d6a496c4a67924c (patch)
tree5d0803349222c26b2af3c39b3516929ec08c7087 /sound/soc/tegra
parent2f8a84dcc28dfb3fc9638dadc6692b8f96c5bb77 (diff)
spi: tegra: synchronize PPSB late write
When any write is made to PPSB register, it take time to actual happen in the register due to ARM-PPSB design. Delay or readback is required to make sure that write is completed. There is no worst case guaranteed delay and hence doing the register read to make write completes actually. Change-Id: Iefd25115e1a9f02c64e83f11a4e249ad9d086d16 Signed-off-by: Laxman Dewangan <> Reviewed-on: http://git-master/r/102207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <>
Diffstat (limited to 'sound/soc/tegra')
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