diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-12-16 13:06:13 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:18:49 -0600 |
| commit | 3773562ba6c3a34bd8509039a0affdfb1a1b51b9 (patch) | |
| tree | edc338b817e8abad35bc89f9771ecfcbb864ebad /sound | |
| parent | 3bf7b16d3f37eac8110d08762e4e770a87795c0b (diff) | |
MLK-10003-1: ASoC: fsl_sai: The record sound is faster or slower in master mode
The default setting of sai is RX sync with TX, TX output the I2S clock. So
When recording, we should set TCR2's divider, not RCR2's divider.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 9bfe1d33b984b44af011c644f995c3b406b2f3e1)
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/fsl/fsl_sai.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index e29e07899cf7..2f188d0430cf 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -349,10 +349,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) return -EINVAL; } - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), FSL_SAI_CR2_MSEL_MASK, - FSL_SAI_CR2_MSEL(sai->mclk_id)); - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), - FSL_SAI_CR2_DIV_MASK, savediv - 1); + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) { + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_MSEL_MASK, + FSL_SAI_CR2_MSEL(sai->mclk_id)); + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, + FSL_SAI_CR2_DIV_MASK, savediv - 1); + } else { + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_MSEL_MASK, + FSL_SAI_CR2_MSEL(sai->mclk_id)); + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, + FSL_SAI_CR2_DIV_MASK, savediv - 1); + } dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", sai->mclk_id, savediv, savesub); |