diff options
| author | Dara Ramesh <dramesh@nvidia.com> | 2013-01-03 17:20:23 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2013-01-04 15:35:00 -0800 |
| commit | b1682c1befae19107ed88d298f71c9bee9ea1e2b (patch) | |
| tree | 21140b2576acb2a727d10224cc4cf6c608e0f5d9 /sound | |
| parent | 30cf08449e0cceacedda2bca26975ade2d60fee5 (diff) | |
asoc: tegra: i2s: fix DSP mode frame sync width
set default fsync width (i.e short fsync) for
both DSP_A and DSP_B modes.
Change-Id: I519743d4332220b7f686b09da87a096508827990
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/188278
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/tegra/tegra30_i2s.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c index 09c56dc37101..9ad1bb641710 100644 --- a/sound/soc/tegra/tegra30_i2s.c +++ b/sound/soc/tegra/tegra30_i2s.c @@ -554,8 +554,6 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream, bitcnt = (i2sclock / srate) - 1; sym_bitclk = !(i2sclock % srate); #ifndef CONFIG_ARCH_TEGRA_3x_SOC - i2s->reg_ch_ctrl |= (1 << - TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT); val = 0; for (i = 0; i < params_channels(params); i++) val |= (1 << i); @@ -1048,18 +1046,10 @@ static int configure_baseband_i2s(struct tegra30_i2s *i2s, int is_i2smaster, i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE; if (i2s_mode == TEGRA_DAIFMT_DSP_A) { -#ifndef CONFIG_ARCH_TEGRA_3x_SOC - i2s->reg_ch_ctrl |= (1 << - TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT); -#endif i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW; i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE; } else if (i2s_mode == TEGRA_DAIFMT_DSP_B) { -#ifndef CONFIG_ARCH_TEGRA_3x_SOC - i2s->reg_ch_ctrl |= (1 << - TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT); -#endif i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC; i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW; i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE; |