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authorBard Liao <bardliao@realtek.com>2015-04-28 11:27:39 +0800
committerSasha Levin <sasha.levin@oracle.com>2015-05-17 19:12:39 -0400
commit36bcc94a440275cac127cff94e4abeb1658297df (patch)
treef5f3179b5e51a4024d9be374a1dfdd2cbc6c2a2e /sound
parent5d767349a158c8fab2bbb0e2bbe4d5a75b4abf9f (diff)
ASoC: rt5677: fixed wrong DMIC ref clock
[ Upstream commit 60a8d62b8497c23eb3d48149af7e55dac2dd83a2 ] DMIC clock source is not from codec system clock directly. it is generated from the division of system clock. And it should be 256 * sample rate of AIF1. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/rt5677.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index 16aa4d99a713..691237a3ab52 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -644,7 +644,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
{
struct snd_soc_codec *codec = w->codec;
struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
- int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
+ int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
if (idx < 0)
dev_err(codec->dev, "Failed to set DMIC clock\n");