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-rw-r--r--arch/arm/mach-mvf/board-twr-vf700.c20
-rw-r--r--arch/arm/mach-mvf/clock.c58
-rw-r--r--arch/arm/mach-mvf/crm_regs.h4
3 files changed, 80 insertions, 2 deletions
diff --git a/arch/arm/mach-mvf/board-twr-vf700.c b/arch/arm/mach-mvf/board-twr-vf700.c
index fe409af32c7e..7dcda05c80a2 100644
--- a/arch/arm/mach-mvf/board-twr-vf700.c
+++ b/arch/arm/mach-mvf/board-twr-vf700.c
@@ -247,7 +247,7 @@ static struct platform_device mvf_twr_audio_device = {
};
static struct imxuart_platform_data mvf_uart1_pdata = {
- .flags = IMXUART_FIFO | IMXUART_EDMA,
+ .flags = IMXUART_FIFO,
.dma_req_rx = DMA_MUX03_UART1_RX,
.dma_req_tx = DMA_MUX03_UART1_TX,
};
@@ -435,6 +435,10 @@ static struct imx_asrc_platform_data imx_asrc_data = {
.clk_map_ver = 3,
};
+static struct viv_gpu_platform_data mvf_gpu_pdata __initdata = {
+ .reserved_mem_size = SZ_16M,
+};
+
static void __init mvf_twr_init_usb(void)
{
imx_otg_base = MVF_IO_ADDRESS(MVF_USBC0_BASE_ADDR);
@@ -504,7 +508,6 @@ static void __init mvf_board_init(void)
imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
mvf_add_asrc(&imx_asrc_data);
-
}
static void __init mvf_timer_init(void)
@@ -521,6 +524,18 @@ static struct sys_timer mxc_timer = {
.init = mvf_timer_init,
};
+static void __init mvf_mem_reserve(void)
+{
+ phys_addr_t phys;
+ if (mvf_gpu_pdata.reserved_mem_size) {
+ phys = memblock_alloc_base(mvf_gpu_pdata.reserved_mem_size,
+ SZ_4K, 0x88000000);
+ memblock_free(phys, mvf_gpu_pdata.reserved_mem_size);
+ memblock_remove(phys, mvf_gpu_pdata.reserved_mem_size);
+ mvf_gpu_pdata.reserved_mem_base = phys;
+ }
+}
+
/*
* initialize __mach_desc_ data structure.
*/
@@ -532,4 +547,5 @@ MACHINE_START(MVFA5_TWR_VF700, "Freescale MVF TOWER VF700 Board")
.init_irq = mvf_init_irq,
.init_machine = mvf_board_init,
.timer = &mxc_timer,
+ .reserve = mvf_mem_reserve,
MACHINE_END
diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c
index 199483ccb32a..8afe91946907 100644
--- a/arch/arm/mach-mvf/clock.c
+++ b/arch/arm/mach-mvf/clock.c
@@ -1880,6 +1880,57 @@ static struct clk qspi1_clk = {
.get_rate = _clk_qspi1_get_rate,
};
+static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
+{
+ int mux;
+ u32 reg = __raw_readl(MXC_CCM_CSCMR1)
+ & ~MXC_CCM_CSCMR1_GPU_CLK_SEL_MASK;
+
+ mux = _get_mux6(parent, &pll2_pfd2_396M, &pll3_pfd2_396M,
+ NULL, NULL, NULL, NULL);
+
+ reg |= (mux << MXC_CCM_CSCMR1_GPU_CLK_SEL_OFFSET);
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCDR2);
+ reg |= MXC_CCM_CSCDR2_GPU_EN;
+ __raw_writel(reg, MXC_CCM_CSCDR2);
+
+ return 0;
+}
+
+static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent);
+}
+
+static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk, unsigned long rate)
+{
+ return clk_get_rate(clk->parent);
+}
+
+static struct clk gpu2d_core_clk = {
+ __INIT_CLK_DEBUG(gpu2d_core_clk)
+ .id = 0,
+ .parent = &pll2_pfd2_396M,
+ .enable_reg = MXC_CCM_CCGR8,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .set_parent = _clk_gpu2d_core_set_parent,
+ .set_rate = _clk_gpu2d_core_set_rate,
+ .get_rate = _clk_gpu2d_core_get_rate,
+ .round_rate = _clk_gpu2d_core_round_rate,
+};
+
static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
{
return 0;
@@ -1963,6 +2014,9 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
_REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
_REGISTER_CLOCK(NULL, "caam_clk", caam_clk),
+ _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk),
+ _REGISTER_CLOCK(NULL, "openvg_axi_clk", gpu2d_core_clk),
+ _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_core_clk),
};
static void clk_tree_init(void)
@@ -2035,6 +2089,10 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long osc,
clk_set_parent(&qspi0_clk, &pll1_pfd4_528M);
clk_set_rate(&qspi0_clk, 66000000);
+
+ clk_set_parent(&gpu2d_core_clk, &pll2_pfd2_396M);
+ clk_set_rate(&gpu2d_core_clk, 396000000);
+
return 0;
}
diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h
index 4cfc7898aa87..6b0f14dcb867 100644
--- a/arch/arm/mach-mvf/crm_regs.h
+++ b/arch/arm/mach-mvf/crm_regs.h
@@ -312,6 +312,9 @@
#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << 2)
#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_OFFSET (0)
#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_MASK (0x3)
+#define MXC_CCM_CSCMR1_GPU_CLK_SEL_MASK (0x1 << 14)
+#define MXC_CCM_CSCMR1_GPU_CLK_SEL_OFFSET (14)
+
/* Define the bits in register CSCDR1 */
#define MXC_CCM_CSCDR1_FTM3_CLK_EN (0x1 << 28)
@@ -335,6 +338,7 @@
#define MXC_CCM_CSCDR1_SAI1_DIV_MASK (0xF << 4)
#define MXC_CCM_CSCDR1_SAI0_DIV_OFFSET (0)
#define MXC_CCM_CSCDR1_SAI0_DIV_MASK (0xF << 0)
+#define MXC_CCM_CSCDR2_GPU_EN (0x1 << 10)
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_ESAI_EN (0x1 << 30)