diff options
-rw-r--r--[-rwxr-xr-x] | sound/soc/tegra/tegra30_ahub.c | 21 | ||||
-rw-r--r-- | sound/soc/tegra/tegra30_dam.c | 16 |
2 files changed, 35 insertions, 2 deletions
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c index 29476bce6b65..4af245869f60 100755..100644 --- a/sound/soc/tegra/tegra30_ahub.c +++ b/sound/soc/tegra/tegra30_ahub.c @@ -483,7 +483,7 @@ int tegra30_ahub_set_tx_cif_channels(enum tegra30_ahub_txcif txcif, static int __devinit tegra30_ahub_probe(struct platform_device *pdev) { struct resource *res0, *res1, *region; - int ret = 0; + int ret = 0, i = 0, cache_idx_rsvd; if (ahub) return -ENODEV; @@ -556,6 +556,25 @@ static int __devinit tegra30_ahub_probe(struct platform_device *pdev) goto err_release1; } + /* cache the POR values of ahub/apbif regs*/ + tegra30_ahub_enable_clocks(); + + for (i = 0; i < TEGRA30_AHUB_AUDIO_RX_COUNT; i++) + ahub->ahub_reg_cache[i] = tegra30_audio_read(i<<2); + + cache_idx_rsvd = TEGRA30_APBIF_CACHE_REG_INDEX_RSVD; + for (i = 0; i < TEGRA30_APBIF_CACHE_REG_COUNT; i++) { + if (i == cache_idx_rsvd) { + cache_idx_rsvd += + TEGRA30_APBIF_CACHE_REG_INDEX_RSVD_STRIDE; + continue; + } + + ahub->apbif_reg_cache[i] = tegra30_apbif_read(i<<2); + } + + tegra30_ahub_disable_clocks(); + tegra30_ahub_debug_add(ahub); platform_set_drvdata(pdev, ahub); diff --git a/sound/soc/tegra/tegra30_dam.c b/sound/soc/tegra/tegra30_dam.c index fa3d5de4e42d..430374820b97 100644 --- a/sound/soc/tegra/tegra30_dam.c +++ b/sound/soc/tegra/tegra30_dam.c @@ -525,7 +525,7 @@ static int __devinit tegra30_dam_probe(struct platform_device *pdev) { struct resource *res, *region; struct tegra30_dam_context *dam; - int ret = 0; + int ret = 0, i; if ((pdev->id < 0) || (pdev->id >= TEGRA30_NR_DAM_IFC)) { @@ -572,6 +572,20 @@ static int __devinit tegra30_dam_probe(struct platform_device *pdev) goto err_clk_put_dam; } + /* cache the POR values of DAM regs*/ + tegra30_dam_enable_clock(pdev->id); + + for (i = 0; i <= TEGRA30_DAM_CTRL_REGINDEX; i++) { + if ((i == TEGRA30_DAM_CTRL_RSVD_6) || + (i == TEGRA30_DAM_CTRL_RSVD_10)) + continue; + + dam->reg_cache[i] = + tegra30_dam_readl(dam, i << 2); + } + + tegra30_dam_disable_clock(pdev->id); + platform_set_drvdata(pdev, dam); tegra30_dam_debug_add(dam, pdev->id); |