diff options
299 files changed, 11289 insertions, 9265 deletions
diff --git a/Documentation/ABI/testing/sysfs-platform-ideapad-laptop b/Documentation/ABI/testing/sysfs-platform-ideapad-laptop index 807fca2ae2a4..ff53183c3848 100644 --- a/Documentation/ABI/testing/sysfs-platform-ideapad-laptop +++ b/Documentation/ABI/testing/sysfs-platform-ideapad-laptop @@ -4,3 +4,20 @@ KernelVersion: 2.6.37 Contact: "Ike Panhc <ike.pan@canonical.com>" Description: Control the power of camera module. 1 means on, 0 means off. + +What: /sys/devices/platform/ideapad/cfg +Date: Jun 2011 +KernelVersion: 3.1 +Contact: "Ike Panhc <ike.pan@canonical.com>" +Description: + Ideapad capability bits. + Bit 8-10: 1 - Intel graphic only + 2 - ATI graphic only + 3 - Nvidia graphic only + 4 - Intel and ATI graphic + 5 - Intel and Nvidia graphic + Bit 16: Bluetooth exist (1 for exist) + Bit 17: 3G exist (1 for exist) + Bit 18: Wifi exist (1 for exist) + Bit 19: Camera exist (1 for exist) + diff --git a/Documentation/CodingStyle b/Documentation/CodingStyle index fa6e25b94a54..c940239d9678 100644 --- a/Documentation/CodingStyle +++ b/Documentation/CodingStyle @@ -80,22 +80,13 @@ available tools. The limit on the length of lines is 80 columns and this is a strongly preferred limit. -Statements longer than 80 columns will be broken into sensible chunks. -Descendants are always substantially shorter than the parent and are placed -substantially to the right. The same applies to function headers with a long -argument list. Long strings are as well broken into shorter strings. The -only exception to this is where exceeding 80 columns significantly increases -readability and does not hide information. - -void fun(int a, int b, int c) -{ - if (condition) - printk(KERN_WARNING "Warning this is a long printk with " - "3 parameters a: %u b: %u " - "c: %u \n", a, b, c); - else - next_statement; -} +Statements longer than 80 columns will be broken into sensible chunks, unless +exceeding 80 columns significantly increases readability and does not hide +information. Descendants are always substantially shorter than the parent and +are placed substantially to the right. The same applies to function headers +with a long argument list. However, never break user-visible strings such as +printk messages, because that breaks the ability to grep for them. + Chapter 3: Placing Braces and Spaces diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 43f48098220d..c4a6e148732a 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -581,3 +581,14 @@ Why: This driver has been superseded by g_mass_storage. Who: Alan Stern <stern@rowland.harvard.edu> ---------------------------- + +What: threeg and interface sysfs files in /sys/devices/platform/acer-wmi +When: 2012 +Why: In 3.0, we can now autodetect internal 3G device and already have + the threeg rfkill device. So, we plan to remove threeg sysfs support + for it's no longer necessary. + + We also plan to remove interface sysfs file that exposed which ACPI-WMI + interface that was used by acer-wmi driver. It will replaced by + information log when acer-wmi initial. +Who: Lee, Chun-Yi <jlee@novell.com> diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt index 675612ff41ae..5dd960d75174 100644 --- a/Documentation/networking/bonding.txt +++ b/Documentation/networking/bonding.txt @@ -599,7 +599,7 @@ num_unsol_na affect only the active-backup mode. These options were added for bonding versions 3.3.0 and 3.4.0 respectively. - From Linux 2.6.40 and bonding version 3.7.1, these notifications + From Linux 3.0 and bonding version 3.7.1, these notifications are generated by the ipv4 and ipv6 code and the numbers of repetitions cannot be set independently. diff --git a/Documentation/power/runtime_pm.txt b/Documentation/power/runtime_pm.txt index 14dd3c6ad97e..4ce5450ab6e8 100644 --- a/Documentation/power/runtime_pm.txt +++ b/Documentation/power/runtime_pm.txt @@ -54,11 +54,10 @@ referred to as subsystem-level callbacks in what follows. By default, the callbacks are always invoked in process context with interrupts enabled. However, subsystems can use the pm_runtime_irq_safe() helper function to tell the PM core that a device's ->runtime_suspend() and ->runtime_resume() -callbacks should be invoked in atomic context with interrupts disabled -(->runtime_idle() is still invoked the default way). This implies that these -callback routines must not block or sleep, but it also means that the -synchronous helper functions listed at the end of Section 4 can be used within -an interrupt handler or in an atomic context. +callbacks should be invoked in atomic context with interrupts disabled. +This implies that these callback routines must not block or sleep, but it also +means that the synchronous helper functions listed at the end of Section 4 can +be used within an interrupt handler or in an atomic context. The subsystem-level suspend callback is _entirely_ _responsible_ for handling the suspend of the device as appropriate, which may, but need not include @@ -483,6 +482,7 @@ pm_runtime_suspend() pm_runtime_autosuspend() pm_runtime_resume() pm_runtime_get_sync() +pm_runtime_put_sync() pm_runtime_put_sync_suspend() 5. Runtime PM Initialization, Device Probing and Removal diff --git a/MAINTAINERS b/MAINTAINERS index 2c1bc6ea22ea..1f8267f1a2ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2643,9 +2643,8 @@ S: Maintained F: arch/x86/math-emu/ FRAME RELAY DLCI/FRAD (Sangoma drivers too) -M: Mike McLagan <mike.mclagan@linux.org> L: netdev@vger.kernel.org -S: Maintained +S: Orphan F: drivers/net/wan/dlci.c F: drivers/net/wan/sdla.c @@ -4415,10 +4414,10 @@ F: net/*/netfilter/ F: net/netfilter/ NETLABEL -M: Paul Moore <paul.moore@hp.com> +M: Paul Moore <paul@paul-moore.com> W: http://netlabel.sf.net L: netdev@vger.kernel.org -S: Supported +S: Maintained F: Documentation/netlabel/ F: include/net/netlabel.h F: net/netlabel/ @@ -4463,7 +4462,6 @@ F: include/linux/netdevice.h NETWORKING [IPv4/IPv6] M: "David S. Miller" <davem@davemloft.net> M: Alexey Kuznetsov <kuznet@ms2.inr.ac.ru> -M: "Pekka Savola (ipv6)" <pekkas@netcore.fi> M: James Morris <jmorris@namei.org> M: Hideaki YOSHIFUJI <yoshfuji@linux-ipv6.org> M: Patrick McHardy <kaber@trash.net> @@ -4476,7 +4474,7 @@ F: include/net/ip* F: arch/x86/net/* NETWORKING [LABELED] (NetLabel, CIPSO, Labeled IPsec, SECMARK) -M: Paul Moore <paul.moore@hp.com> +M: Paul Moore <paul@paul-moore.com> L: netdev@vger.kernel.org S: Maintained @@ -1,7 +1,7 @@ VERSION = 3 -PATCHLEVEL = 0 +PATCHLEVEL = 1 SUBLEVEL = 0 -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = Sneaky Weasel # *DOCUMENTATION* diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index acca35aebe28..aeef960ff795 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -112,9 +112,6 @@ EXPORT_SYMBOL(__put_user_4); EXPORT_SYMBOL(__put_user_8); #endif - /* crypto hash */ -EXPORT_SYMBOL(sha_transform); - /* gcc lib functions */ EXPORT_SYMBOL(__ashldi3); EXPORT_SYMBOL(__ashrdi3); diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index d7ee0d4c072d..1a347f481e5e 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -197,7 +197,7 @@ void cpu_idle(void) cpu_relax(); } else { stop_critical_timings(); - if (cpuidle_call_idle()) + if (cpuidle_idle_call()) pm_idle(); start_critical_timings(); /* diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 59ff42ddf0ae..cf73a7f742dd 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -12,7 +12,7 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ strchr.o strrchr.o \ testchangebit.o testclearbit.o testsetbit.o \ ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ - ucmpdi2.o lib1funcs.o div64.o sha1.o \ + ucmpdi2.o lib1funcs.o div64.o \ io-readsb.o io-writesb.o io-readsl.o io-writesl.o mmu-y := clear_user.o copy_page.o getuser.o putuser.o diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S deleted file mode 100644 index eb0edb80d7b8..000000000000 --- a/arch/arm/lib/sha1.S +++ /dev/null @@ -1,211 +0,0 @@ -/* - * linux/arch/arm/lib/sha1.S - * - * SHA transform optimized for ARM - * - * Copyright: (C) 2005 by Nicolas Pitre <nico@fluxnic.net> - * Created: September 17, 2005 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * The reference implementation for this code is linux/lib/sha1.c - */ - -#include <linux/linkage.h> - - .text - - -/* - * void sha_transform(__u32 *digest, const char *in, __u32 *W) - * - * Note: the "in" ptr may be unaligned. - */ - -ENTRY(sha_transform) - - stmfd sp!, {r4 - r8, lr} - - @ for (i = 0; i < 16; i++) - @ W[i] = be32_to_cpu(in[i]); - -#ifdef __ARMEB__ - mov r4, r0 - mov r0, r2 - mov r2, #64 - bl memcpy - mov r2, r0 - mov r0, r4 -#else - mov r3, r2 - mov lr, #16 -1: ldrb r4, [r1], #1 - ldrb r5, [r1], #1 - ldrb r6, [r1], #1 - ldrb r7, [r1], #1 - subs lr, lr, #1 - orr r5, r5, r4, lsl #8 - orr r6, r6, r5, lsl #8 - orr r7, r7, r6, lsl #8 - str r7, [r3], #4 - bne 1b -#endif - - @ for (i = 0; i < 64; i++) - @ W[i+16] = ror(W[i+13] ^ W[i+8] ^ W[i+2] ^ W[i], 31); - - sub r3, r2, #4 - mov lr, #64 -2: ldr r4, [r3, #4]! - subs lr, lr, #1 - ldr r5, [r3, #8] - ldr r6, [r3, #32] - ldr r7, [r3, #52] - eor r4, r4, r5 - eor r4, r4, r6 - eor r4, r4, r7 - mov r4, r4, ror #31 - str r4, [r3, #64] - bne 2b - - /* - * The SHA functions are: - * - * f1(B,C,D) = (D ^ (B & (C ^ D))) - * f2(B,C,D) = (B ^ C ^ D) - * f3(B,C,D) = ((B & C) | (D & (B | C))) - * - * Then the sub-blocks are processed as follows: - * - * A' = ror(A, 27) + f(B,C,D) + E + K + *W++ - * B' = A - * C' = ror(B, 2) - * D' = C - * E' = D - * - * We therefore unroll each loop 5 times to avoid register shuffling. - * Also the ror for C (and also D and E which are successivelyderived - * from it) is applied in place to cut on an additional mov insn for - * each round. - */ - - .macro sha_f1, A, B, C, D, E - ldr r3, [r2], #4 - eor ip, \C, \D - add \E, r1, \E, ror #2 - and ip, \B, ip, ror #2 - add \E, \E, \A, ror #27 - eor ip, ip, \D, ror #2 - add \E, \E, r3 - add \E, \E, ip - .endm - - .macro sha_f2, A, B, C, D, E - ldr r3, [r2], #4 - add \E, r1, \E, ror #2 - eor ip, \B, \C, ror #2 - add \E, \E, \A, ror #27 - eor ip, ip, \D, ror #2 - add \E, \E, r3 - add \E, \E, ip - .endm - - .macro sha_f3, A, B, C, D, E - ldr r3, [r2], #4 - add \E, r1, \E, ror #2 - orr ip, \B, \C, ror #2 - add \E, \E, \A, ror #27 - and ip, ip, \D, ror #2 - add \E, \E, r3 - and r3, \B, \C, ror #2 - orr ip, ip, r3 - add \E, \E, ip - .endm - - ldmia r0, {r4 - r8} - - mov lr, #4 - ldr r1, .L_sha_K + 0 - - /* adjust initial values */ - mov r6, r6, ror #30 - mov r7, r7, ror #30 - mov r8, r8, ror #30 - -3: subs lr, lr, #1 - sha_f1 r4, r5, r6, r7, r8 - sha_f1 r8, r4, r5, r6, r7 - sha_f1 r7, r8, r4, r5, r6 - sha_f1 r6, r7, r8, r4, r5 - sha_f1 r5, r6, r7, r8, r4 - bne 3b - - ldr r1, .L_sha_K + 4 - mov lr, #4 - -4: subs lr, lr, #1 - sha_f2 r4, r5, r6, r7, r8 - sha_f2 r8, r4, r5, r6, r7 - sha_f2 r7, r8, r4, r5, r6 - sha_f2 r6, r7, r8, r4, r5 - sha_f2 r5, r6, r7, r8, r4 - bne 4b - - ldr r1, .L_sha_K + 8 - mov lr, #4 - -5: subs lr, lr, #1 - sha_f3 r4, r5, r6, r7, r8 - sha_f3 r8, r4, r5, r6, r7 - sha_f3 r7, r8, r4, r5, r6 - sha_f3 r6, r7, r8, r4, r5 - sha_f3 r5, r6, r7, r8, r4 - bne 5b - - ldr r1, .L_sha_K + 12 - mov lr, #4 - -6: subs lr, lr, #1 - sha_f2 r4, r5, r6, r7, r8 - sha_f2 r8, r4, r5, r6, r7 - sha_f2 r7, r8, r4, r5, r6 - sha_f2 r6, r7, r8, r4, r5 - sha_f2 r5, r6, r7, r8, r4 - bne 6b - - ldmia r0, {r1, r2, r3, ip, lr} - add r4, r1, r4 - add r5, r2, r5 - add r6, r3, r6, ror #2 - add r7, ip, r7, ror #2 - add r8, lr, r8, ror #2 - stmia r0, {r4 - r8} - - ldmfd sp!, {r4 - r8, pc} - -ENDPROC(sha_transform) - - .align 2 -.L_sha_K: - .word 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 - - -/* - * void sha_init(__u32 *buf) - */ - - .align 2 -.L_sha_initial_digest: - .word 0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0 - -ENTRY(sha_init) - - str lr, [sp, #-4]! - adr r1, .L_sha_initial_digest - ldmia r1, {r1, r2, r3, ip, lr} - stmia r0, {r1, r2, r3, ip, lr} - ldr pc, [sp], #4 - -ENDPROC(sha_init) diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index 9026249233ad..af0c2fe1ea37 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -65,7 +65,7 @@ #include <plat/iic.h> #include <plat/pm.h> -#include <sound/wm8915.h> +#include <sound/wm8996.h> #include <sound/wm8962.h> #include <sound/wm9081.h> @@ -614,7 +614,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = { .disable_touch = true, }; -static struct wm8915_retune_mobile_config wm8915_retune[] = { +static struct wm8996_retune_mobile_config wm8996_retune[] = { { .name = "Sub LPF", .rate = 48000, @@ -635,12 +635,12 @@ static struct wm8915_retune_mobile_config wm8915_retune[] = { }, }; -static struct wm8915_pdata wm8915_pdata __initdata = { +static struct wm8996_pdata wm8996_pdata __initdata = { .ldo_ena = S3C64XX_GPN(7), .gpio_base = CODEC_GPIO_BASE, .micdet_def = 1, - .inl_mode = WM8915_DIFFERRENTIAL_1, - .inr_mode = WM8915_DIFFERRENTIAL_1, + .inl_mode = WM8996_DIFFERRENTIAL_1, + .inr_mode = WM8996_DIFFERRENTIAL_1, .irq_flags = IRQF_TRIGGER_RISING, @@ -652,8 +652,8 @@ static struct wm8915_pdata wm8915_pdata __initdata = { 0x020e, /* GPIO5 == CLKOUT */ }, - .retune_mobile_cfgs = wm8915_retune, - .num_retune_mobile_cfgs = ARRAY_SIZE(wm8915_retune), + .retune_mobile_cfgs = wm8996_retune, + .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune), }; static struct wm8962_pdata wm8962_pdata __initdata = { @@ -679,8 +679,8 @@ static struct i2c_board_info i2c_devs1[] __initdata = { .platform_data = &glenfarclas_pmic_pdata }, { I2C_BOARD_INFO("wm1250-ev1", 0x27) }, - { I2C_BOARD_INFO("wm8915", 0x1a), - .platform_data = &wm8915_pdata, + { I2C_BOARD_INFO("wm8996", 0x1a), + .platform_data = &wm8996_pdata, .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, }, { I2C_BOARD_INFO("wm9081", 0x6c), diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c index 6fc03aff046c..c38d22e5e902 100644 --- a/arch/ia64/kernel/efi.c +++ b/arch/ia64/kernel/efi.c @@ -156,7 +156,7 @@ prefix##_get_next_variable (unsigned long *name_size, efi_char16_t *name, \ #define STUB_SET_VARIABLE(prefix, adjust_arg) \ static efi_status_t \ prefix##_set_variable (efi_char16_t *name, efi_guid_t *vendor, \ - unsigned long attr, unsigned long data_size, \ + u32 attr, unsigned long data_size, \ void *data) \ { \ struct ia64_fpreg fr[6]; \ diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c index 3c45de1db716..32114e0941ae 100644 --- a/arch/sh/kernel/idle.c +++ b/arch/sh/kernel/idle.c @@ -101,7 +101,7 @@ void cpu_idle(void) local_irq_disable(); /* Don't trace irqs off for idle */ stop_critical_timings(); - if (cpuidle_call_idle()) + if (cpuidle_idle_call()) pm_idle(); /* * Sanity check to ensure that pm_idle() returns diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild index 3c93f08ce187..2c2e38821f60 100644 --- a/arch/sparc/include/asm/Kbuild +++ b/arch/sparc/include/asm/Kbuild @@ -16,3 +16,8 @@ header-y += traps.h header-y += uctx.h header-y += utrap.h header-y += watchdog.h + +generic-y += div64.h +generic-y += local64.h +generic-y += irq_regs.h +generic-y += local.h diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h index 325e295d60de..29011cc0e4be 100644 --- a/arch/sparc/include/asm/bitops_64.h +++ b/arch/sparc/include/asm/bitops_64.h @@ -26,61 +26,28 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr); #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() -#include <asm-generic/bitops/ffz.h> -#include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/fls64.h> #ifdef __KERNEL__ +extern int ffs(int x); +extern unsigned long __ffs(unsigned long); + +#include <asm-generic/bitops/ffz.h> #include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/ffs.h> /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word */ -#ifdef ULTRA_HAS_POPULATION_COUNT - -static inline unsigned int __arch_hweight64(unsigned long w) -{ - unsigned int res; - - __asm__ ("popc %1,%0" : "=r" (res) : "r" (w)); - return res; -} - -static inline unsigned int __arch_hweight32(unsigned int w) -{ - unsigned int res; - - __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff)); - return res; -} +extern unsigned long __arch_hweight64(__u64 w); +extern unsigned int __arch_hweight32(unsigned int w); +extern unsigned int __arch_hweight16(unsigned int w); +extern unsigned int __arch_hweight8(unsigned int w); -static inline unsigned int __arch_hweight16(unsigned int w) -{ - unsigned int res; - - __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff)); - return res; -} - -static inline unsigned int __arch_hweight8(unsigned int w) -{ - unsigned int res; - - __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff)); - return res; -} - -#else - -#include <asm-generic/bitops/arch_hweight.h> - -#endif #include <asm-generic/bitops/const_hweight.h> #include <asm-generic/bitops/lock.h> #endif /* __KERNEL__ */ diff --git a/arch/sparc/include/asm/div64.h b/arch/sparc/include/asm/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/arch/sparc/include/asm/div64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/div64.h> diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h index 64f7a00b3747..7df8b7f544d4 100644 --- a/arch/sparc/include/asm/elf_64.h +++ b/arch/sparc/include/asm/elf_64.h @@ -59,15 +59,33 @@ #define R_SPARC_6 45 /* Bits present in AT_HWCAP, primarily for Sparc32. */ - -#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */ -#define HWCAP_SPARC_STBAR 2 -#define HWCAP_SPARC_SWAP 4 -#define HWCAP_SPARC_MULDIV 8 -#define HWCAP_SPARC_V9 16 -#define HWCAP_SPARC_ULTRA3 32 -#define HWCAP_SPARC_BLKINIT 64 -#define HWCAP_SPARC_N2 128 +#define HWCAP_SPARC_FLUSH 0x00000001 +#define HWCAP_SPARC_STBAR 0x00000002 +#define HWCAP_SPARC_SWAP 0x00000004 +#define HWCAP_SPARC_MULDIV 0x00000008 +#define HWCAP_SPARC_V9 0x00000010 +#define HWCAP_SPARC_ULTRA3 0x00000020 +#define HWCAP_SPARC_BLKINIT 0x00000040 +#define HWCAP_SPARC_N2 0x00000080 + +/* Solaris compatible AT_HWCAP bits. */ +#define AV_SPARC_MUL32 0x00000100 /* 32x32 multiply is efficient */ +#define AV_SPARC_DIV32 0x00000200 /* 32x32 divide is efficient */ +#define AV_SPARC_FSMULD 0x00000400 /* 'fsmuld' is efficient */ +#define AV_SPARC_V8PLUS 0x00000800 /* v9 insn available to 32bit */ +#define AV_SPARC_POPC 0x00001000 /* 'popc' is efficient */ +#define AV_SPARC_VIS 0x00002000 /* VIS insns available */ +#define AV_SPARC_VIS2 0x00004000 /* VIS2 insns available */ +#define AV_SPARC_ASI_BLK_INIT 0x00008000 /* block init ASIs available */ +#define AV_SPARC_FMAF 0x00010000 /* fused multiply-add */ +#define AV_SPARC_VIS3 0x00020000 /* VIS3 insns available */ +#define AV_SPARC_HPC 0x00040000 /* HPC insns available */ +#define AV_SPARC_RANDOM 0x00080000 /* 'random' insn available */ +#define AV_SPARC_TRANS 0x00100000 /* transaction insns available */ +#define AV_SPARC_FJFMAU 0x00200000 /* unfused multiply-add */ +#define AV_SPARC_IMA 0x00400000 /* integer multiply-add */ +#define AV_SPARC_ASI_CACHE_SPARING \ + 0x00800000 /* cache sparing ASIs available */ #define CORE_DUMP_USE_REGSET @@ -162,33 +180,8 @@ typedef struct { #define ELF_ET_DYN_BASE 0x0000010000000000UL #define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -/* On Ultra, we support all of the v8 capabilities. */ -static inline unsigned int sparc64_elf_hwcap(void) -{ - unsigned int cap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | - HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | - HWCAP_SPARC_V9); - - if (tlb_type == cheetah || tlb_type == cheetah_plus) - cap |= HWCAP_SPARC_ULTRA3; - else if (tlb_type == hypervisor) { - if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || - sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || - sun4v_chip_type == SUN4V_CHIP_NIAGARA3) - cap |= HWCAP_SPARC_BLKINIT; - if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || - sun4v_chip_type == SUN4V_CHIP_NIAGARA3) - cap |= HWCAP_SPARC_N2; - } - - return cap; -} - -#define ELF_HWCAP sparc64_elf_hwcap() +extern unsigned long sparc64_elf_hwcap; +#define ELF_HWCAP sparc64_elf_hwcap /* This yields a string that ld.so will use to load implementation specific libraries for optimization. This is more specific in diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h index 7a5f80df15d0..015a761eaa32 100644 --- a/arch/sparc/include/asm/hypervisor.h +++ b/arch/sparc/include/asm/hypervisor.h @@ -2927,6 +2927,13 @@ extern unsigned long sun4v_ncs_request(unsigned long request, #define HV_FAST_FIRE_GET_PERFREG 0x120 #define HV_FAST_FIRE_SET_PERFREG 0x121 +#define HV_FAST_REBOOT_DATA_SET 0x172 + +#ifndef __ASSEMBLY__ +extern unsigned long sun4v_reboot_data_set(unsigned long ra, + unsigned long len); +#endif + /* Function numbers for HV_CORE_TRAP. */ #define HV_CORE_SET_VER 0x00 #define HV_CORE_PUTCHAR 0x01 @@ -2940,11 +2947,17 @@ extern unsigned long sun4v_ncs_request(unsigned long request, #define HV_GRP_CORE 0x0001 #define HV_GRP_INTR 0x0002 #define HV_GRP_SOFT_STATE 0x0003 +#define HV_GRP_TM 0x0080 #define HV_GRP_PCI 0x0100 #define HV_GRP_LDOM 0x0101 #define HV_GRP_SVC_CHAN 0x0102 #define HV_GRP_NCS 0x0103 #define HV_GRP_RNG 0x0104 +#define HV_GRP_PBOOT 0x0105 +#define HV_GRP_TPM 0x0107 +#define HV_GRP_SDIO 0x0108 +#define HV_GRP_SDIO_ERR 0x0109 +#define HV_GRP_REBOOT_DATA 0x0110 #define HV_GRP_NIAG_PERF 0x0200 #define HV_GRP_FIRE_PERF 0x0201 #define HV_GRP_N2_CPU 0x0202 diff --git a/arch/sparc/include/asm/irq_regs.h b/arch/sparc/include/asm/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/arch/sparc/include/asm/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/irq_regs.h> diff --git a/arch/sparc/include/asm/local.h b/arch/sparc/include/asm/local.h deleted file mode 100644 index bc80815a435c..000000000000 --- a/arch/sparc/include/asm/local.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _SPARC_LOCAL_H -#define _SPARC_LOCAL_H - -#include <asm-generic/local.h> - -#endif diff --git a/arch/sparc/include/asm/local64.h b/arch/sparc/include/asm/local64.h deleted file mode 100644 index 36c93b5cc239..000000000000 --- a/arch/sparc/include/asm/local64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/local64.h> diff --git a/arch/sparc/include/asm/tsb.h b/arch/sparc/include/asm/tsb.h index 83c571d8c8a7..1a8afd1ad04f 100644 --- a/arch/sparc/include/asm/tsb.h +++ b/arch/sparc/include/asm/tsb.h @@ -133,29 +133,6 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; sub TSB, 0x8, TSB; \ TSB_STORE(TSB, TAG); -#define KTSB_LOAD_QUAD(TSB, REG) \ - ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; - -#define KTSB_STORE(ADDR, VAL) \ - stxa VAL, [ADDR] ASI_N; - -#define KTSB_LOCK_TAG(TSB, REG1, REG2) \ -99: lduwa [TSB] ASI_N, REG1; \ - sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\ - andcc REG1, REG2, %g0; \ - bne,pn %icc, 99b; \ - nop; \ - casa [TSB] ASI_N, REG1, REG2;\ - cmp REG1, REG2; \ - bne,pn %icc, 99b; \ - nop; \ - -#define KTSB_WRITE(TSB, TTE, TAG) \ - add TSB, 0x8, TSB; \ - stxa TTE, [TSB] ASI_N; \ - sub TSB, 0x8, TSB; \ - stxa TAG, [TSB] ASI_N; - /* Do a kernel page table walk. Leaves physical PTE pointer in * REG1. Jumps to FAIL_LABEL on early page table walk termination. * VADDR will not be clobbered, but REG2 will. @@ -239,6 +216,8 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; (KERNEL_TSB_SIZE_BYTES / 16) #define KERNEL_TSB4M_NENTRIES 4096 +#define KTSB_PHYS_SHIFT 15 + /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries * and the found TTE will be left in REG1. REG3 and REG4 must @@ -247,13 +226,22 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; * VADDR and TAG will be preserved and not clobbered by this macro. */ #define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ - sethi %hi(swapper_tsb), REG1; \ +661: sethi %hi(swapper_tsb), REG1; \ or REG1, %lo(swapper_tsb), REG1; \ + .section .swapper_tsb_phys_patch, "ax"; \ + .word 661b; \ + .previous; \ +661: nop; \ + .section .tsb_ldquad_phys_patch, "ax"; \ + .word 661b; \ + sllx REG1, KTSB_PHYS_SHIFT, REG1; \ + sllx REG1, KTSB_PHYS_SHIFT, REG1; \ + .previous; \ srlx VADDR, PAGE_SHIFT, REG2; \ and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \ sllx REG2, 4, REG2; \ add REG1, REG2, REG2; \ - KTSB_LOAD_QUAD(REG2, REG3); \ + TSB_LOAD_QUAD(REG2, REG3); \ cmp REG3, TAG; \ be,a,pt %xcc, OK_LABEL; \ mov REG4, REG1; @@ -263,12 +251,21 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; * we can make use of that for the index computation. */ #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ - sethi %hi(swapper_4m_tsb), REG1; \ +661: sethi %hi(swapper_4m_tsb), REG1; \ or REG1, %lo(swapper_4m_tsb), REG1; \ + .section .swapper_4m_tsb_phys_patch, "ax"; \ + .word 661b; \ + .previous; \ +661: nop; \ + .section .tsb_ldquad_phys_patch, "ax"; \ + .word 661b; \ + sllx REG1, KTSB_PHYS_SHIFT, REG1; \ + sllx REG1, KTSB_PHYS_SHIFT, REG1; \ + .previous; \ and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \ sllx REG2, 4, REG2; \ add REG1, REG2, REG2; \ - KTSB_LOAD_QUAD(REG2, REG3); \ + TSB_LOAD_QUAD(REG2, REG3); \ cmp REG3, TAG; \ be,a,pt %xcc, OK_LABEL; \ mov REG4, REG1; diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index 17cf290dc2bc..9810fd881058 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c @@ -396,6 +396,7 @@ static int show_cpuinfo(struct seq_file *m, void *__unused) , cpu_data(0).clock_tick #endif ); + cpucap_info(m); #ifdef CONFIG_SMP smp_bogo(m); #endif diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c index dd1342c0a3be..490e5418740d 100644 --- a/arch/sparc/kernel/ds.c +++ b/arch/sparc/kernel/ds.c @@ -15,12 +15,15 @@ #include <linux/reboot.h> #include <linux/cpu.h> +#include <asm/hypervisor.h> #include <asm/ldc.h> #include <asm/vio.h> #include <asm/mdesc.h> #include <asm/head.h> #include <asm/irq.h> +#include "kernel.h" + #define DRV_MODULE_NAME "ds" #define PFX DRV_MODULE_NAME ": " #define DRV_MODULE_VERSION "1.0" @@ -828,18 +831,32 @@ void ldom_set_var(const char *var, const char *value) } } +static char full_boot_str[256] __attribute__((aligned(32))); +static int reboot_data_supported; + void ldom_reboot(const char *boot_command) { /* Don't bother with any of this if the boot_command * is empty. */ if (boot_command && strlen(boot_command)) { - char full_boot_str[256]; + unsigned long len; strcpy(full_boot_str, "boot "); strcpy(full_boot_str + strlen("boot "), boot_command); + len = strlen(full_boot_str); - ldom_set_var("reboot-command", full_boot_str); + if (reboot_data_supported) { + unsigned long ra = kimage_addr_to_ra(full_boot_str); + unsigned long hv_ret; + + hv_ret = sun4v_reboot_data_set(ra, len); + if (hv_ret != HV_EOK) + pr_err("SUN4V: Unable to set reboot data " + "hv_ret=%lu\n", hv_ret); + } else { + ldom_set_var("reboot-command", full_boot_str); + } } sun4v_mach_sir(); } @@ -1237,6 +1254,15 @@ static struct vio_driver ds_driver = { static int __init ds_init(void) { + unsigned long hv_ret, major, minor; + + hv_ret = sun4v_get_version(HV_GRP_REBOOT_DATA, &major, &minor); + if (hv_ret == HV_EOK) { + pr_info("SUN4V: Reboot data supported (maj=%lu,min=%lu).\n", + major, minor); + reboot_data_supported = 1; + } + kthread_run(ds_thread, NULL, "kldomd"); return vio_register_driver(&ds_driver); diff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h index d1f1361c4167..e27f8ea8656e 100644 --- a/arch/sparc/kernel/entry.h +++ b/arch/sparc/kernel/entry.h @@ -42,6 +42,20 @@ extern void fpsave(unsigned long *fpregs, unsigned long *fsr, extern void fpload(unsigned long *fpregs, unsigned long *fsr); #else /* CONFIG_SPARC32 */ +struct popc_3insn_patch_entry { + unsigned int addr; + unsigned int insns[3]; +}; +extern struct popc_3insn_patch_entry __popc_3insn_patch, + __popc_3insn_patch_end; + +struct popc_6insn_patch_entry { + unsigned int addr; + unsigned int insns[6]; +}; +extern struct popc_6insn_patch_entry __popc_6insn_patch, + __popc_6insn_patch_end; + extern void __init per_cpu_patch(void); extern void __init sun4v_patch(void); extern void __init boot_cpu_id_too_large(int cpu); diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S index c752603a7c0d..0eac1b2fc53d 100644 --- a/arch/sparc/kernel/head_64.S +++ b/arch/sparc/kernel/head_64.S @@ -559,7 +559,7 @@ niagara2_patch: nop call niagara_patch_bzero nop - call niagara2_patch_pageops + call niagara_patch_pageops nop ba,a,pt %xcc, 80f diff --git a/arch/sparc/kernel/hvapi.c b/arch/sparc/kernel/hvapi.c index d306e648c33c..c2d055d8ba9e 100644 --- a/arch/sparc/kernel/hvapi.c +++ b/arch/sparc/kernel/hvapi.c @@ -28,11 +28,17 @@ static struct api_info api_table[] = { { .group = HV_GRP_CORE, .flags = FLAG_PRE_API }, { .group = HV_GRP_INTR, }, { .group = HV_GRP_SOFT_STATE, }, + { .group = HV_GRP_TM, }, { .group = HV_GRP_PCI, .flags = FLAG_PRE_API }, { .group = HV_GRP_LDOM, }, { .group = HV_GRP_SVC_CHAN, .flags = FLAG_PRE_API }, { .group = HV_GRP_NCS, .flags = FLAG_PRE_API }, { .group = HV_GRP_RNG, }, + { .group = HV_GRP_PBOOT, }, + { .group = HV_GRP_TPM, }, + { .group = HV_GRP_SDIO, }, + { .group = HV_GRP_SDIO_ERR, }, + { .group = HV_GRP_REBOOT_DATA, }, { .group = HV_GRP_NIAG_PERF, .flags = FLAG_PRE_API }, { .group = HV_GRP_FIRE_PERF, }, { .group = HV_GRP_N2_CPU, }, diff --git a/arch/sparc/kernel/hvcalls.S b/arch/sparc/kernel/hvcalls.S index 8a5f35ffb15e..58d60de4d65b 100644 --- a/arch/sparc/kernel/hvcalls.S +++ b/arch/sparc/kernel/hvcalls.S @@ -798,3 +798,10 @@ ENTRY(sun4v_niagara2_setperf) retl nop ENDPROC(sun4v_niagara2_setperf) + +ENTRY(sun4v_reboot_data_set) + mov HV_FAST_REBOOT_DATA_SET, %o5 + ta HV_FAST_TRAP + retl + nop +ENDPROC(sun4v_reboot_data_set) diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h index 6f6544cfa0ef..fd6c36b1df74 100644 --- a/arch/sparc/kernel/kernel.h +++ b/arch/sparc/kernel/kernel.h @@ -4,12 +4,27 @@ #include <linux/interrupt.h> #include <asm/traps.h> +#include <asm/head.h> +#include <asm/io.h> /* cpu.c */ extern const char *sparc_pmu_type; extern unsigned int fsr_storage; extern int ncpus_probed; +#ifdef CONFIG_SPARC64 +/* setup_64.c */ +struct seq_file; +extern void cpucap_info(struct seq_file *); + +static inline unsigned long kimage_addr_to_ra(const char *p) +{ + unsigned long val = (unsigned long) p; + + return kern_base + (val - KERNBASE); +} +#endif + #ifdef CONFIG_SPARC32 /* cpu.c */ extern void cpu_probe(void); diff --git a/arch/sparc/kernel/ktlb.S b/arch/sparc/kernel/ktlb.S index 1d361477d7d6..79f310364849 100644 --- a/arch/sparc/kernel/ktlb.S +++ b/arch/sparc/kernel/ktlb.S @@ -47,16 +47,16 @@ kvmap_itlb_tsb_miss: kvmap_itlb_vmalloc_addr: KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath) - KTSB_LOCK_TAG(%g1, %g2, %g7) + TSB_LOCK_TAG(%g1, %g2, %g7) /* Load and check PTE. */ ldxa [%g5] ASI_PHYS_USE_EC, %g5 mov 1, %g7 sllx %g7, TSB_TAG_INVALID_BIT, %g7 brgez,a,pn %g5, kvmap_itlb_longpath - KTSB_STORE(%g1, %g7) + TSB_STORE(%g1, %g7) - KTSB_WRITE(%g1, %g5, %g6) + TSB_WRITE(%g1, %g5, %g6) /* fallthrough to TLB load */ @@ -102,9 +102,9 @@ kvmap_itlb_longpath: kvmap_itlb_obp: OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath) - KTSB_LOCK_TAG(%g1, %g2, %g7) + TSB_LOCK_TAG(%g1, %g2, %g7) - KTSB_WRITE(%g1, %g5, %g6) + TSB_WRITE(%g1, %g5, %g6) ba,pt %xcc, kvmap_itlb_load nop @@ -112,17 +112,17 @@ kvmap_itlb_obp: kvmap_dtlb_obp: OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath) - KTSB_LOCK_TAG(%g1, %g2, %g7) + TSB_LOCK_TAG(%g1, %g2, %g7) - KTSB_WRITE(%g1, %g5, %g6) + TSB_WRITE(%g1, %g5, %g6) ba,pt %xcc, kvmap_dtlb_load nop .align 32 kvmap_dtlb_tsb4m_load: - KTSB_LOCK_TAG(%g1, %g2, %g7) - KTSB_WRITE(%g1, %g5, %g6) + TSB_LOCK_TAG(%g1, %g2, %g7) + TSB_WRITE(%g1, %g5, %g6) ba,pt %xcc, kvmap_dtlb_load nop @@ -222,16 +222,16 @@ kvmap_linear_patch: kvmap_dtlb_vmalloc_addr: KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath) - KTSB_LOCK_TAG(%g1, %g2, %g7) + TSB_LOCK_TAG(%g1, %g2, %g7) /* Load and check PTE. */ ldxa [%g5] ASI_PHYS_USE_EC, %g5 mov 1, %g7 sllx %g7, TSB_TAG_INVALID_BIT, %g7 brgez,a,pn %g5, kvmap_dtlb_longpath - KTSB_STORE(%g1, %g7) + TSB_STORE(%g1, %g7) - KTSB_WRITE(%g1, %g5, %g6) + TSB_WRITE(%g1, %g5, %g6) /* fallthrough to TLB load */ diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c index 42f28c7420e1..acaebb63c4fd 100644 --- a/arch/sparc/kernel/mdesc.c +++ b/arch/sparc/kernel/mdesc.c @@ -508,6 +508,8 @@ const char *mdesc_node_name(struct mdesc_handle *hp, u64 node) } EXPORT_SYMBOL(mdesc_node_name); +static u64 max_cpus = 64; + static void __init report_platform_properties(void) { struct mdesc_handle *hp = mdesc_grab(); @@ -543,8 +545,10 @@ static void __init report_platform_properties(void) if (v) printk("PLATFORM: watchdog-max-timeout [%llu ms]\n", *v); v = mdesc_get_property(hp, pn, "max-cpus", NULL); - if (v) - printk("PLATFORM: max-cpus [%llu]\n", *v); + if (v) { + max_cpus = *v; + printk("PLATFORM: max-cpus [%llu]\n", max_cpus); + } #ifdef CONFIG_SMP { @@ -715,7 +719,7 @@ static void __cpuinit set_proc_ids(struct mdesc_handle *hp) } static void __cpuinit get_one_mondo_bits(const u64 *p, unsigned int *mask, - unsigned char def) + unsigned long def, unsigned long max) { u64 val; @@ -726,6 +730,9 @@ static void __cpuinit get_one_mondo_bits(const u64 *p, unsigned int *mask, if (!val || val >= 64) goto use_default; + if (val > max) + val = max; + *mask = ((1U << val) * 64U) - 1U; return; @@ -736,19 +743,28 @@ use_default: static void __cpuinit get_mondo_data(struct mdesc_handle *hp, u64 mp, struct trap_per_cpu *tb) { + static int printed; const u64 *val; val = mdesc_get_property(hp, mp, "q-cpu-mondo-#bits", NULL); - get_one_mondo_bits(val, &tb->cpu_mondo_qmask, 7); + get_one_mondo_bits(val, &tb->cpu_mondo_qmask, 7, ilog2(max_cpus * 2)); val = mdesc_get_property(hp, mp, "q-dev-mondo-#bits", NULL); - get_one_mondo_bits(val, &tb->dev_mondo_qmask, 7); + get_one_mondo_bits(val, &tb->dev_mondo_qmask, 7, 8); val = mdesc_get_property(hp, mp, "q-resumable-#bits", NULL); - get_one_mondo_bits(val, &tb->resum_qmask, 6); + get_one_mondo_bits(val, &tb->resum_qmask, 6, 7); val = mdesc_get_property(hp, mp, "q-nonresumable-#bits", NULL); - get_one_mondo_bits(val, &tb->nonresum_qmask, 2); + get_one_mondo_bits(val, &tb->nonresum_qmask, 2, 2); + if (!printed++) { + pr_info("SUN4V: Mondo queue sizes " + "[cpu(%u) dev(%u) r(%u) nr(%u)]\n", + tb->cpu_mondo_qmask + 1, + tb->dev_mondo_qmask + 1, + tb->resum_qmask + 1, + tb->nonresum_qmask + 1); + } } static void * __cpuinit mdesc_iterate_over_cpus(void *(*func)(struct mdesc_handle *, u64, int, void *), void *arg, cpumask_t *mask) diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c index c4dd0999da86..3e9daea1653d 100644 --- a/arch/sparc/kernel/setup_64.c +++ b/arch/sparc/kernel/setup_64.c @@ -29,6 +29,7 @@ #include <linux/interrupt.h> #include <linux/cpu.h> #include <linux/initrd.h> +#include <linux/module.h> #include <asm/system.h> #include <asm/io.h> @@ -46,6 +47,8 @@ #include <asm/mmu.h> #include <asm/ns87303.h> #include <asm/btext.h> +#include <asm/elf.h> +#include <asm/mdesc.h> #ifdef CONFIG_IP_PNP #include <net/ipconfig.h> @@ -269,6 +272,40 @@ void __init sun4v_patch(void) sun4v_hvapi_init(); } +static void __init popc_patch(void) +{ + struct popc_3insn_patch_entry *p3; + struct popc_6insn_patch_entry *p6; + + p3 = &__popc_3insn_patch; + while (p3 < &__popc_3insn_patch_end) { + unsigned long i, addr = p3->addr; + + for (i = 0; i < 3; i++) { + *(unsigned int *) (addr + (i * 4)) = p3->insns[i]; + wmb(); + __asm__ __volatile__("flush %0" + : : "r" (addr + (i * 4))); + } + + p3++; + } + + p6 = &__popc_6insn_patch; + while (p6 < &__popc_6insn_patch_end) { + unsigned long i, addr = p6->addr; + + for (i = 0; i < 6; i++) { + *(unsigned int *) (addr + (i * 4)) = p6->insns[i]; + wmb(); + __asm__ __volatile__("flush %0" + : : "r" (addr + (i * 4))); + } + + p6++; + } +} + #ifdef CONFIG_SMP void __init boot_cpu_id_too_large(int cpu) { @@ -278,6 +315,154 @@ void __init boot_cpu_id_too_large(int cpu) } #endif +/* On Ultra, we support all of the v8 capabilities. */ +unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | + HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | + HWCAP_SPARC_V9); +EXPORT_SYMBOL(sparc64_elf_hwcap); + +static const char *hwcaps[] = { + "flush", "stbar", "swap", "muldiv", "v9", + "ultra3", "blkinit", "n2", + + /* These strings are as they appear in the machine description + * 'hwcap-list' property for cpu nodes. + */ + "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", + "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", + "ima", "cspare", +}; + +void cpucap_info(struct seq_file *m) +{ + unsigned long caps = sparc64_elf_hwcap; + int i, printed = 0; + + seq_puts(m, "cpucaps\t\t: "); + for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { + unsigned long bit = 1UL << i; + if (caps & bit) { + seq_printf(m, "%s%s", + printed ? "," : "", hwcaps[i]); + printed++; + } + } + seq_putc(m, '\n'); +} + +static void __init report_hwcaps(unsigned long caps) +{ + int i, printed = 0; + + printk(KERN_INFO "CPU CAPS: ["); + for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { + unsigned long bit = 1UL << i; + if (caps & bit) { + printk(KERN_CONT "%s%s", + printed ? "," : "", hwcaps[i]); + if (++printed == 8) { + printk(KERN_CONT "]\n"); + printk(KERN_INFO "CPU CAPS: ["); + printed = 0; + } + } + } + printk(KERN_CONT "]\n"); +} + +static unsigned long __init mdesc_cpu_hwcap_list(void) +{ + struct mdesc_handle *hp; + unsigned long caps = 0; + const char *prop; + int len; + u64 pn; + + hp = mdesc_grab(); + if (!hp) + return 0; + + pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu"); + if (pn == MDESC_NODE_NULL) + goto out; + + prop = mdesc_get_property(hp, pn, "hwcap-list", &len); + if (!prop) + goto out; + + while (len) { + int i, plen; + + for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { + unsigned long bit = 1UL << i; + + if (!strcmp(prop, hwcaps[i])) { + caps |= bit; + break; + } + } + + plen = strlen(prop) + 1; + prop += plen; + len -= plen; + } + +out: + mdesc_release(hp); + return caps; +} + +/* This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +static void __init init_sparc64_elf_hwcap(void) +{ + unsigned long cap = sparc64_elf_hwcap; + unsigned long mdesc_caps; + + if (tlb_type == cheetah || tlb_type == cheetah_plus) + cap |= HWCAP_SPARC_ULTRA3; + else if (tlb_type == hypervisor) { + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || + sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || + sun4v_chip_type == SUN4V_CHIP_NIAGARA3) + cap |= HWCAP_SPARC_BLKINIT; + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || + sun4v_chip_type == SUN4V_CHIP_NIAGARA3) + cap |= HWCAP_SPARC_N2; + } + + cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS); + + mdesc_caps = mdesc_cpu_hwcap_list(); + if (!mdesc_caps) { + if (tlb_type == spitfire) + cap |= AV_SPARC_VIS; + if (tlb_type == cheetah || tlb_type == cheetah_plus) + cap |= AV_SPARC_VIS | AV_SPARC_VIS2; + if (tlb_type == cheetah_plus) + cap |= AV_SPARC_POPC; + if (tlb_type == hypervisor) { + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) + cap |= AV_SPARC_ASI_BLK_INIT; + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || + sun4v_chip_type == SUN4V_CHIP_NIAGARA3) + cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | + AV_SPARC_ASI_BLK_INIT | + AV_SPARC_POPC); + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3) + cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | + AV_SPARC_FMAF); + } + } + sparc64_elf_hwcap = cap | mdesc_caps; + + report_hwcaps(sparc64_elf_hwcap); + + if (sparc64_elf_hwcap & AV_SPARC_POPC) + popc_patch(); +} + void __init setup_arch(char **cmdline_p) { /* Initialize PROM console and command line. */ @@ -337,6 +522,7 @@ void __init setup_arch(char **cmdline_p) init_cur_cpu_trap(current_thread_info()); paging_init(); + init_sparc64_elf_hwcap(); } extern int stop_a_enabled; diff --git a/arch/sparc/kernel/sparc_ksyms_64.c b/arch/sparc/kernel/sparc_ksyms_64.c index 372ad59c4cba..83b47ab02d96 100644 --- a/arch/sparc/kernel/sparc_ksyms_64.c +++ b/arch/sparc/kernel/sparc_ksyms_64.c @@ -8,6 +8,7 @@ #include <linux/module.h> #include <linux/pci.h> #include <linux/init.h> +#include <linux/bitops.h> #include <asm/system.h> #include <asm/cpudata.h> @@ -38,5 +39,15 @@ EXPORT_SYMBOL(sun4v_niagara_setperf); EXPORT_SYMBOL(sun4v_niagara2_getperf); EXPORT_SYMBOL(sun4v_niagara2_setperf); +/* from hweight.S */ +EXPORT_SYMBOL(__arch_hweight8); +EXPORT_SYMBOL(__arch_hweight16); +EXPORT_SYMBOL(__arch_hweight32); +EXPORT_SYMBOL(__arch_hweight64); + +/* from ffs_ffz.S */ +EXPORT_SYMBOL(ffs); +EXPORT_SYMBOL(__ffs); + /* Exporting a symbol from /init/main.c */ EXPORT_SYMBOL(saved_command_line); diff --git a/arch/sparc/kernel/sstate.c b/arch/sparc/kernel/sstate.c index 8cdbe5946b43..c59af546f522 100644 --- a/arch/sparc/kernel/sstate.c +++ b/arch/sparc/kernel/sstate.c @@ -14,14 +14,9 @@ #include <asm/head.h> #include <asm/io.h> -static int hv_supports_soft_state; - -static unsigned long kimage_addr_to_ra(const char *p) -{ - unsigned long val = (unsigned long) p; +#include "kernel.h" - return kern_base + (val - KERNBASE); -} +static int hv_supports_soft_state; static void do_set_sstate(unsigned long state, const char *msg) { diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c index 35cff1673aa4..76e4ac1a13e1 100644 --- a/arch/sparc/kernel/unaligned_64.c +++ b/arch/sparc/kernel/unaligned_64.c @@ -22,6 +22,7 @@ #include <linux/bitops.h> #include <linux/perf_event.h> #include <linux/ratelimit.h> +#include <linux/bitops.h> #include <asm/fpumacro.h> enum direction { @@ -373,16 +374,11 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn) } } -static char popc_helper[] = { -0, 1, 1, 2, 1, 2, 2, 3, -1, 2, 2, 3, 2, 3, 3, 4, -}; - int handle_popc(u32 insn, struct pt_regs *regs) { - u64 value; - int ret, i, rd = ((insn >> 25) & 0x1f); int from_kernel = (regs->tstate & TSTATE_PRIV) != 0; + int ret, rd = ((insn >> 25) & 0x1f); + u64 value; perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); if (insn & 0x2000) { @@ -392,10 +388,7 @@ int handle_popc(u32 insn, struct pt_regs *regs) maybe_flush_windows(0, insn & 0x1f, rd, from_kernel); value = fetch_reg(insn & 0x1f, regs); } - for (ret = 0, i = 0; i < 16; i++) { - ret += popc_helper[value & 0xf]; - value >>= 4; - } + ret = hweight64(value); if (rd < 16) { if (rd) regs->u_regs[rd] = ret; diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S index c0220759003e..0e1605697b49 100644 --- a/arch/sparc/kernel/vmlinux.lds.S +++ b/arch/sparc/kernel/vmlinux.lds.S @@ -107,7 +107,26 @@ SECTIONS *(.sun4v_2insn_patch) __sun4v_2insn_patch_end = .; } - + .swapper_tsb_phys_patch : { + __swapper_tsb_phys_patch = .; + *(.swapper_tsb_phys_patch) + __swapper_tsb_phys_patch_end = .; + } + .swapper_4m_tsb_phys_patch : { + __swapper_4m_tsb_phys_patch = .; + *(.swapper_4m_tsb_phys_patch) + __swapper_4m_tsb_phys_patch_end = .; + } + .popc_3insn_patch : { + __popc_3insn_patch = .; + *(.popc_3insn_patch) + __popc_3insn_patch_end = .; + } + .popc_6insn_patch : { + __popc_6insn_patch = .; + *(.popc_6insn_patch) + __popc_6insn_patch_end = .; + } PERCPU_SECTION(SMP_CACHE_BYTES) . = ALIGN(PAGE_SIZE); diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile index 7f01b8fce8bc..a3fc4375a150 100644 --- a/arch/sparc/lib/Makefile +++ b/arch/sparc/lib/Makefile @@ -31,13 +31,13 @@ lib-$(CONFIG_SPARC64) += NGmemcpy.o NGcopy_from_user.o NGcopy_to_user.o lib-$(CONFIG_SPARC64) += NGpatch.o NGpage.o NGbzero.o lib-$(CONFIG_SPARC64) += NG2memcpy.o NG2copy_from_user.o NG2copy_to_user.o -lib-$(CONFIG_SPARC64) += NG2patch.o NG2page.o +lib-$(CONFIG_SPARC64) += NG2patch.o lib-$(CONFIG_SPARC64) += GENmemcpy.o GENcopy_from_user.o GENcopy_to_user.o lib-$(CONFIG_SPARC64) += GENpatch.o GENpage.o GENbzero.o lib-$(CONFIG_SPARC64) += copy_in_user.o user_fixup.o memmove.o -lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o +lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o hweight.o ffs.o obj-y += iomap.o obj-$(CONFIG_SPARC32) += atomic32.o diff --git a/arch/sparc/lib/NG2page.S b/arch/sparc/lib/NG2page.S deleted file mode 100644 index 73b6b7c72cbf..000000000000 --- a/arch/sparc/lib/NG2page.S +++ /dev/null @@ -1,61 +0,0 @@ -/* NG2page.S: Niagara-2 optimized clear and copy page. - * - * Copyright (C) 2007 (davem@davemloft.net) - */ - -#include <asm/asi.h> -#include <asm/page.h> -#include <asm/visasm.h> - - .text - .align 32 - - /* This is heavily simplified from the sun4u variants - * because Niagara-2 does not have any D-cache aliasing issues. - */ -NG2copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */ - prefetch [%o1 + 0x00], #one_read - prefetch [%o1 + 0x40], #one_read - VISEntryHalf - set PAGE_SIZE, %g7 - sub %o0, %o1, %g3 -1: stxa %g0, [%o1 + %g3] ASI_BLK_INIT_QUAD_LDD_P - subcc %g7, 64, %g7 - ldda [%o1] ASI_BLK_P, %f0 - stda %f0, [%o1 + %g3] ASI_BLK_P - add %o1, 64, %o1 - bne,pt %xcc, 1b - prefetch [%o1 + 0x40], #one_read - membar #Sync - VISExitHalf - retl - nop - -#define BRANCH_ALWAYS 0x10680000 -#define NOP 0x01000000 -#define NG_DO_PATCH(OLD, NEW) \ - sethi %hi(NEW), %g1; \ - or %g1, %lo(NEW), %g1; \ - sethi %hi(OLD), %g2; \ - or %g2, %lo(OLD), %g2; \ - sub %g1, %g2, %g1; \ - sethi %hi(BRANCH_ALWAYS), %g3; \ - sll %g1, 11, %g1; \ - srl %g1, 11 + 2, %g1; \ - or %g3, %lo(BRANCH_ALWAYS), %g3; \ - or %g3, %g1, %g3; \ - stw %g3, [%g2]; \ - sethi %hi(NOP), %g3; \ - or %g3, %lo(NOP), %g3; \ - stw %g3, [%g2 + 0x4]; \ - flush %g2; - - .globl niagara2_patch_pageops - .type niagara2_patch_pageops,#function -niagara2_patch_pageops: - NG_DO_PATCH(copy_user_page, NG2copy_user_page) - NG_DO_PATCH(_clear_page, NGclear_page) - NG_DO_PATCH(clear_user_page, NGclear_user_page) - retl - nop - .size niagara2_patch_pageops,.-niagara2_patch_pageops diff --git a/arch/sparc/lib/NGpage.S b/arch/sparc/lib/NGpage.S index 428920de05ba..b9e790b9c6b8 100644 --- a/arch/sparc/lib/NGpage.S +++ b/arch/sparc/lib/NGpage.S @@ -16,55 +16,91 @@ */ NGcopy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */ - prefetch [%o1 + 0x00], #one_read - mov 8, %g1 - mov 16, %g2 - mov 24, %g3 + save %sp, -192, %sp + rd %asi, %g3 + wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi set PAGE_SIZE, %g7 + prefetch [%i1 + 0x00], #one_read + prefetch [%i1 + 0x40], #one_read -1: ldda [%o1 + %g0] ASI_BLK_INIT_QUAD_LDD_P, %o2 - ldda [%o1 + %g2] ASI_BLK_INIT_QUAD_LDD_P, %o4 - prefetch [%o1 + 0x40], #one_read - add %o1, 32, %o1 - stxa %o2, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P - stxa %o3, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P - ldda [%o1 + %g0] ASI_BLK_INIT_QUAD_LDD_P, %o2 - stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P - stxa %o5, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P - ldda [%o1 + %g2] ASI_BLK_INIT_QUAD_LDD_P, %o4 - add %o1, 32, %o1 - add %o0, 32, %o0 - stxa %o2, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P - stxa %o3, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P - stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P - stxa %o5, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P - subcc %g7, 64, %g7 +1: prefetch [%i1 + 0x80], #one_read + prefetch [%i1 + 0xc0], #one_read + ldda [%i1 + 0x00] %asi, %o2 + ldda [%i1 + 0x10] %asi, %o4 + ldda [%i1 + 0x20] %asi, %l2 + ldda [%i1 + 0x30] %asi, %l4 + stxa %o2, [%i0 + 0x00] %asi + stxa %o3, [%i0 + 0x08] %asi + stxa %o4, [%i0 + 0x10] %asi + stxa %o5, [%i0 + 0x18] %asi + stxa %l2, [%i0 + 0x20] %asi + stxa %l3, [%i0 + 0x28] %asi + stxa %l4, [%i0 + 0x30] %asi + stxa %l5, [%i0 + 0x38] %asi + ldda [%i1 + 0x40] %asi, %o2 + ldda [%i1 + 0x50] %asi, %o4 + ldda [%i1 + 0x60] %asi, %l2 + ldda [%i1 + 0x70] %asi, %l4 + stxa %o2, [%i0 + 0x40] %asi + stxa %o3, [%i0 + 0x48] %asi + stxa %o4, [%i0 + 0x50] %asi + stxa %o5, [%i0 + 0x58] %asi + stxa %l2, [%i0 + 0x60] %asi + stxa %l3, [%i0 + 0x68] %asi + stxa %l4, [%i0 + 0x70] %asi + stxa %l5, [%i0 + 0x78] %asi + add %i1, 128, %i1 + subcc %g7, 128, %g7 bne,pt %xcc, 1b - add %o0, 32, %o0 + add %i0, 128, %i0 + wr %g3, 0x0, %asi membar #Sync - retl - nop + ret + restore - .globl NGclear_page, NGclear_user_page + .align 32 NGclear_page: /* %o0=dest */ NGclear_user_page: /* %o0=dest, %o1=vaddr */ - mov 8, %g1 - mov 16, %g2 - mov 24, %g3 + rd %asi, %g3 + wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi set PAGE_SIZE, %g7 -1: stxa %g0, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P - stxa %g0, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P - stxa %g0, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P - stxa %g0, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P - add %o0, 32, %o0 - stxa %g0, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P - stxa %g0, [%o0 + %g1] ASI_BLK_INIT_QUAD_LDD_P - stxa %g0, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P - stxa %g0, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P - subcc %g7, 64, %g7 +1: stxa %g0, [%o0 + 0x00] %asi + stxa %g0, [%o0 + 0x08] %asi + stxa %g0, [%o0 + 0x10] %asi + stxa %g0, [%o0 + 0x18] %asi + stxa %g0, [%o0 + 0x20] %asi + stxa %g0, [%o0 + 0x28] %asi + stxa %g0, [%o0 + 0x30] %asi + stxa %g0, [%o0 + 0x38] %asi + stxa %g0, [%o0 + 0x40] %asi + stxa %g0, [%o0 + 0x48] %asi + stxa %g0, [%o0 + 0x50] %asi + stxa %g0, [%o0 + 0x58] %asi + stxa %g0, [%o0 + 0x60] %asi + stxa %g0, [%o0 + 0x68] %asi + stxa %g0, [%o0 + 0x70] %asi + stxa %g0, [%o0 + 0x78] %asi + stxa %g0, [%o0 + 0x80] %asi + stxa %g0, [%o0 + 0x88] %asi + stxa %g0, [%o0 + 0x90] %asi + stxa %g0, [%o0 + 0x98] %asi + stxa %g0, [%o0 + 0xa0] %asi + stxa %g0, [%o0 + 0xa8] %asi + stxa %g0, [%o0 + 0xb0] %asi + stxa %g0, [%o0 + 0xb8] %asi + stxa %g0, [%o0 + 0xc0] %asi + stxa %g0, [%o0 + 0xc8] %asi + stxa %g0, [%o0 + 0xd0] %asi + stxa %g0, [%o0 + 0xd8] %asi + stxa %g0, [%o0 + 0xe0] %asi + stxa %g0, [%o0 + 0xe8] %asi + stxa %g0, [%o0 + 0xf0] %asi + stxa %g0, [%o0 + 0xf8] %asi + subcc %g7, 256, %g7 bne,pt %xcc, 1b - add %o0, 32, %o0 + add %o0, 256, %o0 + wr %g3, 0x0, %asi membar #Sync retl nop diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index 8600eb2461b5..1d32b54089aa 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -65,7 +65,7 @@ int __atomic_add_unless(atomic_t *v, int a, int u) if (ret != u) v->counter += a; spin_unlock_irqrestore(ATOMIC_HASH(v), flags); - return ret != u; + return ret; } EXPORT_SYMBOL(__atomic_add_unless); diff --git a/arch/sparc/lib/ffs.S b/arch/sparc/lib/ffs.S new file mode 100644 index 000000000000..b39389f69899 --- /dev/null +++ b/arch/sparc/lib/ffs.S @@ -0,0 +1,84 @@ +#include <linux/linkage.h> + + .register %g2,#scratch + + .text + .align 32 + +ENTRY(ffs) + brnz,pt %o0, 1f + mov 1, %o1 + retl + clr %o0 + nop + nop +ENTRY(__ffs) + sllx %o0, 32, %g1 /* 1 */ + srlx %o0, 32, %g2 + + clr %o1 /* 2 */ + movrz %g1, %g2, %o0 + + movrz %g1, 32, %o1 /* 3 */ +1: clr %o2 + + sllx %o0, (64 - 16), %g1 /* 4 */ + srlx %o0, 16, %g2 + + movrz %g1, %g2, %o0 /* 5 */ + clr %o3 + + movrz %g1, 16, %o2 /* 6 */ + clr %o4 + + and %o0, 0xff, %g1 /* 7 */ + srlx %o0, 8, %g2 + + movrz %g1, %g2, %o0 /* 8 */ + clr %o5 + + movrz %g1, 8, %o3 /* 9 */ + add %o2, %o1, %o2 + + and %o0, 0xf, %g1 /* 10 */ + srlx %o0, 4, %g2 + + movrz %g1, %g2, %o0 /* 11 */ + add %o2, %o3, %o2 + + movrz %g1, 4, %o4 /* 12 */ + + and %o0, 0x3, %g1 /* 13 */ + srlx %o0, 2, %g2 + + movrz %g1, %g2, %o0 /* 14 */ + add %o2, %o4, %o2 + + movrz %g1, 2, %o5 /* 15 */ + + and %o0, 0x1, %g1 /* 16 */ + + add %o2, %o5, %o2 /* 17 */ + xor %g1, 0x1, %g1 + + retl /* 18 */ + add %o2, %g1, %o0 +ENDPROC(ffs) +ENDPROC(__ffs) + + .section .popc_6insn_patch, "ax" + .word ffs + brz,pn %o0, 98f + neg %o0, %g1 + xnor %o0, %g1, %o1 + popc %o1, %o0 +98: retl + nop + .word __ffs + neg %o0, %g1 + xnor %o0, %g1, %o1 + popc %o1, %o0 + retl + sub %o0, 1, %o0 + nop + .previous diff --git a/arch/sparc/lib/hweight.S b/arch/sparc/lib/hweight.S new file mode 100644 index 000000000000..95414e0a6808 --- /dev/null +++ b/arch/sparc/lib/hweight.S @@ -0,0 +1,51 @@ +#include <linux/linkage.h> + + .text + .align 32 +ENTRY(__arch_hweight8) + ba,pt %xcc, __sw_hweight8 + nop + nop +ENDPROC(__arch_hweight8) + .section .popc_3insn_patch, "ax" + .word __arch_hweight8 + sllx %o0, 64-8, %g1 + retl + popc %g1, %o0 + .previous + +ENTRY(__arch_hweight16) + ba,pt %xcc, __sw_hweight16 + nop + nop +ENDPROC(__arch_hweight16) + .section .popc_3insn_patch, "ax" + .word __arch_hweight16 + sllx %o0, 64-16, %g1 + retl + popc %g1, %o0 + .previous + +ENTRY(__arch_hweight32) + ba,pt %xcc, __sw_hweight32 + nop + nop +ENDPROC(__arch_hweight32) + .section .popc_3insn_patch, "ax" + .word __arch_hweight32 + sllx %o0, 64-32, %g1 + retl + popc %g1, %o0 + .previous + +ENTRY(__arch_hweight64) + ba,pt %xcc, __sw_hweight64 + nop + nop +ENDPROC(__arch_hweight64) + .section .popc_3insn_patch, "ax" + .word __arch_hweight64 + retl + popc %o0, %o0 + nop + .previous diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 3fd8e18bed80..581531dbc8b5 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -1597,6 +1597,44 @@ static void __init tsb_phys_patch(void) static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; +static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) +{ + pa >>= KTSB_PHYS_SHIFT; + + while (start < end) { + unsigned int *ia = (unsigned int *)(unsigned long)*start; + + ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10); + __asm__ __volatile__("flush %0" : : "r" (ia)); + + ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff); + __asm__ __volatile__("flush %0" : : "r" (ia + 1)); + + start++; + } +} + +static void ktsb_phys_patch(void) +{ + extern unsigned int __swapper_tsb_phys_patch; + extern unsigned int __swapper_tsb_phys_patch_end; + unsigned long ktsb_pa; + + ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); + patch_one_ktsb_phys(&__swapper_tsb_phys_patch, + &__swapper_tsb_phys_patch_end, ktsb_pa); +#ifndef CONFIG_DEBUG_PAGEALLOC + { + extern unsigned int __swapper_4m_tsb_phys_patch; + extern unsigned int __swapper_4m_tsb_phys_patch_end; + ktsb_pa = (kern_base + + ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); + patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, + &__swapper_4m_tsb_phys_patch_end, ktsb_pa); + } +#endif +} + static void __init sun4v_ktsb_init(void) { unsigned long ktsb_pa; @@ -1716,8 +1754,10 @@ void __init paging_init(void) sun4u_pgprot_init(); if (tlb_type == cheetah_plus || - tlb_type == hypervisor) + tlb_type == hypervisor) { tsb_phys_patch(); + ktsb_phys_patch(); + } if (tlb_type == hypervisor) { sun4v_patch_tlb_handlers(); diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile index 45e94aca5bce..3326204e251f 100644 --- a/arch/x86/xen/Makefile +++ b/arch/x86/xen/Makefile @@ -15,7 +15,7 @@ obj-y := enlighten.o setup.o multicalls.o mmu.o irq.o \ grant-table.o suspend.o platform-pci-unplug.o \ p2m.o -obj-$(CONFIG_FUNCTION_TRACER) += trace.o +obj-$(CONFIG_FTRACE) += trace.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index a9627e2e3295..df118a825f39 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -93,8 +93,6 @@ static unsigned long __init xen_release_chunk(phys_addr_t start_addr, if (end <= start) return 0; - printk(KERN_INFO "xen_release_chunk: looking at area pfn %lx-%lx: ", - start, end); for(pfn = start; pfn < end; pfn++) { unsigned long mfn = pfn_to_mfn(pfn); @@ -107,14 +105,14 @@ static unsigned long __init xen_release_chunk(phys_addr_t start_addr, ret = HYPERVISOR_memory_op(XENMEM_decrease_reservation, &reservation); - WARN(ret != 1, "Failed to release memory %lx-%lx err=%d\n", - start, end, ret); + WARN(ret != 1, "Failed to release pfn %lx err=%d\n", pfn, ret); if (ret == 1) { __set_phys_to_machine(pfn, INVALID_P2M_ENTRY); len++; } } - printk(KERN_CONT "%ld pages freed\n", len); + printk(KERN_INFO "Freeing %lx-%lx pfn range: %lu pages freed\n", + start, end, len); return len; } @@ -140,7 +138,7 @@ static unsigned long __init xen_return_unused_memory(unsigned long max_pfn, if (last_end < max_addr) released += xen_release_chunk(last_end, max_addr); - printk(KERN_INFO "released %ld pages of unused memory\n", released); + printk(KERN_INFO "released %lu pages of unused memory\n", released); return released; } diff --git a/arch/x86/xen/trace.c b/arch/x86/xen/trace.c index 734beba2a08c..520022d1a181 100644 --- a/arch/x86/xen/trace.c +++ b/arch/x86/xen/trace.c @@ -1,4 +1,5 @@ #include <linux/ftrace.h> +#include <xen/interface/xen.h> #define N(x) [__HYPERVISOR_##x] = "("#x")" static const char *xen_hypercall_names[] = { diff --git a/crypto/md5.c b/crypto/md5.c index 30efc7dad891..7febeaab923b 100644 --- a/crypto/md5.c +++ b/crypto/md5.c @@ -21,99 +21,9 @@ #include <linux/module.h> #include <linux/string.h> #include <linux/types.h> +#include <linux/cryptohash.h> #include <asm/byteorder.h> -#define F1(x, y, z) (z ^ (x & (y ^ z))) -#define F2(x, y, z) F1(z, x, y) -#define F3(x, y, z) (x ^ y ^ z) -#define F4(x, y, z) (y ^ (x | ~z)) - -#define MD5STEP(f, w, x, y, z, in, s) \ - (w += f(x, y, z) + in, w = (w<<s | w>>(32-s)) + x) - -static void md5_transform(u32 *hash, u32 const *in) -{ - u32 a, b, c, d; - - a = hash[0]; - b = hash[1]; - c = hash[2]; - d = hash[3]; - - MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); - MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); - MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); - MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); - MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); - MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); - MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); - MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); - MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); - MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); - MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); - MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); - MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); - MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); - MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); - MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); - - MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); - MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); - MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); - MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); - MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); - MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); - MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); - MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); - MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); - MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); - MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); - MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); - MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); - MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); - MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); - MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); - - MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); - MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); - MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); - MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); - MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); - MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); - MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); - MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); - MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); - MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); - MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); - MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); - MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); - MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); - MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); - MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); - - MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); - MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); - MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); - MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); - MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); - MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); - MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); - MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); - MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); - MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); - MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); - MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); - MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); - MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); - MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); - MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); - - hash[0] += a; - hash[1] += b; - hash[2] += c; - hash[3] += d; -} - /* XXX: this stuff can be optimized */ static inline void le32_to_cpu_array(u32 *buf, unsigned int words) { diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index 87c0a8daa99a..7711d94a0409 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -99,6 +99,7 @@ enum { struct acpi_battery { struct mutex lock; + struct mutex sysfs_lock; struct power_supply bat; struct acpi_device *device; struct notifier_block pm_nb; @@ -573,16 +574,16 @@ static int sysfs_add_battery(struct acpi_battery *battery) static void sysfs_remove_battery(struct acpi_battery *battery) { - mutex_lock(&battery->lock); + mutex_lock(&battery->sysfs_lock); if (!battery->bat.dev) { - mutex_unlock(&battery->lock); + mutex_unlock(&battery->sysfs_lock); return; } device_remove_file(battery->bat.dev, &alarm_attr); power_supply_unregister(&battery->bat); battery->bat.dev = NULL; - mutex_unlock(&battery->lock); + mutex_unlock(&battery->sysfs_lock); } /* @@ -982,6 +983,7 @@ static int acpi_battery_add(struct acpi_device *device) strcpy(acpi_device_class(device), ACPI_BATTERY_CLASS); device->driver_data = battery; mutex_init(&battery->lock); + mutex_init(&battery->sysfs_lock); if (ACPI_SUCCESS(acpi_get_handle(battery->device->handle, "_BIX", &handle))) set_bit(ACPI_BATTERY_XINFO_PRESENT, &battery->flags); @@ -1010,6 +1012,7 @@ static int acpi_battery_add(struct acpi_device *device) fail: sysfs_remove_battery(battery); mutex_destroy(&battery->lock); + mutex_destroy(&battery->sysfs_lock); kfree(battery); return result; } @@ -1027,6 +1030,7 @@ static int acpi_battery_remove(struct acpi_device *device, int type) #endif sysfs_remove_battery(battery); mutex_destroy(&battery->lock); + mutex_destroy(&battery->sysfs_lock); kfree(battery); return 0; } diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index be8714aa9dd6..e18566a0fedd 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -80,7 +80,6 @@ static void genpd_set_active(struct generic_pm_domain *genpd) int pm_genpd_poweron(struct generic_pm_domain *genpd) { struct generic_pm_domain *parent = genpd->parent; - DEFINE_WAIT(wait); int ret = 0; start: @@ -112,7 +111,7 @@ int pm_genpd_poweron(struct generic_pm_domain *genpd) } if (genpd->power_on) { - int ret = genpd->power_on(genpd); + ret = genpd->power_on(genpd); if (ret) goto out; } diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c index 8dc247c974af..acb3f83b8079 100644 --- a/drivers/base/power/runtime.c +++ b/drivers/base/power/runtime.c @@ -226,11 +226,17 @@ static int rpm_idle(struct device *dev, int rpmflags) callback = NULL; if (callback) { - spin_unlock_irq(&dev->power.lock); + if (dev->power.irq_safe) + spin_unlock(&dev->power.lock); + else + spin_unlock_irq(&dev->power.lock); callback(dev); - spin_lock_irq(&dev->power.lock); + if (dev->power.irq_safe) + spin_lock(&dev->power.lock); + else + spin_lock_irq(&dev->power.lock); } dev->power.idle_notification = false; diff --git a/drivers/char/random.c b/drivers/char/random.c index 729281961f22..c35a785005b0 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -1300,345 +1300,14 @@ ctl_table random_table[] = { }; #endif /* CONFIG_SYSCTL */ -/******************************************************************** - * - * Random functions for networking - * - ********************************************************************/ - -/* - * TCP initial sequence number picking. This uses the random number - * generator to pick an initial secret value. This value is hashed - * along with the TCP endpoint information to provide a unique - * starting point for each pair of TCP endpoints. This defeats - * attacks which rely on guessing the initial TCP sequence number. - * This algorithm was suggested by Steve Bellovin. - * - * Using a very strong hash was taking an appreciable amount of the total - * TCP connection establishment time, so this is a weaker hash, - * compensated for by changing the secret periodically. - */ - -/* F, G and H are basic MD4 functions: selection, majority, parity */ -#define F(x, y, z) ((z) ^ ((x) & ((y) ^ (z)))) -#define G(x, y, z) (((x) & (y)) + (((x) ^ (y)) & (z))) -#define H(x, y, z) ((x) ^ (y) ^ (z)) - -/* - * The generic round function. The application is so specific that - * we don't bother protecting all the arguments with parens, as is generally - * good macro practice, in favor of extra legibility. - * Rotation is separate from addition to prevent recomputation - */ -#define ROUND(f, a, b, c, d, x, s) \ - (a += f(b, c, d) + x, a = (a << s) | (a >> (32 - s))) -#define K1 0 -#define K2 013240474631UL -#define K3 015666365641UL - -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) - -static __u32 twothirdsMD4Transform(__u32 const buf[4], __u32 const in[12]) -{ - __u32 a = buf[0], b = buf[1], c = buf[2], d = buf[3]; - - /* Round 1 */ - ROUND(F, a, b, c, d, in[ 0] + K1, 3); - ROUND(F, d, a, b, c, in[ 1] + K1, 7); - ROUND(F, c, d, a, b, in[ 2] + K1, 11); - ROUND(F, b, c, d, a, in[ 3] + K1, 19); - ROUND(F, a, b, c, d, in[ 4] + K1, 3); - ROUND(F, d, a, b, c, in[ 5] + K1, 7); - ROUND(F, c, d, a, b, in[ 6] + K1, 11); - ROUND(F, b, c, d, a, in[ 7] + K1, 19); - ROUND(F, a, b, c, d, in[ 8] + K1, 3); - ROUND(F, d, a, b, c, in[ 9] + K1, 7); - ROUND(F, c, d, a, b, in[10] + K1, 11); - ROUND(F, b, c, d, a, in[11] + K1, 19); - - /* Round 2 */ - ROUND(G, a, b, c, d, in[ 1] + K2, 3); - ROUND(G, d, a, b, c, in[ 3] + K2, 5); - ROUND(G, c, d, a, b, in[ 5] + K2, 9); - ROUND(G, b, c, d, a, in[ 7] + K2, 13); - ROUND(G, a, b, c, d, in[ 9] + K2, 3); - ROUND(G, d, a, b, c, in[11] + K2, 5); - ROUND(G, c, d, a, b, in[ 0] + K2, 9); - ROUND(G, b, c, d, a, in[ 2] + K2, 13); - ROUND(G, a, b, c, d, in[ 4] + K2, 3); - ROUND(G, d, a, b, c, in[ 6] + K2, 5); - ROUND(G, c, d, a, b, in[ 8] + K2, 9); - ROUND(G, b, c, d, a, in[10] + K2, 13); - - /* Round 3 */ - ROUND(H, a, b, c, d, in[ 3] + K3, 3); - ROUND(H, d, a, b, c, in[ 7] + K3, 9); - ROUND(H, c, d, a, b, in[11] + K3, 11); - ROUND(H, b, c, d, a, in[ 2] + K3, 15); - ROUND(H, a, b, c, d, in[ 6] + K3, 3); - ROUND(H, d, a, b, c, in[10] + K3, 9); - ROUND(H, c, d, a, b, in[ 1] + K3, 11); - ROUND(H, b, c, d, a, in[ 5] + K3, 15); - ROUND(H, a, b, c, d, in[ 9] + K3, 3); - ROUND(H, d, a, b, c, in[ 0] + K3, 9); - ROUND(H, c, d, a, b, in[ 4] + K3, 11); - ROUND(H, b, c, d, a, in[ 8] + K3, 15); - - return buf[1] + b; /* "most hashed" word */ - /* Alternative: return sum of all words? */ -} -#endif - -#undef ROUND -#undef F -#undef G -#undef H -#undef K1 -#undef K2 -#undef K3 - -/* This should not be decreased so low that ISNs wrap too fast. */ -#define REKEY_INTERVAL (300 * HZ) -/* - * Bit layout of the tcp sequence numbers (before adding current time): - * bit 24-31: increased after every key exchange - * bit 0-23: hash(source,dest) - * - * The implementation is similar to the algorithm described - * in the Appendix of RFC 1185, except that - * - it uses a 1 MHz clock instead of a 250 kHz clock - * - it performs a rekey every 5 minutes, which is equivalent - * to a (source,dest) tulple dependent forward jump of the - * clock by 0..2^(HASH_BITS+1) - * - * Thus the average ISN wraparound time is 68 minutes instead of - * 4.55 hours. - * - * SMP cleanup and lock avoidance with poor man's RCU. - * Manfred Spraul <manfred@colorfullife.com> - * - */ -#define COUNT_BITS 8 -#define COUNT_MASK ((1 << COUNT_BITS) - 1) -#define HASH_BITS 24 -#define HASH_MASK ((1 << HASH_BITS) - 1) +static u32 random_int_secret[MD5_MESSAGE_BYTES / 4] ____cacheline_aligned; -static struct keydata { - __u32 count; /* already shifted to the final position */ - __u32 secret[12]; -} ____cacheline_aligned ip_keydata[2]; - -static unsigned int ip_cnt; - -static void rekey_seq_generator(struct work_struct *work); - -static DECLARE_DELAYED_WORK(rekey_work, rekey_seq_generator); - -/* - * Lock avoidance: - * The ISN generation runs lockless - it's just a hash over random data. - * State changes happen every 5 minutes when the random key is replaced. - * Synchronization is performed by having two copies of the hash function - * state and rekey_seq_generator always updates the inactive copy. - * The copy is then activated by updating ip_cnt. - * The implementation breaks down if someone blocks the thread - * that processes SYN requests for more than 5 minutes. Should never - * happen, and even if that happens only a not perfectly compliant - * ISN is generated, nothing fatal. - */ -static void rekey_seq_generator(struct work_struct *work) +static int __init random_int_secret_init(void) { - struct keydata *keyptr = &ip_keydata[1 ^ (ip_cnt & 1)]; - - get_random_bytes(keyptr->secret, sizeof(keyptr->secret)); - keyptr->count = (ip_cnt & COUNT_MASK) << HASH_BITS; - smp_wmb(); - ip_cnt++; - schedule_delayed_work(&rekey_work, - round_jiffies_relative(REKEY_INTERVAL)); -} - -static inline struct keydata *get_keyptr(void) -{ - struct keydata *keyptr = &ip_keydata[ip_cnt & 1]; - - smp_rmb(); - - return keyptr; -} - -static __init int seqgen_init(void) -{ - rekey_seq_generator(NULL); + get_random_bytes(random_int_secret, sizeof(random_int_secret)); return 0; } -late_initcall(seqgen_init); - -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -__u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr, - __be16 sport, __be16 dport) -{ - __u32 seq; - __u32 hash[12]; - struct keydata *keyptr = get_keyptr(); - - /* The procedure is the same as for IPv4, but addresses are longer. - * Thus we must use twothirdsMD4Transform. - */ - - memcpy(hash, saddr, 16); - hash[4] = ((__force u16)sport << 16) + (__force u16)dport; - memcpy(&hash[5], keyptr->secret, sizeof(__u32) * 7); - - seq = twothirdsMD4Transform((const __u32 *)daddr, hash) & HASH_MASK; - seq += keyptr->count; - - seq += ktime_to_ns(ktime_get_real()); - - return seq; -} -EXPORT_SYMBOL(secure_tcpv6_sequence_number); -#endif - -/* The code below is shamelessly stolen from secure_tcp_sequence_number(). - * All blames to Andrey V. Savochkin <saw@msu.ru>. - */ -__u32 secure_ip_id(__be32 daddr) -{ - struct keydata *keyptr; - __u32 hash[4]; - - keyptr = get_keyptr(); - - /* - * Pick a unique starting offset for each IP destination. - * The dest ip address is placed in the starting vector, - * which is then hashed with random data. - */ - hash[0] = (__force __u32)daddr; - hash[1] = keyptr->secret[9]; - hash[2] = keyptr->secret[10]; - hash[3] = keyptr->secret[11]; - - return half_md4_transform(hash, keyptr->secret); -} - -__u32 secure_ipv6_id(const __be32 daddr[4]) -{ - const struct keydata *keyptr; - __u32 hash[4]; - - keyptr = get_keyptr(); - - hash[0] = (__force __u32)daddr[0]; - hash[1] = (__force __u32)daddr[1]; - hash[2] = (__force __u32)daddr[2]; - hash[3] = (__force __u32)daddr[3]; - - return half_md4_transform(hash, keyptr->secret); -} - -#ifdef CONFIG_INET - -__u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr, - __be16 sport, __be16 dport) -{ - __u32 seq; - __u32 hash[4]; - struct keydata *keyptr = get_keyptr(); - - /* - * Pick a unique starting offset for each TCP connection endpoints - * (saddr, daddr, sport, dport). - * Note that the words are placed into the starting vector, which is - * then mixed with a partial MD4 over random data. - */ - hash[0] = (__force u32)saddr; - hash[1] = (__force u32)daddr; - hash[2] = ((__force u16)sport << 16) + (__force u16)dport; - hash[3] = keyptr->secret[11]; - - seq = half_md4_transform(hash, keyptr->secret) & HASH_MASK; - seq += keyptr->count; - /* - * As close as possible to RFC 793, which - * suggests using a 250 kHz clock. - * Further reading shows this assumes 2 Mb/s networks. - * For 10 Mb/s Ethernet, a 1 MHz clock is appropriate. - * For 10 Gb/s Ethernet, a 1 GHz clock should be ok, but - * we also need to limit the resolution so that the u32 seq - * overlaps less than one time per MSL (2 minutes). - * Choosing a clock of 64 ns period is OK. (period of 274 s) - */ - seq += ktime_to_ns(ktime_get_real()) >> 6; - - return seq; -} - -/* Generate secure starting point for ephemeral IPV4 transport port search */ -u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport) -{ - struct keydata *keyptr = get_keyptr(); - u32 hash[4]; - - /* - * Pick a unique starting offset for each ephemeral port search - * (saddr, daddr, dport) and 48bits of random data. - */ - hash[0] = (__force u32)saddr; - hash[1] = (__force u32)daddr; - hash[2] = (__force u32)dport ^ keyptr->secret[10]; - hash[3] = keyptr->secret[11]; - - return half_md4_transform(hash, keyptr->secret); -} -EXPORT_SYMBOL_GPL(secure_ipv4_port_ephemeral); - -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, - __be16 dport) -{ - struct keydata *keyptr = get_keyptr(); - u32 hash[12]; - - memcpy(hash, saddr, 16); - hash[4] = (__force u32)dport; - memcpy(&hash[5], keyptr->secret, sizeof(__u32) * 7); - - return twothirdsMD4Transform((const __u32 *)daddr, hash); -} -#endif - -#if defined(CONFIG_IP_DCCP) || defined(CONFIG_IP_DCCP_MODULE) -/* Similar to secure_tcp_sequence_number but generate a 48 bit value - * bit's 32-47 increase every key exchange - * 0-31 hash(source, dest) - */ -u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr, - __be16 sport, __be16 dport) -{ - u64 seq; - __u32 hash[4]; - struct keydata *keyptr = get_keyptr(); - - hash[0] = (__force u32)saddr; - hash[1] = (__force u32)daddr; - hash[2] = ((__force u16)sport << 16) + (__force u16)dport; - hash[3] = keyptr->secret[11]; - - seq = half_md4_transform(hash, keyptr->secret); - seq |= ((u64)keyptr->count) << (32 - HASH_BITS); - - seq += ktime_to_ns(ktime_get_real()); - seq &= (1ull << 48) - 1; - - return seq; -} -EXPORT_SYMBOL(secure_dccp_sequence_number); -#endif - -#endif /* CONFIG_INET */ - +late_initcall(random_int_secret_init); /* * Get a random word for internal kernel use only. Similar to urandom but @@ -1646,17 +1315,15 @@ EXPORT_SYMBOL(secure_dccp_sequence_number); * value is not cryptographically secure but for several uses the cost of * depleting entropy is too high */ -DEFINE_PER_CPU(__u32 [4], get_random_int_hash); +DEFINE_PER_CPU(__u32 [MD5_DIGEST_WORDS], get_random_int_hash); unsigned int get_random_int(void) { - struct keydata *keyptr; __u32 *hash = get_cpu_var(get_random_int_hash); - int ret; + unsigned int ret; - keyptr = get_keyptr(); hash[0] += current->pid + jiffies + get_cycles(); - - ret = half_md4_transform(hash, keyptr->secret); + md5_transform(hash, random_int_secret); + ret = hash[0]; put_cpu_var(get_random_int_hash); return ret; diff --git a/drivers/connector/cn_proc.c b/drivers/connector/cn_proc.c index 3ee1fdb31ea7..e55814bc0d06 100644 --- a/drivers/connector/cn_proc.c +++ b/drivers/connector/cn_proc.c @@ -57,6 +57,7 @@ void proc_fork_connector(struct task_struct *task) struct proc_event *ev; __u8 buffer[CN_PROC_MSG_SIZE]; struct timespec ts; + struct task_struct *parent; if (atomic_read(&proc_event_num_listeners) < 1) return; @@ -67,8 +68,11 @@ void proc_fork_connector(struct task_struct *task) ktime_get_ts(&ts); /* get high res monotonic timestamp */ put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns); ev->what = PROC_EVENT_FORK; - ev->event_data.fork.parent_pid = task->real_parent->pid; - ev->event_data.fork.parent_tgid = task->real_parent->tgid; + rcu_read_lock(); + parent = rcu_dereference(task->real_parent); + ev->event_data.fork.parent_pid = parent->pid; + ev->event_data.fork.parent_tgid = parent->tgid; + rcu_read_unlock(); ev->event_data.fork.child_pid = task->pid; ev->event_data.fork.child_tgid = task->tgid; diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 26374b2a55a2..b48967b499da 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -62,9 +62,9 @@ #include <linux/slab.h> static DEFINE_MUTEX(dma_list_mutex); +static DEFINE_IDR(dma_idr); static LIST_HEAD(dma_device_list); static long dmaengine_ref_count; -static struct idr dma_idr; /* --- sysfs implementation --- */ @@ -1050,8 +1050,6 @@ EXPORT_SYMBOL_GPL(dma_run_dependencies); static int __init dma_bus_init(void) { - idr_init(&dma_idr); - mutex_init(&dma_list_mutex); return class_register(&dma_devclass); } arch_initcall(dma_bus_init); diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index d845dc4b7103..f519c93a61e7 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -73,10 +73,10 @@ /* provide a lookup table for setting the source address in the base or * extended descriptor of an xor or pq descriptor */ -static const u8 xor_idx_to_desc __read_mostly = 0xd0; -static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 }; -static const u8 pq_idx_to_desc __read_mostly = 0xf8; -static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 }; +static const u8 xor_idx_to_desc = 0xe0; +static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; +static const u8 pq_idx_to_desc = 0xf8; +static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) { diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index fab37d1cf48d..5e3a40f79945 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -72,6 +72,17 @@ static struct pci_device_id ioat_pci_tbl[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, + { 0, } }; MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index af1a17d42bd7..c422fead0855 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -41,7 +41,7 @@ config EDAC_DEBUG config EDAC_DECODE_MCE tristate "Decode MCEs in human-readable form (only on AMD for now)" - depends on CPU_SUP_AMD && X86_MCE + depends on CPU_SUP_AMD && X86_MCE_AMD default y ---help--- Enable this option if you want to decode Machine Check Exceptions @@ -173,8 +173,7 @@ config EDAC_I5400 config EDAC_I7CORE tristate "Intel i7 Core (Nehalem) processors" - depends on EDAC_MM_EDAC && PCI && X86 - select EDAC_MCE + depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL help Support for error detection and correction the Intel i7 Core (Nehalem) Integrated Memory Controller that exists on diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c index 9d8c892d07c9..9d2668a50872 100644 --- a/drivers/gpu/drm/drm_debugfs.c +++ b/drivers/gpu/drm/drm_debugfs.c @@ -90,7 +90,6 @@ int drm_debugfs_create_files(struct drm_info_list *files, int count, struct drm_device *dev = minor->dev; struct dentry *ent; struct drm_info_node *tmp; - char name[64]; int i, ret; for (i = 0; i < count; i++) { @@ -108,6 +107,9 @@ int drm_debugfs_create_files(struct drm_info_list *files, int count, ent = debugfs_create_file(files[i].name, S_IFREG | S_IRUGO, root, tmp, &drm_debugfs_fops); if (!ent) { + char name[64]; + strncpy(name, root->d_name.name, + min(root->d_name.len, 64U)); DRM_ERROR("Cannot create /sys/kernel/debug/dri/%s/%s\n", name, files[i].name); kfree(tmp); diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 756af4d7ec74..7425e5c9bd75 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -127,6 +127,23 @@ static const u8 edid_header[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; + /* + * Sanity check the header of the base EDID block. Return 8 if the header + * is perfect, down to 0 if it's totally wrong. + */ +int drm_edid_header_is_valid(const u8 *raw_edid) +{ + int i, score = 0; + + for (i = 0; i < sizeof(edid_header); i++) + if (raw_edid[i] == edid_header[i]) + score++; + + return score; +} +EXPORT_SYMBOL(drm_edid_header_is_valid); + + /* * Sanity check the EDID block (base or extension). Return 0 if the block * doesn't check out, or 1 if it's valid. @@ -139,12 +156,7 @@ drm_edid_block_valid(u8 *raw_edid) struct edid *edid = (struct edid *)raw_edid; if (raw_edid[0] == 0x00) { - int score = 0; - - for (i = 0; i < sizeof(edid_header); i++) - if (raw_edid[i] == edid_header[i]) - score++; - + int score = drm_edid_header_is_valid(raw_edid); if (score == 8) ; else if (score >= 6) { DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); @@ -1439,6 +1451,8 @@ EXPORT_SYMBOL(drm_detect_monitor_audio); static void drm_add_display_info(struct edid *edid, struct drm_display_info *info) { + u8 *edid_ext; + info->width_mm = edid->width_cm * 10; info->height_mm = edid->height_cm * 10; @@ -1483,6 +1497,13 @@ static void drm_add_display_info(struct edid *edid, info->color_formats = DRM_COLOR_FORMAT_YCRCB444; if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB422) info->color_formats = DRM_COLOR_FORMAT_YCRCB422; + + /* Get data from CEA blocks if present */ + edid_ext = drm_find_cea_extension(edid); + if (!edid_ext) + return; + + info->cea_rev = edid_ext[1]; } /** diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 2022a5c966bb..3830e9e478c0 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -291,11 +291,14 @@ static void drm_irq_vgaarb_nokms(void *cookie, bool state) if (!dev->irq_enabled) return; - if (state) - dev->driver->irq_uninstall(dev); - else { - dev->driver->irq_preinstall(dev); - dev->driver->irq_postinstall(dev); + if (state) { + if (dev->driver->irq_uninstall) + dev->driver->irq_uninstall(dev); + } else { + if (dev->driver->irq_preinstall) + dev->driver->irq_preinstall(dev); + if (dev->driver->irq_postinstall) + dev->driver->irq_postinstall(dev); } } @@ -338,7 +341,8 @@ int drm_irq_install(struct drm_device *dev) DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev)); /* Before installing handler */ - dev->driver->irq_preinstall(dev); + if (dev->driver->irq_preinstall) + dev->driver->irq_preinstall(dev); /* Install handler */ if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED)) @@ -363,11 +367,16 @@ int drm_irq_install(struct drm_device *dev) vga_client_register(dev->pdev, (void *)dev, drm_irq_vgaarb_nokms, NULL); /* After installing handler */ - ret = dev->driver->irq_postinstall(dev); + if (dev->driver->irq_postinstall) + ret = dev->driver->irq_postinstall(dev); + if (ret < 0) { mutex_lock(&dev->struct_mutex); dev->irq_enabled = 0; mutex_unlock(&dev->struct_mutex); + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + vga_client_register(dev->pdev, NULL, NULL, NULL); + free_irq(drm_dev_to_irq(dev), dev); } return ret; @@ -413,7 +422,8 @@ int drm_irq_uninstall(struct drm_device *dev) if (!drm_core_check_feature(dev, DRIVER_MODESET)) vga_client_register(dev->pdev, NULL, NULL, NULL); - dev->driver->irq_uninstall(dev); + if (dev->driver->irq_uninstall) + dev->driver->irq_uninstall(dev); free_irq(drm_dev_to_irq(dev), dev); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e2662497d50f..a8ab6263e0d7 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1338,6 +1338,155 @@ static const struct file_operations i915_wedged_fops = { .llseek = default_llseek, }; +static int +i915_max_freq_open(struct inode *inode, + struct file *filp) +{ + filp->private_data = inode->i_private; + return 0; +} + +static ssize_t +i915_max_freq_read(struct file *filp, + char __user *ubuf, + size_t max, + loff_t *ppos) +{ + struct drm_device *dev = filp->private_data; + drm_i915_private_t *dev_priv = dev->dev_private; + char buf[80]; + int len; + + len = snprintf(buf, sizeof (buf), + "max freq: %d\n", dev_priv->max_delay * 50); + + if (len > sizeof (buf)) + len = sizeof (buf); + + return simple_read_from_buffer(ubuf, max, ppos, buf, len); +} + +static ssize_t +i915_max_freq_write(struct file *filp, + const char __user *ubuf, + size_t cnt, + loff_t *ppos) +{ + struct drm_device *dev = filp->private_data; + struct drm_i915_private *dev_priv = dev->dev_private; + char buf[20]; + int val = 1; + + if (cnt > 0) { + if (cnt > sizeof (buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, ubuf, cnt)) + return -EFAULT; + buf[cnt] = 0; + + val = simple_strtoul(buf, NULL, 0); + } + + DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); + + /* + * Turbo will still be enabled, but won't go above the set value. + */ + dev_priv->max_delay = val / 50; + + gen6_set_rps(dev, val / 50); + + return cnt; +} + +static const struct file_operations i915_max_freq_fops = { + .owner = THIS_MODULE, + .open = i915_max_freq_open, + .read = i915_max_freq_read, + .write = i915_max_freq_write, + .llseek = default_llseek, +}; + +static int +i915_cache_sharing_open(struct inode *inode, + struct file *filp) +{ + filp->private_data = inode->i_private; + return 0; +} + +static ssize_t +i915_cache_sharing_read(struct file *filp, + char __user *ubuf, + size_t max, + loff_t *ppos) +{ + struct drm_device *dev = filp->private_data; + drm_i915_private_t *dev_priv = dev->dev_private; + char buf[80]; + u32 snpcr; + int len; + + mutex_lock(&dev_priv->dev->struct_mutex); + snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); + mutex_unlock(&dev_priv->dev->struct_mutex); + + len = snprintf(buf, sizeof (buf), + "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> + GEN6_MBC_SNPCR_SHIFT); + + if (len > sizeof (buf)) + len = sizeof (buf); + + return simple_read_from_buffer(ubuf, max, ppos, buf, len); +} + +static ssize_t +i915_cache_sharing_write(struct file *filp, + const char __user *ubuf, + size_t cnt, + loff_t *ppos) +{ + struct drm_device *dev = filp->private_data; + struct drm_i915_private *dev_priv = dev->dev_private; + char buf[20]; + u32 snpcr; + int val = 1; + + if (cnt > 0) { + if (cnt > sizeof (buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, ubuf, cnt)) + return -EFAULT; + buf[cnt] = 0; + + val = simple_strtoul(buf, NULL, 0); + } + + if (val < 0 || val > 3) + return -EINVAL; + + DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); + + /* Update the cache sharing policy here as well */ + snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); + snpcr &= ~GEN6_MBC_SNPCR_MASK; + snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); + I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); + + return cnt; +} + +static const struct file_operations i915_cache_sharing_fops = { + .owner = THIS_MODULE, + .open = i915_cache_sharing_open, + .read = i915_cache_sharing_read, + .write = i915_cache_sharing_write, + .llseek = default_llseek, +}; + /* As the drm_debugfs_init() routines are called before dev->dev_private is * allocated we need to hook into the minor for release. */ static int @@ -1437,6 +1586,36 @@ static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); } +static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor) +{ + struct drm_device *dev = minor->dev; + struct dentry *ent; + + ent = debugfs_create_file("i915_max_freq", + S_IRUGO | S_IWUSR, + root, dev, + &i915_max_freq_fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + + return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops); +} + +static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor) +{ + struct drm_device *dev = minor->dev; + struct dentry *ent; + + ent = debugfs_create_file("i915_cache_sharing", + S_IRUGO | S_IWUSR, + root, dev, + &i915_cache_sharing_fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + + return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops); +} + static struct drm_info_list i915_debugfs_list[] = { {"i915_capabilities", i915_capabilities, 0}, {"i915_gem_objects", i915_gem_object_info, 0}, @@ -1490,6 +1669,12 @@ int i915_debugfs_init(struct drm_minor *minor) ret = i915_forcewake_create(minor->debugfs_root, minor); if (ret) return ret; + ret = i915_max_freq_create(minor->debugfs_root, minor); + if (ret) + return ret; + ret = i915_cache_sharing_create(minor->debugfs_root, minor); + if (ret) + return ret; return drm_debugfs_create_files(i915_debugfs_list, I915_DEBUGFS_ENTRIES, @@ -1504,6 +1689,10 @@ void i915_debugfs_cleanup(struct drm_minor *minor) 1, minor); drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, 1, minor); + drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, + 1, minor); + drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, + 1, minor); } #endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 12712824a6d2..8a3942c4f099 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -61,7 +61,6 @@ static void i915_write_hws_pga(struct drm_device *dev) static int i915_init_phys_hws(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; - struct intel_ring_buffer *ring = LP_RING(dev_priv); /* Program Hardware Status Page */ dev_priv->status_page_dmah = @@ -71,10 +70,9 @@ static int i915_init_phys_hws(struct drm_device *dev) DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } - ring->status_page.page_addr = - (void __force __iomem *)dev_priv->status_page_dmah->vaddr; - memset_io(ring->status_page.page_addr, 0, PAGE_SIZE); + memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr, + 0, PAGE_SIZE); i915_write_hws_pga(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6867e193d85e..feb4f164fd1b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -544,6 +544,7 @@ typedef struct drm_i915_private { u32 savePIPEB_LINK_M1; u32 savePIPEB_LINK_N1; u32 saveMCHBAR_RENDER_STANDBY; + u32 savePCH_PORT_HOTPLUG; struct { /** Bridge to intel-gtt-ko */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d1cd8b89f47d..a546a71fb060 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3112,7 +3112,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, if (pipelined != obj->ring) { ret = i915_gem_object_wait_rendering(obj); - if (ret) + if (ret == -ERESTARTSYS) return ret; } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 23d1ae67d279..02f96fd0d52d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -306,12 +306,15 @@ static void i915_hotplug_work_func(struct work_struct *work) struct drm_mode_config *mode_config = &dev->mode_config; struct intel_encoder *encoder; + mutex_lock(&mode_config->mutex); DRM_DEBUG_KMS("running encoder hotplug functions\n"); list_for_each_entry(encoder, &mode_config->encoder_list, base.head) if (encoder->hot_plug) encoder->hot_plug(encoder); + mutex_unlock(&mode_config->mutex); + /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 02db299f621a..d1331f771e2f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -78,6 +78,14 @@ #define GRDOM_RENDER (1<<2) #define GRDOM_MEDIA (3<<2) +#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ +#define GEN6_MBC_SNPCR_SHIFT 21 +#define GEN6_MBC_SNPCR_MASK (3<<21) +#define GEN6_MBC_SNPCR_MAX (0<<21) +#define GEN6_MBC_SNPCR_MED (1<<21) +#define GEN6_MBC_SNPCR_LOW (2<<21) +#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ + #define GEN6_GDRST 0x941c #define GEN6_GRDOM_FULL (1 << 0) #define GEN6_GRDOM_RENDER (1 << 1) @@ -1506,6 +1514,7 @@ #define VIDEO_DIP_SELECT_AVI (0 << 19) #define VIDEO_DIP_SELECT_VENDOR (1 << 19) #define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) #define VIDEO_DIP_FREQ_ONCE (0 << 16) #define VIDEO_DIP_FREQ_VSYNC (1 << 16) #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) @@ -2084,9 +2093,6 @@ #define DP_PIPEB_SELECT (1 << 30) #define DP_PIPE_MASK (1 << 30) -#define DP_PIPE_ENABLED(V, P) \ - (((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN)) - /* Link training mode - select a suitable mode for each stage */ #define DP_LINK_TRAIN_PAT_1 (0 << 28) #define DP_LINK_TRAIN_PAT_2 (1 << 28) @@ -3024,6 +3030,20 @@ #define _TRANSA_DP_LINK_M2 0xe0048 #define _TRANSA_DP_LINK_N2 0xe004c +/* Per-transcoder DIP controls */ + +#define _VIDEO_DIP_CTL_A 0xe0200 +#define _VIDEO_DIP_DATA_A 0xe0208 +#define _VIDEO_DIP_GCP_A 0xe0210 + +#define _VIDEO_DIP_CTL_B 0xe1200 +#define _VIDEO_DIP_DATA_B 0xe1208 +#define _VIDEO_DIP_GCP_B 0xe1210 + +#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) +#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) +#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) + #define _TRANS_HTOTAL_B 0xe1000 #define _TRANS_HBLANK_B 0xe1004 #define _TRANS_HSYNC_B 0xe1008 @@ -3076,6 +3096,16 @@ #define TRANS_6BPC (2<<5) #define TRANS_12BPC (3<<5) +#define _TRANSA_CHICKEN2 0xf0064 +#define _TRANSB_CHICKEN2 0xf1064 +#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) + +#define SOUTH_CHICKEN1 0xc2000 +#define FDIA_PHASE_SYNC_SHIFT_OVR 19 +#define FDIA_PHASE_SYNC_SHIFT_EN 18 +#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) +#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 285758603ac8..87677d60d0df 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -812,6 +812,7 @@ int i915_save_state(struct drm_device *dev) dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR); dev_priv->saveMCHBAR_RENDER_STANDBY = I915_READ(RSTDBYCTL); + dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG); } else { dev_priv->saveIER = I915_READ(IER); dev_priv->saveIMR = I915_READ(IMR); @@ -863,6 +864,7 @@ int i915_restore_state(struct drm_device *dev) I915_WRITE(GTIMR, dev_priv->saveGTIMR); I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); + I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG); } else { I915_WRITE(IER, dev_priv->saveIER); I915_WRITE(IMR, dev_priv->saveIMR); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 393a39922e53..35364e68a091 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -980,11 +980,29 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, pipe_name(pipe)); } +static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe, + int reg, u32 port_sel, u32 val) +{ + if ((val & DP_PORT_EN) == 0) + return false; + + if (HAS_PCH_CPT(dev_priv->dev)) { + u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); + u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); + if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) + return false; + } else { + if ((val & DP_PIPE_MASK) != (pipe << 30)) + return false; + } + return true; +} + static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, - enum pipe pipe, int reg) + enum pipe pipe, int reg, u32 port_sel) { u32 val = I915_READ(reg); - WARN(DP_PIPE_ENABLED(val, pipe), + WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val), "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", reg, pipe_name(pipe)); } @@ -1004,9 +1022,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, int reg; u32 val; - assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B); - assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C); - assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D); + assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); + assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); + assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); reg = PCH_ADPA; val = I915_READ(reg); @@ -1276,6 +1294,17 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, intel_wait_for_pipe_off(dev_priv->dev, pipe); } +/* + * Plane regs are double buffered, going from enabled->disabled needs a + * trigger in order to latch. The display address reg provides this. + */ +static void intel_flush_display_plane(struct drm_i915_private *dev_priv, + enum plane plane) +{ + I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); + I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); +} + /** * intel_enable_plane - enable a display plane on a given pipe * @dev_priv: i915 private structure @@ -1299,20 +1328,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, return; I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); + intel_flush_display_plane(dev_priv, plane); intel_wait_for_vblank(dev_priv->dev, pipe); } -/* - * Plane regs are double buffered, going from enabled->disabled needs a - * trigger in order to latch. The display address reg provides this. - */ -static void intel_flush_display_plane(struct drm_i915_private *dev_priv, - enum plane plane) -{ - u32 reg = DSPADDR(plane); - I915_WRITE(reg, I915_READ(reg)); -} - /** * intel_disable_plane - disable a display plane * @dev_priv: i915 private structure @@ -1338,19 +1357,24 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv, } static void disable_pch_dp(struct drm_i915_private *dev_priv, - enum pipe pipe, int reg) + enum pipe pipe, int reg, u32 port_sel) { u32 val = I915_READ(reg); - if (DP_PIPE_ENABLED(val, pipe)) + if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) { + DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); I915_WRITE(reg, val & ~DP_PORT_EN); + } } static void disable_pch_hdmi(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) { u32 val = I915_READ(reg); - if (HDMI_PIPE_ENABLED(val, pipe)) + if (HDMI_PIPE_ENABLED(val, pipe)) { + DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", + reg, pipe); I915_WRITE(reg, val & ~PORT_ENABLE); + } } /* Disable any ports connected to this transcoder */ @@ -1362,9 +1386,9 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, val = I915_READ(PCH_PP_CONTROL); I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); - disable_pch_dp(dev_priv, pipe, PCH_DP_B); - disable_pch_dp(dev_priv, pipe, PCH_DP_C); - disable_pch_dp(dev_priv, pipe, PCH_DP_D); + disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); + disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); + disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); reg = PCH_ADPA; val = I915_READ(reg); @@ -2096,7 +2120,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, /* no fb bound */ if (!crtc->fb) { - DRM_DEBUG_KMS("No FB bound\n"); + DRM_ERROR("No FB bound\n"); return 0; } @@ -2105,6 +2129,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, case 1: break; default: + DRM_ERROR("no plane for crtc\n"); return -EINVAL; } @@ -2114,6 +2139,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, NULL); if (ret != 0) { mutex_unlock(&dev->struct_mutex); + DRM_ERROR("pin & fence failed\n"); return ret; } @@ -2142,6 +2168,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, if (ret) { i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); mutex_unlock(&dev->struct_mutex); + DRM_ERROR("failed to update base address\n"); return ret; } @@ -2248,6 +2275,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) FDI_FE_ERRC_ENABLE); } +static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 flags = I915_READ(SOUTH_CHICKEN1); + + flags |= FDI_PHASE_SYNC_OVR(pipe); + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ + flags |= FDI_PHASE_SYNC_EN(pipe); + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ + POSTING_READ(SOUTH_CHICKEN1); +} + /* The FDI link training functions for ILK/Ibexpeak. */ static void ironlake_fdi_link_train(struct drm_crtc *crtc) { @@ -2398,6 +2437,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) POSTING_READ(reg); udelay(150); + if (HAS_PCH_CPT(dev)) + cpt_phase_pointer_enable(dev, pipe); + for (i = 0; i < 4; i++ ) { reg = FDI_TX_CTL(pipe); temp = I915_READ(reg); @@ -2514,6 +2556,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) POSTING_READ(reg); udelay(150); + if (HAS_PCH_CPT(dev)) + cpt_phase_pointer_enable(dev, pipe); + for (i = 0; i < 4; i++ ) { reg = FDI_TX_CTL(pipe); temp = I915_READ(reg); @@ -2623,6 +2668,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) } } +static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 flags = I915_READ(SOUTH_CHICKEN1); + + flags &= ~(FDI_PHASE_SYNC_EN(pipe)); + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ + flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ + POSTING_READ(SOUTH_CHICKEN1); +} static void ironlake_fdi_disable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -2652,6 +2708,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) I915_WRITE(FDI_RX_CHICKEN(pipe), I915_READ(FDI_RX_CHICKEN(pipe) & ~FDI_RX_PHASE_SYNC_POINTER_EN)); + } else if (HAS_PCH_CPT(dev)) { + cpt_phase_pointer_disable(dev, pipe); } /* still set train pattern 1 */ @@ -2862,14 +2920,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); } + /* + * On ILK+ LUT must be loaded before the pipe is running but with + * clocks enabled + */ + intel_crtc_load_lut(crtc); + intel_enable_pipe(dev_priv, pipe, is_pch_port); intel_enable_plane(dev_priv, plane, pipe); if (is_pch_port) ironlake_pch_enable(crtc); - intel_crtc_load_lut(crtc); - mutex_lock(&dev->struct_mutex); intel_update_fbc(dev); mutex_unlock(&dev->struct_mutex); @@ -4538,7 +4600,9 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, if (connector->encoder != encoder) continue; - if (connector->display_info.bpc < display_bpc) { + /* Don't use an invalid EDID bpc value */ + if (connector->display_info.bpc && + connector->display_info.bpc < display_bpc) { DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); display_bpc = connector->display_info.bpc; } @@ -5153,7 +5217,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, temp |= PIPE_12BPC; break; default: - WARN(1, "intel_choose_pipe_bpp returned invalid value\n"); + WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", + pipe_bpp); temp |= PIPE_8BPC; pipe_bpp = 24; break; @@ -5238,7 +5303,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } else if (is_sdvo && is_tv) factor = 20; - if (clock.m1 < factor * clock.n) + if (clock.m < factor * clock.n) fp |= FP_CB_TUNE; dpll = 0; @@ -5516,6 +5581,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, drm_vblank_post_modeset(dev, pipe); + intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; + return ret; } @@ -7714,10 +7781,12 @@ static void gen6_init_clock_gating(struct drm_device *dev) ILK_DPARB_CLK_GATE | ILK_DPFD_CLK_GATE); - for_each_pipe(pipe) + for_each_pipe(pipe) { I915_WRITE(DSPCNTR(pipe), I915_READ(DSPCNTR(pipe)) | DISPPLANE_TRICKLE_FEED_DISABLE); + intel_flush_display_plane(dev_priv, pipe); + } } static void ivybridge_init_clock_gating(struct drm_device *dev) @@ -7734,10 +7803,12 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); - for_each_pipe(pipe) + for_each_pipe(pipe) { I915_WRITE(DSPCNTR(pipe), I915_READ(DSPCNTR(pipe)) | DISPPLANE_TRICKLE_FEED_DISABLE); + intel_flush_display_plane(dev_priv, pipe); + } } static void g4x_init_clock_gating(struct drm_device *dev) @@ -7820,6 +7891,7 @@ static void ibx_init_clock_gating(struct drm_device *dev) static void cpt_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + int pipe; /* * On Ibex Peak and Cougar Point, we need to disable clock @@ -7829,6 +7901,9 @@ static void cpt_init_clock_gating(struct drm_device *dev) I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | DPLS_EDP_PPS_FIX_DIS); + /* Without this, mode sets may fail silently on FDI */ + for_each_pipe(pipe) + I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); } static void ironlake_teardown_rc6(struct drm_device *dev) @@ -8178,6 +8253,9 @@ struct intel_quirk intel_quirks[] = { /* Lenovo U160 cannot use SSC on LVDS */ { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, + + /* Sony Vaio Y cannot use SSC on LVDS */ + { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, }; static void intel_init_quirks(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f797fb58ba9c..0feae908bb37 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -50,9 +50,10 @@ struct intel_dp { bool has_audio; int force_audio; uint32_t color_range; + int dpms_mode; uint8_t link_bw; uint8_t lane_count; - uint8_t dpcd[4]; + uint8_t dpcd[8]; struct i2c_adapter adapter; struct i2c_algo_dp_aux_data algo; bool is_pch_edp; @@ -316,9 +317,17 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, else precharge = 5; - if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { - DRM_ERROR("dp_aux_ch not started status 0x%08x\n", - I915_READ(ch_ctl)); + /* Try to wait for any previous AUX channel activity */ + for (try = 0; try < 3; try++) { + status = I915_READ(ch_ctl); + if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) + break; + msleep(1); + } + + if (try == 3) { + WARN(1, "dp_aux_ch not started status 0x%08x\n", + I915_READ(ch_ctl)); return -EBUSY; } @@ -770,6 +779,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); intel_dp->link_configuration[0] = intel_dp->link_bw; intel_dp->link_configuration[1] = intel_dp->lane_count; + intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; /* * Check for DPCD version > 1.1 and enhanced framing support @@ -1011,6 +1021,8 @@ static void intel_dp_commit(struct drm_encoder *encoder) if (is_edp(intel_dp)) ironlake_edp_backlight_on(dev); + + intel_dp->dpms_mode = DRM_MODE_DPMS_ON; } static void @@ -1045,6 +1057,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode) if (is_edp(intel_dp)) ironlake_edp_backlight_on(dev); } + intel_dp->dpms_mode = mode; } /* @@ -1334,10 +1347,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) u32 reg; uint32_t DP = intel_dp->DP; - /* Enable output, wait for it to become active */ - I915_WRITE(intel_dp->output_reg, intel_dp->DP); - POSTING_READ(intel_dp->output_reg); - intel_wait_for_vblank(dev, intel_crtc->pipe); + /* + * On CPT we have to enable the port in training pattern 1, which + * will happen below in intel_dp_set_link_train. Otherwise, enable + * the port and wait for it to become active. + */ + if (!HAS_PCH_CPT(dev)) { + I915_WRITE(intel_dp->output_reg, intel_dp->DP); + POSTING_READ(intel_dp->output_reg); + intel_wait_for_vblank(dev, intel_crtc->pipe); + } /* Write the link configuration data */ intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, @@ -1370,7 +1389,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) reg = DP | DP_LINK_TRAIN_PAT_1; if (!intel_dp_set_link_train(intel_dp, reg, - DP_TRAINING_PATTERN_1)) + DP_TRAINING_PATTERN_1 | + DP_LINK_SCRAMBLING_DISABLE)) break; /* Set training pattern 1 */ @@ -1445,7 +1465,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* channel eq pattern */ if (!intel_dp_set_link_train(intel_dp, reg, - DP_TRAINING_PATTERN_2)) + DP_TRAINING_PATTERN_2 | + DP_LINK_SCRAMBLING_DISABLE)) break; udelay(400); @@ -1559,6 +1580,18 @@ intel_dp_link_down(struct intel_dp *intel_dp) POSTING_READ(intel_dp->output_reg); } +static bool +intel_dp_get_dpcd(struct intel_dp *intel_dp) +{ + if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, + sizeof (intel_dp->dpcd)) && + (intel_dp->dpcd[DP_DPCD_REV] != 0)) { + return true; + } + + return false; +} + /* * According to DP spec * 5.1.2: @@ -1571,36 +1604,44 @@ intel_dp_link_down(struct intel_dp *intel_dp) static void intel_dp_check_link_status(struct intel_dp *intel_dp) { - int ret; + if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) + return; if (!intel_dp->base.base.crtc) return; + /* Try to read receiver status if the link appears to be up */ if (!intel_dp_get_link_status(intel_dp)) { intel_dp_link_down(intel_dp); return; } - /* Try to read receiver status if the link appears to be up */ - ret = intel_dp_aux_native_read(intel_dp, - 0x000, intel_dp->dpcd, - sizeof (intel_dp->dpcd)); - if (ret != sizeof(intel_dp->dpcd)) { + /* Now read the DPCD to see if it's actually running */ + if (!intel_dp_get_dpcd(intel_dp)) { intel_dp_link_down(intel_dp); return; } if (!intel_channel_eq_ok(intel_dp)) { + DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", + drm_get_encoder_name(&intel_dp->base.base)); intel_dp_start_link_train(intel_dp); intel_dp_complete_link_train(intel_dp); } } static enum drm_connector_status +intel_dp_detect_dpcd(struct intel_dp *intel_dp) +{ + if (intel_dp_get_dpcd(intel_dp)) + return connector_status_connected; + return connector_status_disconnected; +} + +static enum drm_connector_status ironlake_dp_detect(struct intel_dp *intel_dp) { enum drm_connector_status status; - bool ret; /* Can't disconnect eDP, but you can close the lid... */ if (is_edp(intel_dp)) { @@ -1610,15 +1651,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp) return status; } - status = connector_status_disconnected; - ret = intel_dp_aux_native_read_retry(intel_dp, - 0x000, intel_dp->dpcd, - sizeof (intel_dp->dpcd)); - if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0) - status = connector_status_connected; - DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], - intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); - return status; + return intel_dp_detect_dpcd(intel_dp); } static enum drm_connector_status @@ -1626,7 +1659,6 @@ g4x_dp_detect(struct intel_dp *intel_dp) { struct drm_device *dev = intel_dp->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - enum drm_connector_status status; uint32_t temp, bit; switch (intel_dp->output_reg) { @@ -1648,15 +1680,7 @@ g4x_dp_detect(struct intel_dp *intel_dp) if ((temp & bit) == 0) return connector_status_disconnected; - status = connector_status_disconnected; - if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, - sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) - { - if (intel_dp->dpcd[DP_DPCD_REV] != 0) - status = connector_status_connected; - } - - return status; + return intel_dp_detect_dpcd(intel_dp); } /** @@ -1679,6 +1703,12 @@ intel_dp_detect(struct drm_connector *connector, bool force) status = ironlake_dp_detect(intel_dp); else status = g4x_dp_detect(intel_dp); + + DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", + intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], + intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], + intel_dp->dpcd[6], intel_dp->dpcd[7]); + if (status != connector_status_connected) return status; @@ -1924,6 +1954,7 @@ intel_dp_init(struct drm_device *dev, int output_reg) return; intel_dp->output_reg = output_reg; + intel_dp->dpms_mode = -1; intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); if (!intel_connector) { @@ -2000,7 +2031,7 @@ intel_dp_init(struct drm_device *dev, int output_reg) /* Cache some DPCD data in the eDP case */ if (is_edp(intel_dp)) { - int ret; + bool ret; u32 pp_on, pp_div; pp_on = I915_READ(PCH_PP_ON_DELAYS); @@ -2013,11 +2044,9 @@ intel_dp_init(struct drm_device *dev, int output_reg) dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ ironlake_edp_panel_vdd_on(intel_dp); - ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, - intel_dp->dpcd, - sizeof(intel_dp->dpcd)); + ret = intel_dp_get_dpcd(intel_dp); ironlake_edp_panel_vdd_off(intel_dp); - if (ret == sizeof(intel_dp->dpcd)) { + if (ret) { if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6e990f9760ef..7b330e76a435 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -178,10 +178,28 @@ struct intel_crtc { #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) +#define DIP_HEADER_SIZE 5 + #define DIP_TYPE_AVI 0x82 #define DIP_VERSION_AVI 0x2 #define DIP_LEN_AVI 13 +#define DIP_TYPE_SPD 0x3 +#define DIP_VERSION_SPD 0x1 +#define DIP_LEN_SPD 25 +#define DIP_SPD_UNKNOWN 0 +#define DIP_SPD_DSTB 0x1 +#define DIP_SPD_DVDP 0x2 +#define DIP_SPD_DVHS 0x3 +#define DIP_SPD_HDDVR 0x4 +#define DIP_SPD_DVC 0x5 +#define DIP_SPD_DSC 0x6 +#define DIP_SPD_VCD 0x7 +#define DIP_SPD_GAME 0x8 +#define DIP_SPD_PC 0x9 +#define DIP_SPD_BD 0xa +#define DIP_SPD_SCD 0xb + struct dip_infoframe { uint8_t type; /* HB0 */ uint8_t ver; /* HB1 */ @@ -206,6 +224,11 @@ struct dip_infoframe { uint16_t left_bar_end; uint16_t right_bar_start; } avi; + struct { + uint8_t vn[8]; + uint8_t pd[16]; + uint8_t sdi; + } spd; uint8_t payload[27]; } __attribute__ ((packed)) body; } __attribute__((packed)); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 1ed8e6903915..226ba830f383 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -45,6 +45,8 @@ struct intel_hdmi { bool has_hdmi_sink; bool has_audio; int force_audio; + void (*write_infoframe)(struct drm_encoder *encoder, + struct dip_infoframe *frame); }; static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) @@ -58,37 +60,70 @@ static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) struct intel_hdmi, base); } -void intel_dip_infoframe_csum(struct dip_infoframe *avi_if) +void intel_dip_infoframe_csum(struct dip_infoframe *frame) { - uint8_t *data = (uint8_t *)avi_if; + uint8_t *data = (uint8_t *)frame; uint8_t sum = 0; unsigned i; - avi_if->checksum = 0; - avi_if->ecc = 0; + frame->checksum = 0; + frame->ecc = 0; - for (i = 0; i < sizeof(*avi_if); i++) + /* Header isn't part of the checksum */ + for (i = 5; i < frame->len; i++) sum += data[i]; - avi_if->checksum = 0x100 - sum; + frame->checksum = 0x100 - sum; } -static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) +static u32 intel_infoframe_index(struct dip_infoframe *frame) { - struct dip_infoframe avi_if = { - .type = DIP_TYPE_AVI, - .ver = DIP_VERSION_AVI, - .len = DIP_LEN_AVI, - }; - uint32_t *data = (uint32_t *)&avi_if; + u32 flags = 0; + + switch (frame->type) { + case DIP_TYPE_AVI: + flags |= VIDEO_DIP_SELECT_AVI; + break; + case DIP_TYPE_SPD: + flags |= VIDEO_DIP_SELECT_SPD; + break; + default: + DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); + break; + } + + return flags; +} + +static u32 intel_infoframe_flags(struct dip_infoframe *frame) +{ + u32 flags = 0; + + switch (frame->type) { + case DIP_TYPE_AVI: + flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; + break; + case DIP_TYPE_SPD: + flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC; + break; + default: + DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); + break; + } + + return flags; +} + +static void i9xx_write_infoframe(struct drm_encoder *encoder, + struct dip_infoframe *frame) +{ + uint32_t *data = (uint32_t *)frame; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - u32 port; - unsigned i; + u32 port, flags, val = I915_READ(VIDEO_DIP_CTL); + unsigned i, len = DIP_HEADER_SIZE + frame->len; - if (!intel_hdmi->has_hdmi_sink) - return; /* XXX first guess at handling video port, is this corrent? */ if (intel_hdmi->sdvox_reg == SDVOB) @@ -98,18 +133,87 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) else return; - I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port | - VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC); + flags = intel_infoframe_index(frame); + + val &= ~VIDEO_DIP_SELECT_MASK; - intel_dip_infoframe_csum(&avi_if); - for (i = 0; i < sizeof(avi_if); i += 4) { + I915_WRITE(VIDEO_DIP_CTL, val | port | flags); + + for (i = 0; i < len; i += 4) { I915_WRITE(VIDEO_DIP_DATA, *data); data++; } - I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port | - VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC | - VIDEO_DIP_ENABLE_AVI); + flags |= intel_infoframe_flags(frame); + + I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); +} + +static void ironlake_write_infoframe(struct drm_encoder *encoder, + struct dip_infoframe *frame) +{ + uint32_t *data = (uint32_t *)frame; + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *crtc = encoder->crtc; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); + unsigned i, len = DIP_HEADER_SIZE + frame->len; + u32 flags, val = I915_READ(reg); + + intel_wait_for_vblank(dev, intel_crtc->pipe); + + flags = intel_infoframe_index(frame); + + val &= ~VIDEO_DIP_SELECT_MASK; + + I915_WRITE(reg, val | flags); + + for (i = 0; i < len; i += 4) { + I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + data++; + } + + flags |= intel_infoframe_flags(frame); + + I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); +} +static void intel_set_infoframe(struct drm_encoder *encoder, + struct dip_infoframe *frame) +{ + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); + + if (!intel_hdmi->has_hdmi_sink) + return; + + intel_dip_infoframe_csum(frame); + intel_hdmi->write_infoframe(encoder, frame); +} + +static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) +{ + struct dip_infoframe avi_if = { + .type = DIP_TYPE_AVI, + .ver = DIP_VERSION_AVI, + .len = DIP_LEN_AVI, + }; + + intel_set_infoframe(encoder, &avi_if); +} + +static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) +{ + struct dip_infoframe spd_if; + + memset(&spd_if, 0, sizeof(spd_if)); + spd_if.type = DIP_TYPE_SPD; + spd_if.ver = DIP_VERSION_SPD; + spd_if.len = DIP_LEN_SPD; + strcpy(spd_if.body.spd.vn, "Intel"); + strcpy(spd_if.body.spd.pd, "Integrated gfx"); + spd_if.body.spd.sdi = DIP_SPD_PC; + + intel_set_infoframe(encoder, &spd_if); } static void intel_hdmi_mode_set(struct drm_encoder *encoder, @@ -156,6 +260,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder, POSTING_READ(intel_hdmi->sdvox_reg); intel_hdmi_set_avi_infoframe(encoder); + intel_hdmi_set_spd_infoframe(encoder); } static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) @@ -433,6 +538,11 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) intel_hdmi->sdvox_reg = sdvox_reg; + if (!HAS_PCH_SPLIT(dev)) + intel_hdmi->write_infoframe = i9xx_write_infoframe; + else + intel_hdmi->write_infoframe = ironlake_write_infoframe; + drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); intel_hdmi_add_properties(intel_hdmi, connector); diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index b28f7bd9f88a..2e8ddfcba40c 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -690,6 +690,14 @@ static const struct dmi_system_id intel_no_lvds[] = { }, { .callback = intel_no_lvds_dmi_callback, + .ident = "Dell OptiPlex FX170", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), + }, + }, + { + .callback = intel_no_lvds_dmi_callback, .ident = "AOpen Mini PC", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index a06ff07a4d3b..05f500cd9c24 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev, u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; if (scaled_width > scaled_height) { /* pillar */ width = scaled_height / mode->vdisplay; + if (width & 1) + width++; x = (adjusted_mode->hdisplay - width + 1) / 2; y = 0; height = adjusted_mode->vdisplay; } else if (scaled_width < scaled_height) { /* letter */ height = scaled_width / mode->hdisplay; + if (height & 1) + height++; y = (adjusted_mode->vdisplay - height + 1) / 2; x = 0; width = adjusted_mode->hdisplay; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e9615685a39c..47b9b2777038 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1321,6 +1321,9 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) ring->get_seqno = pc_render_get_seqno; } + if (!I915_NEED_GFX_HWS(dev)) + ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; + ring->dev = dev; INIT_LIST_HEAD(&ring->active_list); INIT_LIST_HEAD(&ring->request_list); diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 3896ef811102..9f363e0c4b60 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -5,6 +5,7 @@ ccflags-y := -Iinclude/drm hostprogs-y := mkregtable +clean-files := rn50_reg_safe.h r100_reg_safe.h r200_reg_safe.h rv515_reg_safe.h r300_reg_safe.h r420_reg_safe.h rs600_reg_safe.h r600_reg_safe.h evergreen_reg_safe.h cayman_reg_safe.h quiet_cmd_mkregtable = MKREGTABLE $@ cmd_mkregtable = $(obj)/mkregtable $< > $@ diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index ebdb0fdb8348..e88c64417a8a 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c @@ -1245,6 +1245,9 @@ struct atom_context *atom_parse(struct card_info *card, void *bios) char name[512]; int i; + if (!ctx) + return NULL; + ctx->card = card; ctx->bios = bios; diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c index 189e86522b5b..a134790903d3 100644 --- a/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/drivers/gpu/drm/radeon/evergreen_cs.c @@ -428,7 +428,7 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); i = (reg >> 7); - if (i > last_reg) { + if (i >= last_reg) { dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; } diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index db8ef1905d5f..cf83aa05a684 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -915,12 +915,11 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx { struct r600_cs_track *track = (struct r600_cs_track *)p->track; struct radeon_cs_reloc *reloc; - u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm); u32 m, i, tmp, *ib; int r; i = (reg >> 7); - if (i > last_reg) { + if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; } diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index a74217cd192f..e0138b674aca 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2557,6 +2557,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) u16 offset, misc, misc2 = 0; u8 rev, blocks, tmp; int state_index = 0; + struct radeon_i2c_bus_rec i2c_bus; rdev->pm.default_power_state_index = -1; @@ -2575,7 +2576,6 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); if (offset) { u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; - struct radeon_i2c_bus_rec i2c_bus; rev = RBIOS8(offset); @@ -2617,6 +2617,25 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); } } + } else { + /* boards with a thermal chip, but no overdrive table */ + + /* Asus 9600xt has an f75375 on the monid bus */ + if ((dev->pdev->device == 0x4152) && + (dev->pdev->subsystem_vendor == 0x1043) && + (dev->pdev->subsystem_device == 0xc002)) { + i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); + rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); + if (rdev->pm.i2c_bus) { + struct i2c_board_info info = { }; + const char *name = "f75375"; + info.addr = 0x28; + strlcpy(info.type, name, sizeof(info.type)); + i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); + DRM_INFO("Possible %s thermal controller at 0x%02x\n", + name, info.addr); + } + } } if (rdev->flags & RADEON_IS_MOBILITY) { diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 9792d4ffdc86..6d6b5f16bc09 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -430,6 +430,45 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr return 0; } +/* + * Some integrated ATI Radeon chipset implementations (e. g. + * Asus M2A-VM HDMI) may indicate the availability of a DDC, + * even when there's no monitor connected. For these connectors + * following DDC probe extension will be applied: check also for the + * availability of EDID with at least a correct EDID header. Only then, + * DDC is assumed to be available. This prevents drm_get_edid() and + * drm_edid_block_valid() from periodically dumping data and kernel + * errors into the logs and onto the terminal. + */ +static bool radeon_connector_needs_extended_probe(struct radeon_device *dev, + uint32_t supported_device, + int connector_type) +{ + /* Asus M2A-VM HDMI board sends data to i2c bus even, + * if HDMI add-on card is not plugged in or HDMI is disabled in + * BIOS. Valid DDC can only be assumed, if also a valid EDID header + * can be retrieved via i2c bus during DDC probe */ + if ((dev->pdev->device == 0x791e) && + (dev->pdev->subsystem_vendor == 0x1043) && + (dev->pdev->subsystem_device == 0x826d)) { + if ((connector_type == DRM_MODE_CONNECTOR_HDMIA) && + (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) + return true; + } + /* ECS A740GM-M with ATI RADEON 2100 sends data to i2c bus + * for a DVI connector that is not implemented */ + if ((dev->pdev->device == 0x796e) && + (dev->pdev->subsystem_vendor == 0x1019) && + (dev->pdev->subsystem_device == 0x2615)) { + if ((connector_type == DRM_MODE_CONNECTOR_DVID) && + (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) + return true; + } + + /* Default: no EDID header probe required for DDC probing */ + return false; +} + static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, struct drm_connector *connector) { @@ -661,7 +700,8 @@ radeon_vga_detect(struct drm_connector *connector, bool force) ret = connector_status_disconnected; if (radeon_connector->ddc_bus) - dret = radeon_ddc_probe(radeon_connector); + dret = radeon_ddc_probe(radeon_connector, + radeon_connector->requires_extended_probe); if (dret) { if (radeon_connector->edid) { kfree(radeon_connector->edid); @@ -833,7 +873,8 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) bool dret = false; if (radeon_connector->ddc_bus) - dret = radeon_ddc_probe(radeon_connector); + dret = radeon_ddc_probe(radeon_connector, + radeon_connector->requires_extended_probe); if (dret) { if (radeon_connector->edid) { kfree(radeon_connector->edid); @@ -1251,7 +1292,8 @@ radeon_dp_detect(struct drm_connector *connector, bool force) if (radeon_dp_getdpcd(radeon_connector)) ret = connector_status_connected; } else { - if (radeon_ddc_probe(radeon_connector)) + if (radeon_ddc_probe(radeon_connector, + radeon_connector->requires_extended_probe)) ret = connector_status_connected; } } @@ -1406,6 +1448,9 @@ radeon_add_atom_connector(struct drm_device *dev, radeon_connector->shared_ddc = shared_ddc; radeon_connector->connector_object_id = connector_object_id; radeon_connector->hpd = *hpd; + radeon_connector->requires_extended_probe = + radeon_connector_needs_extended_probe(rdev, supported_device, + connector_type); radeon_connector->router = *router; if (router->ddc_valid || router->cd_valid) { radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info); @@ -1752,6 +1797,9 @@ radeon_add_legacy_connector(struct drm_device *dev, radeon_connector->devices = supported_device; radeon_connector->connector_object_id = connector_object_id; radeon_connector->hpd = *hpd; + radeon_connector->requires_extended_probe = + radeon_connector_needs_extended_probe(rdev, supported_device, + connector_type); switch (connector_type) { case DRM_MODE_CONNECTOR_VGA: drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7cfaa7e2f3b5..440e6ecccc40 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -704,8 +704,9 @@ int radeon_device_init(struct radeon_device *rdev, rdev->gpu_lockup = false; rdev->accel_working = false; - DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", - radeon_family_name[rdev->family], pdev->vendor, pdev->device); + DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", + radeon_family_name[rdev->family], pdev->vendor, pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); /* mutex initialization are all done here so we * can recall function without having locking issues */ diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 28f4655905bc..1a858944e4f3 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -751,8 +751,17 @@ static int radeon_ddc_dump(struct drm_connector *connector) if (!radeon_connector->ddc_bus) return -1; edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); + /* Log EDID retrieval status here. In particular with regard to + * connectors with requires_extended_probe flag set, that will prevent + * function radeon_dvi_detect() to fetch EDID on this connector, + * as long as there is no valid EDID header found */ if (edid) { + DRM_INFO("Radeon display connector %s: Found valid EDID", + drm_get_connector_name(connector)); kfree(edid); + } else { + DRM_INFO("Radeon display connector %s: No monitor connected or invalid EDID", + drm_get_connector_name(connector)); } return ret; } diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 85f033f19a8a..e71d2ed7fa11 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -50,8 +50,8 @@ * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query - * 2.10.0 - fusion 2D tiling, initial compute support for the CS checker - * 2.11.0 - backend map + * 2.10.0 - fusion 2D tiling + * 2.11.0 - backend map, initial compute support for the CS checker */ #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 11 diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index 781196db792f..6c111c1fa3f9 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -32,17 +32,17 @@ * radeon_ddc_probe * */ -bool radeon_ddc_probe(struct radeon_connector *radeon_connector) +bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe) { - u8 out_buf[] = { 0x0, 0x0}; - u8 buf[2]; + u8 out = 0x0; + u8 buf[8]; int ret; struct i2c_msg msgs[] = { { .addr = 0x50, .flags = 0, .len = 1, - .buf = out_buf, + .buf = &out, }, { .addr = 0x50, @@ -52,15 +52,31 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector) } }; + /* Read 8 bytes from i2c for extended probe of EDID header */ + if (requires_extended_probe) + msgs[1].len = 8; + /* on hw with routers, select right port */ if (radeon_connector->router.ddc_valid) radeon_router_select_ddc_port(radeon_connector); ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); - if (ret == 2) - return true; - - return false; + if (ret != 2) + /* Couldn't find an accessible DDC on this connector */ + return false; + if (requires_extended_probe) { + /* Probe also for valid EDID header + * EDID header starts with: + * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. + * Only the first 6 bytes must be valid as + * drm_edid_block_valid() can fix the last 2 bytes */ + if (drm_edid_header_is_valid(buf) < 6) { + /* Couldn't find an accessible EDID on this + * connector */ + return false; + } + } + return true; } /* bit banging i2c */ diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 6df4e3cec0c2..d09031c03e26 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -438,6 +438,9 @@ struct radeon_connector { struct radeon_i2c_chan *ddc_bus; /* some systems have an hdmi and vga port with a shared ddc line */ bool shared_ddc; + /* for some Radeon chip families we apply an additional EDID header + check as part of the DDC probe */ + bool requires_extended_probe; bool use_digital; /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ @@ -514,7 +517,8 @@ extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, u8 val); extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); -extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); +extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, + bool requires_extended_probe); extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c index 3be60da52123..67cbcfa35122 100644 --- a/drivers/ide/cy82c693.c +++ b/drivers/ide/cy82c693.c @@ -141,6 +141,8 @@ static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16); pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8); } + if (hwif->index > 0) + pci_dev_put(dev); } static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) diff --git a/drivers/ide/ide_platform.c b/drivers/ide/ide_platform.c index 542603b394e4..962693b10a1c 100644 --- a/drivers/ide/ide_platform.c +++ b/drivers/ide/ide_platform.c @@ -19,6 +19,7 @@ #include <linux/module.h> #include <linux/ata_platform.h> #include <linux/platform_device.h> +#include <linux/interrupt.h> #include <linux/io.h> static void __devinit plat_ide_setup_ports(struct ide_hw *hw, @@ -95,7 +96,10 @@ static int __devinit plat_ide_probe(struct platform_device *pdev) plat_ide_setup_ports(&hw, base, alt_base, pdata, res_irq->start); hw.dev = &pdev->dev; - d.irq_flags = res_irq->flags; + d.irq_flags = res_irq->flags & IRQF_TRIGGER_MASK; + if (res_irq->flags & IORESOURCE_IRQ_SHAREABLE) + d.irq_flags |= IRQF_SHARED; + if (mmio) d.host_flags |= IDE_HFLAG_MMIO; diff --git a/drivers/net/bnx2x/bnx2x_cmn.c b/drivers/net/bnx2x/bnx2x_cmn.c index 5b0dba6d4efa..d724a18b5285 100644 --- a/drivers/net/bnx2x/bnx2x_cmn.c +++ b/drivers/net/bnx2x/bnx2x_cmn.c @@ -1989,14 +1989,20 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) return -EINVAL; } + /* + * It's important to set the bp->state to the value different from + * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int() + * may restart the Tx from the NAPI context (see bnx2x_tx_int()). + */ + bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; + smp_mb(); + /* Stop Tx */ bnx2x_tx_disable(bp); #ifdef BCM_CNIC bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); #endif - bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; - smp_mb(); bp->rx_mode = BNX2X_RX_MODE_NONE; diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h index 06727f32e505..dc24de40e336 100644 --- a/drivers/net/bnx2x/bnx2x_hsi.h +++ b/drivers/net/bnx2x/bnx2x_hsi.h @@ -1204,6 +1204,8 @@ struct drv_port_mb { #define LINK_STATUS_PFC_ENABLED 0x20000000 + #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 + u32 port_stx; u32 stat_nig_timer; diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c index bcd8f0038628..d45b1555a602 100644 --- a/drivers/net/bnx2x/bnx2x_link.c +++ b/drivers/net/bnx2x/bnx2x_link.c @@ -1546,6 +1546,12 @@ static void bnx2x_umac_enable(struct link_params *params, vars->line_speed); break; } + if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) + val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; + + if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) + val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; + REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); udelay(50); @@ -1661,10 +1667,20 @@ static void bnx2x_xmac_disable(struct link_params *params) { u8 port = params->port; struct bnx2x *bp = params->bp; - u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; if (REG_RD(bp, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) { + /* + * Send an indication to change the state in the NIG back to XON + * Clearing this bit enables the next set of this bit to get + * rising edge + */ + pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); + REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, + (pfc_ctrl & ~(1<<1))); + REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, + (pfc_ctrl | (1<<1))); DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0); usleep_range(1000, 1000); @@ -1729,6 +1745,10 @@ static int bnx2x_emac_enable(struct link_params *params, DP(NETIF_MSG_LINK, "enabling EMAC\n"); + /* Disable BMAC */ + REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + /* enable emac and not bmac */ REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); @@ -2583,12 +2603,6 @@ static int bnx2x_bmac1_enable(struct link_params *params, REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, wb_data, 2); - if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) { - REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS, - wb_data, 2); - if (wb_data[0] > 0) - return -ESRCH; - } return 0; } @@ -2654,16 +2668,6 @@ static int bnx2x_bmac2_enable(struct link_params *params, udelay(30); bnx2x_update_pfc_bmac2(params, vars, is_lb); - if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) { - REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT, - wb_data, 2); - if (wb_data[0] > 0) { - DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n", - wb_data[0]); - return -ESRCH; - } - } - return 0; } @@ -2949,7 +2953,9 @@ static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, u32 val; u16 i; int rc = 0; - + if (phy->flags & FLAGS_MDC_MDIO_WA_B0) + bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); /* address */ val = ((phy->addr << 21) | (devad << 16) | reg | EMAC_MDIO_COMM_COMMAND_ADDRESS | @@ -3003,6 +3009,9 @@ static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, } } + if (phy->flags & FLAGS_MDC_MDIO_WA_B0) + bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); return rc; } @@ -3012,6 +3021,9 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, u32 tmp; u8 i; int rc = 0; + if (phy->flags & FLAGS_MDC_MDIO_WA_B0) + bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); /* address */ @@ -3065,7 +3077,9 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); } } - + if (phy->flags & FLAGS_MDC_MDIO_WA_B0) + bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); return rc; } @@ -4353,6 +4367,9 @@ void bnx2x_link_status_update(struct link_params *params, vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); vars->phy_flags = PHY_XGXS_FLAG; + if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) + vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; + if (vars->link_up) { DP(NETIF_MSG_LINK, "phy link up\n"); @@ -4444,6 +4461,8 @@ void bnx2x_link_status_update(struct link_params *params, /* indicate no mac active */ vars->mac_type = MAC_TYPE_NONE; + if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) + vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; } /* Sync media type */ @@ -5903,20 +5922,30 @@ int bnx2x_set_led(struct link_params *params, tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); - return rc; + /* + * return here without enabling traffic + * LED blink andsetting rate in ON mode. + * In oper mode, enabling LED blink + * and setting rate is needed. + */ + if (mode == LED_MODE_ON) + return rc; } - } else if (SINGLE_MEDIA_DIRECT(params) && - (CHIP_IS_E1x(bp) || - CHIP_IS_E2(bp))) { + } else if (SINGLE_MEDIA_DIRECT(params)) { /* * This is a work-around for HW issue found when link * is up in CL73 */ - REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); - } else { + if (CHIP_IS_E1x(bp) || + CHIP_IS_E2(bp) || + (mode == LED_MODE_ON)) + REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); + else + REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, + hw_led_mode); + } else REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode); - } REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); /* Set blinking rate to ~15.9Hz */ @@ -6160,6 +6189,7 @@ static int bnx2x_update_link_down(struct link_params *params, /* update shared memory */ vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | LINK_STATUS_LINK_UP | + LINK_STATUS_PHYSICAL_LINK_FLAG | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | @@ -6197,7 +6227,8 @@ static int bnx2x_update_link_up(struct link_params *params, u8 port = params->port; int rc = 0; - vars->link_status |= LINK_STATUS_LINK_UP; + vars->link_status |= (LINK_STATUS_LINK_UP | + LINK_STATUS_PHYSICAL_LINK_FLAG); vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) @@ -7998,6 +8029,9 @@ static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); + /* Restart microcode to re-read the new mode */ + bnx2x_warpcore_reset_lane(bp, phy, 1); + bnx2x_warpcore_reset_lane(bp, phy, 0); } @@ -8116,7 +8150,6 @@ void bnx2x_handle_module_detect_int(struct link_params *params) offsetof(struct shmem_region, dev_info. port_feature_config[params->port]. config)); - bnx2x_set_gpio_int(bp, gpio_num, MISC_REGISTERS_GPIO_INT_OUTPUT_SET, gpio_port); @@ -8125,8 +8158,9 @@ void bnx2x_handle_module_detect_int(struct link_params *params) * Disable transmit for this module */ phy->media_type = ETH_PHY_NOT_PRESENT; - if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == - PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) + if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) || + CHIP_IS_E3(bp)) bnx2x_sfp_set_transmitter(params, phy, 0); } } @@ -8228,9 +8262,6 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, u16 cnt, val, tmp1; struct bnx2x *bp = params->bp; - /* SPF+ PHY: Set flag to check for Tx error */ - vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG; - bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); /* HW reset */ @@ -8414,9 +8445,6 @@ static int bnx2x_8726_config_init(struct bnx2x_phy *phy, struct bnx2x *bp = params->bp; DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); - /* SPF+ PHY: Set flag to check for Tx error */ - vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG; - bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); bnx2x_wait_reset_complete(bp, phy, params); @@ -8585,9 +8613,6 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy, struct bnx2x *bp = params->bp; /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ - /* SPF+ PHY: Set flag to check for Tx error */ - vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG; - bnx2x_wait_reset_complete(bp, phy, params); rx_alarm_ctrl_val = (1<<2) | (1<<5) ; /* Should be 0x6 to enable XS on Tx side. */ @@ -9243,7 +9268,13 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, if (phy->req_duplex == DUPLEX_FULL) autoneg_val |= (1<<8); - bnx2x_cl45_write(bp, phy, + /* + * Always write this if this is not 84833. + * For 84833, write it only when it's a forced speed. + */ + if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || + ((autoneg_val & (1<<12)) == 0)) + bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); @@ -9257,13 +9288,12 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200); - } else if (phy->req_line_speed != SPEED_10 && - phy->req_line_speed != SPEED_100) { + } else bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1); - } + /* Save spirom version */ bnx2x_save_848xx_spirom_version(phy, params); @@ -9756,11 +9786,9 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &val16); - /* Put to low power mode on newer FW */ - if ((val16 & 0x303f) > 0x1009) - bnx2x_cl45_write(bp, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, 0x800); + bnx2x_cl45_write(bp, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, 0x800); } } @@ -10191,8 +10219,15 @@ static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, u32 cfg_pin; u8 port; - /* This works with E3 only, no need to check the chip - before determining the port. */ + /* + * In case of no EPIO routed to reset the GPHY, put it + * in low power mode. + */ + bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); + /* + * This works with E3 only, no need to check the chip + * before determining the port. + */ port = params->port; cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, @@ -10603,7 +10638,8 @@ static struct bnx2x_phy phy_warpcore = { .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, .addr = 0xff, .def_md_devad = 0, - .flags = FLAGS_HW_LOCK_REQUIRED, + .flags = (FLAGS_HW_LOCK_REQUIRED | + FLAGS_TX_ERROR_CHECK), .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .mdio_ctrl = 0, @@ -10729,7 +10765,8 @@ static struct bnx2x_phy phy_8706 = { .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, .addr = 0xff, .def_md_devad = 0, - .flags = FLAGS_INIT_XGXS_FIRST, + .flags = (FLAGS_INIT_XGXS_FIRST | + FLAGS_TX_ERROR_CHECK), .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .mdio_ctrl = 0, @@ -10760,7 +10797,8 @@ static struct bnx2x_phy phy_8726 = { .addr = 0xff, .def_md_devad = 0, .flags = (FLAGS_HW_LOCK_REQUIRED | - FLAGS_INIT_XGXS_FIRST), + FLAGS_INIT_XGXS_FIRST | + FLAGS_TX_ERROR_CHECK), .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .mdio_ctrl = 0, @@ -10791,7 +10829,8 @@ static struct bnx2x_phy phy_8727 = { .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, .addr = 0xff, .def_md_devad = 0, - .flags = FLAGS_FAN_FAILURE_DET_REQ, + .flags = (FLAGS_FAN_FAILURE_DET_REQ | + FLAGS_TX_ERROR_CHECK), .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .mdio_ctrl = 0, @@ -11112,6 +11151,8 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, */ if (CHIP_REV(bp) == CHIP_REV_Ax) phy->flags |= FLAGS_MDC_MDIO_WA; + else + phy->flags |= FLAGS_MDC_MDIO_WA_B0; } else { switch (switch_cfg) { case SWITCH_CFG_1G: @@ -11500,13 +11541,12 @@ void bnx2x_init_xmac_loopback(struct link_params *params, * Set WC to loopback mode since link is required to provide clock * to the XMAC in 20G mode */ - if (vars->line_speed == SPEED_20000) { - bnx2x_set_aer_mmd(params, ¶ms->phy[0]); - bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); - params->phy[INT_PHY].config_loopback( + bnx2x_set_aer_mmd(params, ¶ms->phy[0]); + bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); + params->phy[INT_PHY].config_loopback( ¶ms->phy[INT_PHY], params); - } + bnx2x_xmac_enable(params, vars, 1); REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); } @@ -11684,12 +11724,16 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, bnx2x_set_led(params, vars, LED_MODE_OFF, 0); if (reset_ext_phy) { + bnx2x_set_mdio_clk(bp, params->chip_id, port); for (phy_index = EXT_PHY1; phy_index < params->num_phys; phy_index++) { - if (params->phy[phy_index].link_reset) + if (params->phy[phy_index].link_reset) { + bnx2x_set_aer_mmd(params, + ¶ms->phy[phy_index]); params->phy[phy_index].link_reset( ¶ms->phy[phy_index], params); + } if (params->phy[phy_index].flags & FLAGS_REARM_LATCH_SIGNAL) clear_latch_ind = 1; @@ -12178,10 +12222,6 @@ static void bnx2x_analyze_link_error(struct link_params *params, u8 led_mode; u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0; - /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n", - vars->link_up, - half_open_conn, lss_status);*/ - if ((lss_status ^ half_open_conn) == 0) return; @@ -12194,6 +12234,7 @@ static void bnx2x_analyze_link_error(struct link_params *params, * b. Update link_vars->link_up */ if (lss_status) { + DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n"); vars->link_status &= ~LINK_STATUS_LINK_UP; vars->link_up = 0; vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; @@ -12203,6 +12244,7 @@ static void bnx2x_analyze_link_error(struct link_params *params, */ led_mode = LED_MODE_OFF; } else { + DP(NETIF_MSG_LINK, "Remote Fault cleared\n"); vars->link_status |= LINK_STATUS_LINK_UP; vars->link_up = 1; vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; @@ -12219,6 +12261,15 @@ static void bnx2x_analyze_link_error(struct link_params *params, bnx2x_notify_link_changed(bp); } +/****************************************************************************** +* Description: +* This function checks for half opened connection change indication. +* When such change occurs, it calls the bnx2x_analyze_link_error +* to check if Remote Fault is set or cleared. Reception of remote fault +* status message in the MAC indicates that the peer's MAC has detected +* a fault, for example, due to break in the TX side of fiber. +* +******************************************************************************/ static void bnx2x_check_half_open_conn(struct link_params *params, struct link_vars *vars) { @@ -12229,9 +12280,28 @@ static void bnx2x_check_half_open_conn(struct link_params *params, if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) return; - if (!CHIP_IS_E3(bp) && + if (CHIP_IS_E3(bp) && (REG_RD(bp, MISC_REG_RESET_REG_2) & - (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) { + (MISC_REGISTERS_RESET_REG_2_XMAC))) { + /* Check E3 XMAC */ + /* + * Note that link speed cannot be queried here, since it may be + * zero while link is down. In case UMAC is active, LSS will + * simply not be set + */ + mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + + /* Clear stick bits (Requires rising edge) */ + REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); + REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, + XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | + XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); + if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) + lss_status = 1; + + bnx2x_analyze_link_error(params, vars, lss_status); + } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { /* Check E1X / E2 BMAC */ u32 lss_status_reg; u32 wb_data[2]; @@ -12253,14 +12323,20 @@ static void bnx2x_check_half_open_conn(struct link_params *params, void bnx2x_period_func(struct link_params *params, struct link_vars *vars) { struct bnx2x *bp = params->bp; + u16 phy_idx; if (!params) { - DP(NETIF_MSG_LINK, "Ininitliazed params !\n"); + DP(NETIF_MSG_LINK, "Uninitialized params !\n"); return; } - /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x - RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed, - REG_RD(bp, MISC_REG_RESET_REG_2)); */ - bnx2x_check_half_open_conn(params, vars); + + for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { + if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { + bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); + bnx2x_check_half_open_conn(params, vars); + break; + } + } + if (CHIP_IS_E3(bp)) bnx2x_check_over_curr(params, vars); } diff --git a/drivers/net/bnx2x/bnx2x_link.h b/drivers/net/bnx2x/bnx2x_link.h index 6a7708d5da37..c12db6da213e 100644 --- a/drivers/net/bnx2x/bnx2x_link.h +++ b/drivers/net/bnx2x/bnx2x_link.h @@ -145,6 +145,8 @@ struct bnx2x_phy { #define FLAGS_SFP_NOT_APPROVED (1<<7) #define FLAGS_MDC_MDIO_WA (1<<8) #define FLAGS_DUMMY_READ (1<<9) +#define FLAGS_MDC_MDIO_WA_B0 (1<<10) +#define FLAGS_TX_ERROR_CHECK (1<<12) /* preemphasis values for the rx side */ u16 rx_preemphasis[4]; @@ -276,7 +278,6 @@ struct link_vars { #define PHY_PHYSICAL_LINK_FLAG (1<<2) #define PHY_HALF_OPEN_CONN_FLAG (1<<3) #define PHY_OVER_CURRENT_FLAG (1<<4) -#define PHY_TX_ERROR_CHECK_FLAG (1<<5) u8 mac_type; #define MAC_TYPE_NONE 0 diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 02461fef8751..27b5ecb11830 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h @@ -4771,9 +4771,11 @@ The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - header pointer. */ #define UCM_REG_XX_TABLE 0xe0300 +#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28) #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15) #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24) #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5) +#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8) #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4) #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1) #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13) @@ -5622,8 +5624,9 @@ #define EMAC_MDIO_COMM_START_BUSY (1L<<29) #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) -#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) +#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 +#define EMAC_MDIO_STATUS_10MB (1L<<1) #define EMAC_MODE_25G_MODE (1L<<5) #define EMAC_MODE_HALF_DUPLEX (1L<<1) #define EMAC_MODE_PORT_GMII (2L<<2) @@ -5634,6 +5637,7 @@ #define EMAC_REG_EMAC_MAC_MATCH 0x10 #define EMAC_REG_EMAC_MDIO_COMM 0xac #define EMAC_REG_EMAC_MDIO_MODE 0xb4 +#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 #define EMAC_REG_EMAC_MODE 0x0 #define EMAC_REG_EMAC_RX_MODE 0xc8 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c index c5f0f04219f3..5548d464261a 100644 --- a/drivers/net/e1000/e1000_ethtool.c +++ b/drivers/net/e1000/e1000_ethtool.c @@ -838,6 +838,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) /* Disable all the interrupts */ ew32(IMC, 0xFFFFFFFF); + E1000_WRITE_FLUSH(); msleep(10); /* Test each interrupt */ @@ -856,6 +857,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) adapter->test_icr = 0; ew32(IMC, mask); ew32(ICS, mask); + E1000_WRITE_FLUSH(); msleep(10); if (adapter->test_icr & mask) { @@ -873,6 +875,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) adapter->test_icr = 0; ew32(IMS, mask); ew32(ICS, mask); + E1000_WRITE_FLUSH(); msleep(10); if (!(adapter->test_icr & mask)) { @@ -890,6 +893,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) adapter->test_icr = 0; ew32(IMC, ~mask & 0x00007FFF); ew32(ICS, ~mask & 0x00007FFF); + E1000_WRITE_FLUSH(); msleep(10); if (adapter->test_icr) { @@ -901,6 +905,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) /* Disable all the interrupts */ ew32(IMC, 0xFFFFFFFF); + E1000_WRITE_FLUSH(); msleep(10); /* Unhook test interrupt handler */ @@ -1394,6 +1399,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter) if (unlikely(++k == txdr->count)) k = 0; } ew32(TDT, k); + E1000_WRITE_FLUSH(); msleep(200); time = jiffies; /* set the start time for the receive */ good_cnt = 0; diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 1698622af434..8545c7aa93eb 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c @@ -446,6 +446,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw) /* Must reset the PHY before resetting the MAC */ if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); + E1000_WRITE_FLUSH(); msleep(5); } @@ -3752,6 +3753,7 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw) /* Clear SK and CS */ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ew32(EECD, eecd); + E1000_WRITE_FLUSH(); udelay(1); } @@ -3824,6 +3826,7 @@ static void e1000_release_eeprom(struct e1000_hw *hw) eecd &= ~E1000_EECD_SK; /* Lower SCK */ ew32(EECD, eecd); + E1000_WRITE_FLUSH(); udelay(hw->eeprom.delay_usec); } else if (hw->eeprom.type == e1000_eeprom_microwire) { diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c index c0ecb2d9fdb7..e4f42257c24c 100644 --- a/drivers/net/e1000e/es2lan.c +++ b/drivers/net/e1000e/es2lan.c @@ -1313,6 +1313,7 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ew32(KMRNCTRLSTA, kmrnctrlsta); + e1e_flush(); udelay(2); @@ -1347,6 +1348,7 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & E1000_KMRNCTRLSTA_OFFSET) | data; ew32(KMRNCTRLSTA, kmrnctrlsta); + e1e_flush(); udelay(2); diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index cb1a3623253e..06d88f316dce 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c @@ -28,8 +28,8 @@ /* ethtool support for e1000 */ -#include <linux/interrupt.h> #include <linux/netdevice.h> +#include <linux/interrupt.h> #include <linux/ethtool.h> #include <linux/pci.h> #include <linux/slab.h> @@ -964,6 +964,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) /* Disable all the interrupts */ ew32(IMC, 0xFFFFFFFF); + e1e_flush(); usleep_range(10000, 20000); /* Test each interrupt */ @@ -996,6 +997,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) adapter->test_icr = 0; ew32(IMC, mask); ew32(ICS, mask); + e1e_flush(); usleep_range(10000, 20000); if (adapter->test_icr & mask) { @@ -1014,6 +1016,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) adapter->test_icr = 0; ew32(IMS, mask); ew32(ICS, mask); + e1e_flush(); usleep_range(10000, 20000); if (!(adapter->test_icr & mask)) { @@ -1032,6 +1035,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) adapter->test_icr = 0; ew32(IMC, ~mask & 0x00007FFF); ew32(ICS, ~mask & 0x00007FFF); + e1e_flush(); usleep_range(10000, 20000); if (adapter->test_icr) { @@ -1043,6 +1047,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) /* Disable all the interrupts */ ew32(IMC, 0xFFFFFFFF); + e1e_flush(); usleep_range(10000, 20000); /* Unhook test interrupt handler */ @@ -1276,6 +1281,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) E1000_CTRL_FD); /* Force Duplex to FULL */ ew32(CTRL, ctrl_reg); + e1e_flush(); udelay(500); return 0; @@ -1418,6 +1424,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter) */ #define E1000_SERDES_LB_ON 0x410 ew32(SCTL, E1000_SERDES_LB_ON); + e1e_flush(); usleep_range(10000, 20000); return 0; @@ -1513,6 +1520,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter) hw->phy.media_type == e1000_media_type_internal_serdes) { #define E1000_SERDES_LB_OFF 0x400 ew32(SCTL, E1000_SERDES_LB_OFF); + e1e_flush(); usleep_range(10000, 20000); break; } @@ -1592,6 +1600,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter) k = 0; } ew32(TDT, k); + e1e_flush(); msleep(200); time = jiffies; /* set the start time for the receive */ good_cnt = 0; diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index c1752124f3cd..4e36978b8fd8 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -283,6 +283,7 @@ static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; ew32(CTRL, ctrl); + e1e_flush(); udelay(10); ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; ew32(CTRL, ctrl); @@ -1230,9 +1231,11 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) ew32(CTRL, reg); ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); + e1e_flush(); udelay(20); ew32(CTRL, ctrl_reg); ew32(CTRL_EXT, ctrl_ext); + e1e_flush(); udelay(20); out: @@ -2134,8 +2137,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, ret_val = 0; for (i = 0; i < words; i++) { - if ((dev_spec->shadow_ram) && - (dev_spec->shadow_ram[offset+i].modified)) { + if (dev_spec->shadow_ram[offset+i].modified) { data[i] = dev_spec->shadow_ram[offset+i].value; } else { ret_val = e1000_read_flash_word_ich8lan(hw, @@ -3090,6 +3092,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ret_val = e1000_acquire_swflag_ich8lan(hw); e_dbg("Issuing a global reset to ich8lan\n"); ew32(CTRL, (ctrl | E1000_CTRL_RST)); + /* cannot issue a flush here because it hangs the hardware */ msleep(20); if (!ret_val) diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c index 65580b405942..7898a67d6505 100644 --- a/drivers/net/e1000e/lib.c +++ b/drivers/net/e1000e/lib.c @@ -1986,6 +1986,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) /* Clear SK and CS */ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ew32(EECD, eecd); + e1e_flush(); udelay(1); /* diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index 4353ad56cf16..ab4be80f7ab5 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c @@ -31,12 +31,12 @@ #include <linux/module.h> #include <linux/types.h> #include <linux/init.h> -#include <linux/interrupt.h> #include <linux/pci.h> #include <linux/vmalloc.h> #include <linux/pagemap.h> #include <linux/delay.h> #include <linux/netdevice.h> +#include <linux/interrupt.h> #include <linux/tcp.h> #include <linux/ipv6.h> #include <linux/slab.h> diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index 2a6ee13285b1..8666476cb9be 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c @@ -537,6 +537,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; ew32(KMRNCTRLSTA, kmrnctrlsta); + e1e_flush(); udelay(2); @@ -609,6 +610,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & E1000_KMRNCTRLSTA_OFFSET) | data; ew32(KMRNCTRLSTA, kmrnctrlsta); + e1e_flush(); udelay(2); diff --git a/drivers/net/igb/e1000_nvm.c b/drivers/net/igb/e1000_nvm.c index 7dcd65cede56..40407124e722 100644 --- a/drivers/net/igb/e1000_nvm.c +++ b/drivers/net/igb/e1000_nvm.c @@ -285,6 +285,7 @@ static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) /* Clear SK and CS */ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); wr32(E1000_EECD, eecd); + wrfl(); udelay(1); timeout = NVM_MAX_RETRY_SPI; diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c index ff244ce803ce..414b0225be89 100644 --- a/drivers/net/igb/igb_ethtool.c +++ b/drivers/net/igb/igb_ethtool.c @@ -1225,6 +1225,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data) /* Disable all the interrupts */ wr32(E1000_IMC, ~0); + wrfl(); msleep(10); /* Define all writable bits for ICS */ @@ -1268,6 +1269,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data) wr32(E1000_IMC, mask); wr32(E1000_ICS, mask); + wrfl(); msleep(10); if (adapter->test_icr & mask) { @@ -1289,6 +1291,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data) wr32(E1000_IMS, mask); wr32(E1000_ICS, mask); + wrfl(); msleep(10); if (!(adapter->test_icr & mask)) { @@ -1310,6 +1313,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data) wr32(E1000_IMC, ~mask); wr32(E1000_ICS, ~mask); + wrfl(); msleep(10); if (adapter->test_icr & mask) { @@ -1321,6 +1325,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data) /* Disable all the interrupts */ wr32(E1000_IMC, ~0); + wrfl(); msleep(10); /* Unhook test interrupt handler */ diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index dc599059512a..40d4c405fd7e 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c @@ -1052,6 +1052,7 @@ msi_only: kfree(adapter->vf_data); adapter->vf_data = NULL; wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); + wrfl(); msleep(100); dev_info(&adapter->pdev->dev, "IOV Disabled\n"); } @@ -2022,7 +2023,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, if (hw->bus.func == 0) hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); - else if (hw->mac.type == e1000_82580) + else if (hw->mac.type >= e1000_82580) hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, &eeprom_data); @@ -2198,6 +2199,7 @@ static void __devexit igb_remove(struct pci_dev *pdev) kfree(adapter->vf_data); adapter->vf_data = NULL; wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); + wrfl(); msleep(100); dev_info(&pdev->dev, "IOV Disabled\n"); } diff --git a/drivers/net/igbvf/netdev.c b/drivers/net/igbvf/netdev.c index 1330c8e932da..40ed066e3ef4 100644 --- a/drivers/net/igbvf/netdev.c +++ b/drivers/net/igbvf/netdev.c @@ -1226,6 +1226,7 @@ static void igbvf_configure_tx(struct igbvf_adapter *adapter) /* disable transmits */ txdctl = er32(TXDCTL(0)); ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); + e1e_flush(); msleep(10); /* Setup the HW Tx Head and Tail descriptor pointers */ @@ -1306,6 +1307,7 @@ static void igbvf_configure_rx(struct igbvf_adapter *adapter) /* disable receives */ rxdctl = er32(RXDCTL(0)); ew32(RXDCTL(0), rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE); + e1e_flush(); msleep(10); rdlen = rx_ring->count * sizeof(union e1000_adv_rx_desc); diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c index 954f6e938fb7..8b1c3484d271 100644 --- a/drivers/net/irda/smsc-ircc2.c +++ b/drivers/net/irda/smsc-ircc2.c @@ -2405,8 +2405,6 @@ static int __init smsc_superio_lpc(unsigned short cfg_base) * addresses making a subsystem device table necessary. */ #ifdef CONFIG_PCI -#define PCIID_VENDOR_INTEL 0x8086 -#define PCIID_VENDOR_ALI 0x10b9 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { /* * Subsystems needing entries: @@ -2416,7 +2414,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini */ { /* Guessed entry */ - .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ + .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ .device = 0x24cc, .subvendor = 0x103c, .subdevice = 0x08bc, @@ -2429,7 +2427,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini .name = "HP nx5000 family", }, { - .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ + .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ .device = 0x24cc, .subvendor = 0x103c, .subdevice = 0x088c, @@ -2443,7 +2441,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini .name = "HP nc8000 family", }, { - .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ + .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ .device = 0x24cc, .subvendor = 0x103c, .subdevice = 0x0890, @@ -2456,7 +2454,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini .name = "HP nc6000 family", }, { - .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ + .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ .device = 0x24cc, .subvendor = 0x0e11, .subdevice = 0x0860, @@ -2471,7 +2469,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini }, { /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ - .vendor = PCIID_VENDOR_INTEL, + .vendor = PCI_VENDOR_ID_INTEL, .device = 0x24c0, .subvendor = 0x1179, .subdevice = 0xffff, /* 0xffff is "any" */ @@ -2484,7 +2482,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", }, { - .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */ + .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */ .device = 0x248c, .subvendor = 0x1179, .subdevice = 0xffff, /* 0xffff is "any" */ @@ -2498,7 +2496,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini }, { /* 82801DBM (ICH4-M) LPC Interface Bridge */ - .vendor = PCIID_VENDOR_INTEL, + .vendor = PCI_VENDOR_ID_INTEL, .device = 0x24cc, .subvendor = 0x1179, .subdevice = 0xffff, /* 0xffff is "any" */ @@ -2512,7 +2510,7 @@ static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __ini }, { /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ - .vendor = PCIID_VENDOR_ALI, + .vendor = PCI_VENDOR_ID_AL, .device = 0x1533, .subvendor = 0x1179, .subdevice = 0xffff, /* 0xffff is "any" */ diff --git a/drivers/net/ixgb/ixgb_ee.c b/drivers/net/ixgb/ixgb_ee.c index c982ab9f9005..38b362b67857 100644 --- a/drivers/net/ixgb/ixgb_ee.c +++ b/drivers/net/ixgb/ixgb_ee.c @@ -57,6 +57,7 @@ ixgb_raise_clock(struct ixgb_hw *hw, */ *eecd_reg = *eecd_reg | IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, *eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); } @@ -75,6 +76,7 @@ ixgb_lower_clock(struct ixgb_hw *hw, */ *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, *eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); } @@ -112,6 +114,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw, eecd_reg |= IXGB_EECD_DI; IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); @@ -206,21 +209,25 @@ ixgb_standby_eeprom(struct ixgb_hw *hw) /* Deselect EEPROM */ eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); /* Clock high */ eecd_reg |= IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); /* Select EEPROM */ eecd_reg |= IXGB_EECD_CS; IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); /* Clock low */ eecd_reg &= ~IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); } @@ -239,11 +246,13 @@ ixgb_clock_eeprom(struct ixgb_hw *hw) /* Rising edge of clock */ eecd_reg |= IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); /* Falling edge of clock */ eecd_reg &= ~IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); + IXGB_WRITE_FLUSH(hw); udelay(50); } diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c index 6cb2e42ff4c1..3d61a9e4faf7 100644 --- a/drivers/net/ixgb/ixgb_hw.c +++ b/drivers/net/ixgb/ixgb_hw.c @@ -149,6 +149,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw) */ IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); + IXGB_WRITE_FLUSH(hw); msleep(IXGB_DELAY_BEFORE_RESET); /* Issue a global reset to the MAC. This will reset the chip's @@ -1220,6 +1221,7 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw) ctrl &= ~IXGB_CTRL0_SDP2; ctrl |= IXGB_CTRL0_SDP3; IXGB_WRITE_REG(hw, CTRL0, ctrl); + IXGB_WRITE_FLUSH(hw); /* SerDes needs extra delay */ msleep(IXGB_SUN_PHY_RESET_DELAY); diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c index 3b3dd4df4c5c..34f30ec79c2e 100644 --- a/drivers/net/ixgbe/ixgbe_82599.c +++ b/drivers/net/ixgbe/ixgbe_82599.c @@ -213,6 +213,7 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) switch (hw->phy.type) { case ixgbe_phy_tn: phy->ops.check_link = &ixgbe_check_phy_link_tnx; + phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; phy->ops.get_firmware_version = &ixgbe_get_phy_firmware_version_tnx; break; diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index 777051f54e53..fc1375f26fe5 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c @@ -2632,6 +2632,7 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) autoc_reg |= IXGBE_AUTOC_AN_RESTART; autoc_reg |= IXGBE_AUTOC_FLU; IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); + IXGBE_WRITE_FLUSH(hw); usleep_range(10000, 20000); } diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c index dc649553a0a6..82d4244c6e10 100644 --- a/drivers/net/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ixgbe/ixgbe_ethtool.c @@ -1378,6 +1378,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) /* Disable all the interrupts */ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); + IXGBE_WRITE_FLUSH(&adapter->hw); usleep_range(10000, 20000); /* Test each interrupt */ @@ -1398,6 +1399,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) ~mask & 0x00007FFF); IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, ~mask & 0x00007FFF); + IXGBE_WRITE_FLUSH(&adapter->hw); usleep_range(10000, 20000); if (adapter->test_icr & mask) { @@ -1415,6 +1417,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) adapter->test_icr = 0; IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); + IXGBE_WRITE_FLUSH(&adapter->hw); usleep_range(10000, 20000); if (!(adapter->test_icr &mask)) { @@ -1435,6 +1438,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) ~mask & 0x00007FFF); IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, ~mask & 0x00007FFF); + IXGBE_WRITE_FLUSH(&adapter->hw); usleep_range(10000, 20000); if (adapter->test_icr) { @@ -1446,6 +1450,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) /* Disable all the interrupts */ IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); + IXGBE_WRITE_FLUSH(&adapter->hw); usleep_range(10000, 20000); /* Unhook test interrupt handler */ diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 1be617545dc9..e86297b32733 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -184,6 +184,7 @@ static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); + IXGBE_WRITE_FLUSH(hw); /* take a breather then clean up driver data */ msleep(100); @@ -1005,7 +1006,7 @@ static int __ixgbe_notify_dca(struct device *dev, void *data) struct ixgbe_adapter *adapter = dev_get_drvdata(dev); unsigned long event = *(unsigned long *)data; - if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) + if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) return 0; switch (event) { diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c index 735f686c3b36..f7ca3511b9fe 100644 --- a/drivers/net/ixgbe/ixgbe_phy.c +++ b/drivers/net/ixgbe/ixgbe_phy.c @@ -1585,6 +1585,7 @@ static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) *i2cctl |= IXGBE_I2C_CLK_OUT; IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); + IXGBE_WRITE_FLUSH(hw); /* SCL rise time (1000ns) */ udelay(IXGBE_I2C_T_RISE); @@ -1605,6 +1606,7 @@ static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) *i2cctl &= ~IXGBE_I2C_CLK_OUT; IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); + IXGBE_WRITE_FLUSH(hw); /* SCL fall time (300ns) */ udelay(IXGBE_I2C_T_FALL); @@ -1628,6 +1630,7 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) *i2cctl &= ~IXGBE_I2C_DATA_OUT; IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); + IXGBE_WRITE_FLUSH(hw); /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); diff --git a/drivers/net/ixgbe/ixgbe_x540.c b/drivers/net/ixgbe/ixgbe_x540.c index bec30ed91adc..2696c78e9f46 100644 --- a/drivers/net/ixgbe/ixgbe_x540.c +++ b/drivers/net/ixgbe/ixgbe_x540.c @@ -162,6 +162,7 @@ mac_reset_top: ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); + IXGBE_WRITE_FLUSH(hw); msleep(50); diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 0fcdc25699d8..dc4e305a1087 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -322,6 +322,9 @@ static void macb_tx(struct macb *bp) for (i = 0; i < TX_RING_SIZE; i++) bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /* Add wrap bit */ + bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); + /* free transmit buffer in upper layer*/ for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { struct ring_info *rp = &bp->tx_skb[tail]; diff --git a/drivers/net/mlx4/en_port.c b/drivers/net/mlx4/en_port.c index 5e7109178061..5ada5b469112 100644 --- a/drivers/net/mlx4/en_port.c +++ b/drivers/net/mlx4/en_port.c @@ -128,7 +128,7 @@ int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, memset(context, 0, sizeof *context); context->base_qpn = cpu_to_be32(base_qpn); - context->n_mac = 0x7; + context->n_mac = 0x2; context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT | base_qpn); context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT | diff --git a/drivers/net/mlx4/main.c b/drivers/net/mlx4/main.c index c94b3426d355..f0ee35df4dd7 100644 --- a/drivers/net/mlx4/main.c +++ b/drivers/net/mlx4/main.c @@ -1117,6 +1117,8 @@ static int mlx4_init_port_info(struct mlx4_dev *dev, int port) info->port = port; mlx4_init_mac_table(dev, &info->mac_table); mlx4_init_vlan_table(dev, &info->vlan_table); + info->base_qpn = dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + + (port - 1) * (1 << log_num_mac); sprintf(info->dev_name, "mlx4_port%d", port); info->port_attr.attr.name = info->dev_name; diff --git a/drivers/net/mlx4/port.c b/drivers/net/mlx4/port.c index 1f95afda6841..609e0ec14cee 100644 --- a/drivers/net/mlx4/port.c +++ b/drivers/net/mlx4/port.c @@ -258,9 +258,12 @@ void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn) if (validate_index(dev, table, index)) goto out; - table->entries[index] = 0; - mlx4_set_port_mac_table(dev, port, table->entries); - --table->total; + /* Check whether this address has reference count */ + if (!(--table->refs[index])) { + table->entries[index] = 0; + mlx4_set_port_mac_table(dev, port, table->entries); + --table->total; + } out: mutex_unlock(&table->mutex); } diff --git a/drivers/net/niu.c b/drivers/net/niu.c index cd6c2317e29e..ed47585a6862 100644 --- a/drivers/net/niu.c +++ b/drivers/net/niu.c @@ -9201,7 +9201,7 @@ static int __devinit niu_ldg_init(struct niu *np) first_chan = 0; for (i = 0; i < port; i++) - first_chan += parent->rxchan_per_port[port]; + first_chan += parent->rxchan_per_port[i]; num_chan = parent->rxchan_per_port[port]; for (i = first_chan; i < (first_chan + num_chan); i++) { @@ -9217,7 +9217,7 @@ static int __devinit niu_ldg_init(struct niu *np) first_chan = 0; for (i = 0; i < port; i++) - first_chan += parent->txchan_per_port[port]; + first_chan += parent->txchan_per_port[i]; num_chan = parent->txchan_per_port[port]; for (i = first_chan; i < (first_chan + num_chan); i++) { err = niu_ldg_assign_ldn(np, parent, diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 7d9c650f395e..02339b3352e7 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -239,6 +239,7 @@ static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, { PCI_VENDOR_ID_LINKSYS, 0x1032, @@ -1091,6 +1092,21 @@ rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); } +struct exgmac_reg { + u16 addr; + u16 mask; + u32 val; +}; + +static void rtl_write_exgmac_batch(void __iomem *ioaddr, + const struct exgmac_reg *r, int len) +{ + while (len-- > 0) { + rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); + r++; + } +} + static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) { u8 value = 0xff; @@ -3116,6 +3132,18 @@ static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) RTL_W32(MAC0, low); RTL_R32(MAC0); + if (tp->mac_version == RTL_GIGA_MAC_VER_34) { + const struct exgmac_reg e[] = { + { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, + { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, + { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, + { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | + low >> 16 }, + }; + + rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); + } + RTL_W8(Cfg9346, Cfg9346_Lock); spin_unlock_irq(&tp->lock); diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c index 8ad7bfbaa3af..3c0f1312b391 100644 --- a/drivers/net/sis190.c +++ b/drivers/net/sis190.c @@ -1825,6 +1825,16 @@ static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL); } +static int sis190_mac_addr(struct net_device *dev, void *p) +{ + int rc; + + rc = eth_mac_addr(dev, p); + if (!rc) + sis190_init_rxfilter(dev); + return rc; +} + static const struct net_device_ops sis190_netdev_ops = { .ndo_open = sis190_open, .ndo_stop = sis190_close, @@ -1833,7 +1843,7 @@ static const struct net_device_ops sis190_netdev_ops = { .ndo_tx_timeout = sis190_tx_timeout, .ndo_set_multicast_list = sis190_set_rx_mode, .ndo_change_mtu = eth_change_mtu, - .ndo_set_mac_address = eth_mac_addr, + .ndo_set_mac_address = sis190_mac_addr, .ndo_validate_addr = eth_validate_addr, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = sis190_netpoll, diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index fd622a66ebbf..a03336e086d5 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -53,7 +53,7 @@ #include <linux/usb/usbnet.h> #include <linux/usb/cdc.h> -#define DRIVER_VERSION "01-June-2011" +#define DRIVER_VERSION "04-Aug-2011" /* CDC NCM subclass 3.2.1 */ #define USB_CDC_NCM_NDP16_LENGTH_MIN 0x10 @@ -163,35 +163,8 @@ cdc_ncm_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info) usb_make_path(dev->udev, info->bus_info, sizeof(info->bus_info)); } -static int -cdc_ncm_do_request(struct cdc_ncm_ctx *ctx, struct usb_cdc_notification *req, - void *data, u16 flags, u16 *actlen, u16 timeout) -{ - int err; - - err = usb_control_msg(ctx->udev, (req->bmRequestType & USB_DIR_IN) ? - usb_rcvctrlpipe(ctx->udev, 0) : - usb_sndctrlpipe(ctx->udev, 0), - req->bNotificationType, req->bmRequestType, - req->wValue, - req->wIndex, data, - req->wLength, timeout); - - if (err < 0) { - if (actlen) - *actlen = 0; - return err; - } - - if (actlen) - *actlen = err; - - return 0; -} - static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx) { - struct usb_cdc_notification req; u32 val; u8 flags; u8 iface_no; @@ -200,14 +173,14 @@ static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx) iface_no = ctx->control->cur_altsetting->desc.bInterfaceNumber; - req.bmRequestType = USB_TYPE_CLASS | USB_DIR_IN | USB_RECIP_INTERFACE; - req.bNotificationType = USB_CDC_GET_NTB_PARAMETERS; - req.wValue = 0; - req.wIndex = cpu_to_le16(iface_no); - req.wLength = cpu_to_le16(sizeof(ctx->ncm_parm)); - - err = cdc_ncm_do_request(ctx, &req, &ctx->ncm_parm, 0, NULL, 1000); - if (err) { + err = usb_control_msg(ctx->udev, + usb_rcvctrlpipe(ctx->udev, 0), + USB_CDC_GET_NTB_PARAMETERS, + USB_TYPE_CLASS | USB_DIR_IN + | USB_RECIP_INTERFACE, + 0, iface_no, &ctx->ncm_parm, + sizeof(ctx->ncm_parm), 10000); + if (err < 0) { pr_debug("failed GET_NTB_PARAMETERS\n"); return 1; } @@ -253,31 +226,26 @@ static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx) /* inform device about NTB input size changes */ if (ctx->rx_max != le32_to_cpu(ctx->ncm_parm.dwNtbInMaxSize)) { - req.bmRequestType = USB_TYPE_CLASS | USB_DIR_OUT | - USB_RECIP_INTERFACE; - req.bNotificationType = USB_CDC_SET_NTB_INPUT_SIZE; - req.wValue = 0; - req.wIndex = cpu_to_le16(iface_no); if (flags & USB_CDC_NCM_NCAP_NTB_INPUT_SIZE) { struct usb_cdc_ncm_ndp_input_size ndp_in_sz; - - req.wLength = 8; - ndp_in_sz.dwNtbInMaxSize = cpu_to_le32(ctx->rx_max); - ndp_in_sz.wNtbInMaxDatagrams = - cpu_to_le16(CDC_NCM_DPT_DATAGRAMS_MAX); - ndp_in_sz.wReserved = 0; - err = cdc_ncm_do_request(ctx, &req, &ndp_in_sz, 0, NULL, - 1000); + err = usb_control_msg(ctx->udev, + usb_sndctrlpipe(ctx->udev, 0), + USB_CDC_SET_NTB_INPUT_SIZE, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + 0, iface_no, &ndp_in_sz, 8, 1000); } else { __le32 dwNtbInMaxSize = cpu_to_le32(ctx->rx_max); - - req.wLength = 4; - err = cdc_ncm_do_request(ctx, &req, &dwNtbInMaxSize, 0, - NULL, 1000); + err = usb_control_msg(ctx->udev, + usb_sndctrlpipe(ctx->udev, 0), + USB_CDC_SET_NTB_INPUT_SIZE, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + 0, iface_no, &dwNtbInMaxSize, 4, 1000); } - if (err) + if (err < 0) pr_debug("Setting NTB Input Size failed\n"); } @@ -332,29 +300,24 @@ static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx) /* set CRC Mode */ if (flags & USB_CDC_NCM_NCAP_CRC_MODE) { - req.bmRequestType = USB_TYPE_CLASS | USB_DIR_OUT | - USB_RECIP_INTERFACE; - req.bNotificationType = USB_CDC_SET_CRC_MODE; - req.wValue = cpu_to_le16(USB_CDC_NCM_CRC_NOT_APPENDED); - req.wIndex = cpu_to_le16(iface_no); - req.wLength = 0; - - err = cdc_ncm_do_request(ctx, &req, NULL, 0, NULL, 1000); - if (err) + err = usb_control_msg(ctx->udev, usb_sndctrlpipe(ctx->udev, 0), + USB_CDC_SET_CRC_MODE, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_CRC_NOT_APPENDED, + iface_no, NULL, 0, 1000); + if (err < 0) pr_debug("Setting CRC mode off failed\n"); } /* set NTB format, if both formats are supported */ if (ntb_fmt_supported & USB_CDC_NCM_NTH32_SIGN) { - req.bmRequestType = USB_TYPE_CLASS | USB_DIR_OUT | - USB_RECIP_INTERFACE; - req.bNotificationType = USB_CDC_SET_NTB_FORMAT; - req.wValue = cpu_to_le16(USB_CDC_NCM_NTB16_FORMAT); - req.wIndex = cpu_to_le16(iface_no); - req.wLength = 0; - - err = cdc_ncm_do_request(ctx, &req, NULL, 0, NULL, 1000); - if (err) + err = usb_control_msg(ctx->udev, usb_sndctrlpipe(ctx->udev, 0), + USB_CDC_SET_NTB_FORMAT, USB_TYPE_CLASS + | USB_DIR_OUT | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB16_FORMAT, + iface_no, NULL, 0, 1000); + if (err < 0) pr_debug("Setting NTB format to 16-bit failed\n"); } @@ -364,17 +327,13 @@ static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx) if (flags & USB_CDC_NCM_NCAP_MAX_DATAGRAM_SIZE) { __le16 max_datagram_size; u16 eth_max_sz = le16_to_cpu(ctx->ether_desc->wMaxSegmentSize); - - req.bmRequestType = USB_TYPE_CLASS | USB_DIR_IN | - USB_RECIP_INTERFACE; - req.bNotificationType = USB_CDC_GET_MAX_DATAGRAM_SIZE; - req.wValue = 0; - req.wIndex = cpu_to_le16(iface_no); - req.wLength = cpu_to_le16(2); - - err = cdc_ncm_do_request(ctx, &req, &max_datagram_size, 0, NULL, - 1000); - if (err) { + err = usb_control_msg(ctx->udev, usb_rcvctrlpipe(ctx->udev, 0), + USB_CDC_GET_MAX_DATAGRAM_SIZE, + USB_TYPE_CLASS | USB_DIR_IN + | USB_RECIP_INTERFACE, + 0, iface_no, &max_datagram_size, + 2, 1000); + if (err < 0) { pr_debug("GET_MAX_DATAGRAM_SIZE failed, use size=%u\n", CDC_NCM_MIN_DATAGRAM_SIZE); } else { @@ -395,17 +354,15 @@ static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx) CDC_NCM_MIN_DATAGRAM_SIZE; /* if value changed, update device */ - req.bmRequestType = USB_TYPE_CLASS | USB_DIR_OUT | - USB_RECIP_INTERFACE; - req.bNotificationType = USB_CDC_SET_MAX_DATAGRAM_SIZE; - req.wValue = 0; - req.wIndex = cpu_to_le16(iface_no); - req.wLength = 2; - max_datagram_size = cpu_to_le16(ctx->max_datagram_size); - - err = cdc_ncm_do_request(ctx, &req, &max_datagram_size, - 0, NULL, 1000); - if (err) + err = usb_control_msg(ctx->udev, + usb_sndctrlpipe(ctx->udev, 0), + USB_CDC_SET_MAX_DATAGRAM_SIZE, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + 0, + iface_no, &max_datagram_size, + 2, 1000); + if (err < 0) pr_debug("SET_MAX_DATAGRAM_SIZE failed\n"); } @@ -671,7 +628,7 @@ cdc_ncm_fill_tx_frame(struct cdc_ncm_ctx *ctx, struct sk_buff *skb) u32 rem; u32 offset; u32 last_offset; - u16 n = 0; + u16 n = 0, index; u8 ready2send = 0; /* if there is a remaining skb, it gets priority */ @@ -859,8 +816,8 @@ cdc_ncm_fill_tx_frame(struct cdc_ncm_ctx *ctx, struct sk_buff *skb) cpu_to_le16(sizeof(ctx->tx_ncm.nth16)); ctx->tx_ncm.nth16.wSequence = cpu_to_le16(ctx->tx_seq); ctx->tx_ncm.nth16.wBlockLength = cpu_to_le16(last_offset); - ctx->tx_ncm.nth16.wNdpIndex = ALIGN(sizeof(struct usb_cdc_ncm_nth16), - ctx->tx_ndp_modulus); + index = ALIGN(sizeof(struct usb_cdc_ncm_nth16), ctx->tx_ndp_modulus); + ctx->tx_ncm.nth16.wNdpIndex = cpu_to_le16(index); memcpy(skb_out->data, &(ctx->tx_ncm.nth16), sizeof(ctx->tx_ncm.nth16)); ctx->tx_seq++; @@ -873,12 +830,11 @@ cdc_ncm_fill_tx_frame(struct cdc_ncm_ctx *ctx, struct sk_buff *skb) ctx->tx_ncm.ndp16.wLength = cpu_to_le16(rem); ctx->tx_ncm.ndp16.wNextNdpIndex = 0; /* reserved */ - memcpy(((u8 *)skb_out->data) + ctx->tx_ncm.nth16.wNdpIndex, + memcpy(((u8 *)skb_out->data) + index, &(ctx->tx_ncm.ndp16), sizeof(ctx->tx_ncm.ndp16)); - memcpy(((u8 *)skb_out->data) + ctx->tx_ncm.nth16.wNdpIndex + - sizeof(ctx->tx_ncm.ndp16), + memcpy(((u8 *)skb_out->data) + index + sizeof(ctx->tx_ncm.ndp16), &(ctx->tx_ncm.dpe16), (ctx->tx_curr_frame_num + 1) * sizeof(struct usb_cdc_ncm_dpe16)); diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c index 9ff7c30573b8..44d9d8d56490 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c @@ -309,11 +309,7 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, u8 i; u32 val; - if (ah->is_pciexpress != true) - return; - - /* Do not touch SerDes registers */ - if (ah->config.pcie_powersave_enable == 2) + if (ah->is_pciexpress != true || ah->aspm_enabled != true) return; /* Nothing to do on restore for 11N */ diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 8efdec247c02..ad2bb2bf4e8a 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -519,11 +519,7 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off) { - if (ah->is_pciexpress != true) - return; - - /* Do not touch SerDes registers */ - if (ah->config.pcie_powersave_enable == 2) + if (ah->is_pciexpress != true || ah->aspm_enabled != true) return; /* Nothing to do on restore for 11N */ diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 8006ce0c7357..8dcefe74f4c3 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c @@ -318,6 +318,14 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah) REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); } +static void ath9k_hw_aspm_init(struct ath_hw *ah) +{ + struct ath_common *common = ath9k_hw_common(ah); + + if (common->bus_ops->aspm_init) + common->bus_ops->aspm_init(common); +} + /* This should work for all families including legacy */ static bool ath9k_hw_chip_test(struct ath_hw *ah) { @@ -378,7 +386,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah) ah->config.additional_swba_backoff = 0; ah->config.ack_6mb = 0x0; ah->config.cwm_ignore_extcca = 0; - ah->config.pcie_powersave_enable = 0; ah->config.pcie_clock_req = 0; ah->config.pcie_waen = 0; ah->config.analog_shiftreg = 1; @@ -598,7 +605,7 @@ static int __ath9k_hw_init(struct ath_hw *ah) if (ah->is_pciexpress) - ath9k_hw_configpcipowersave(ah, 0, 0); + ath9k_hw_aspm_init(ah); else ath9k_hw_disablepcie(ah); diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 6acd0f975ae1..c79889036ec4 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h @@ -219,7 +219,6 @@ struct ath9k_ops_config { int additional_swba_backoff; int ack_6mb; u32 cwm_ignore_extcca; - u8 pcie_powersave_enable; bool pcieSerDesWrite; u8 pcie_clock_req; u32 pcie_waen; @@ -673,6 +672,7 @@ struct ath_hw { bool sw_mgmt_crypto; bool is_pciexpress; + bool aspm_enabled; bool is_monitoring; bool need_an_top2_fixup; u16 tx_trig_level; @@ -874,6 +874,7 @@ struct ath_bus_ops { bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); void (*bt_coex_prep)(struct ath_common *common); void (*extn_synch_en)(struct ath_common *common); + void (*aspm_init)(struct ath_common *common); }; static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index ac5107172f94..aa0ff7e2c922 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c @@ -670,8 +670,10 @@ static void ath9k_init_band_txpower(struct ath_softc *sc, int band) static void ath9k_init_txpower_limits(struct ath_softc *sc) { struct ath_hw *ah = sc->sc_ah; + struct ath_common *common = ath9k_hw_common(sc->sc_ah); struct ath9k_channel *curchan = ah->curchan; + ah->txchainmask = common->tx_chainmask; if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index 3bad0b2cf9a3..be4ea1329813 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -16,6 +16,7 @@ #include <linux/nl80211.h> #include <linux/pci.h> +#include <linux/pci-aspm.h> #include <linux/ath9k_platform.h> #include "ath9k.h" @@ -115,12 +116,38 @@ static void ath_pci_extn_synch_enable(struct ath_common *common) pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); } +static void ath_pci_aspm_init(struct ath_common *common) +{ + struct ath_softc *sc = (struct ath_softc *) common->priv; + struct ath_hw *ah = sc->sc_ah; + struct pci_dev *pdev = to_pci_dev(sc->dev); + struct pci_dev *parent; + int pos; + u8 aspm; + + if (!pci_is_pcie(pdev)) + return; + + parent = pdev->bus->self; + if (WARN_ON(!parent)) + return; + + pos = pci_pcie_cap(parent); + pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); + if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { + ah->aspm_enabled = true; + /* Initialize PCIe PM and SERDES registers. */ + ath9k_hw_configpcipowersave(ah, 0, 0); + } +} + static const struct ath_bus_ops ath_pci_bus_ops = { .ath_bus_type = ATH_PCI, .read_cachesize = ath_pci_read_cachesize, .eeprom_read = ath_pci_eeprom_read, .bt_coex_prep = ath_pci_bt_coex_prep, .extn_synch_en = ath_pci_extn_synch_enable, + .aspm_init = ath_pci_aspm_init, }; static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) diff --git a/drivers/net/wireless/iwlegacy/iwl-3945.c b/drivers/net/wireless/iwlegacy/iwl-3945.c index dab67a12d73b..73fe3cdf796b 100644 --- a/drivers/net/wireless/iwlegacy/iwl-3945.c +++ b/drivers/net/wireless/iwlegacy/iwl-3945.c @@ -1746,7 +1746,11 @@ int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx) } memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); - + /* + * We do not commit tx power settings while channel changing, + * do it now if tx power changed. + */ + iwl_legacy_set_tx_power(priv, priv->tx_power_next, false); return 0; } diff --git a/drivers/net/wireless/iwlegacy/iwl-4965.c b/drivers/net/wireless/iwlegacy/iwl-4965.c index bd4b000733f7..ecdc6e557428 100644 --- a/drivers/net/wireless/iwlegacy/iwl-4965.c +++ b/drivers/net/wireless/iwlegacy/iwl-4965.c @@ -1235,7 +1235,12 @@ static int iwl4965_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *c memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); iwl_legacy_print_rx_config_cmd(priv, ctx); - goto set_tx_power; + /* + * We do not commit tx power settings while channel changing, + * do it now if tx power changed. + */ + iwl_legacy_set_tx_power(priv, priv->tx_power_next, false); + return 0; } /* If we are currently associated and the new config requires @@ -1315,7 +1320,6 @@ static int iwl4965_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *c iwl4965_init_sensitivity(priv); -set_tx_power: /* If we issue a new RXON command which required a tune then we must * send a new TXPOWER command or we won't be able to Tx any frames */ ret = iwl_legacy_set_tx_power(priv, priv->tx_power_next, true); diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c index 3eeb12ebe6e9..c95cefd529dc 100644 --- a/drivers/net/wireless/iwlwifi/iwl-5000.c +++ b/drivers/net/wireless/iwlwifi/iwl-5000.c @@ -365,6 +365,7 @@ static struct iwl_base_params iwl5000_base_params = { .chain_noise_scale = 1000, .wd_timeout = IWL_LONG_WD_TIMEOUT, .max_event_log_size = 512, + .no_idle_support = true, }; static struct iwl_ht_params iwl5000_ht_params = { .ht_greenfield_support = true, diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h index 3e6bb734dcb7..02817a438550 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.h +++ b/drivers/net/wireless/iwlwifi/iwl-core.h @@ -135,6 +135,7 @@ struct iwl_mod_params { * @temperature_kelvin: temperature report by uCode in kelvin * @max_event_log_size: size of event log buffer size for ucode event logging * @shadow_reg_enable: HW shadhow register bit + * @no_idle_support: do not support idle mode */ struct iwl_base_params { int eeprom_size; @@ -156,6 +157,7 @@ struct iwl_base_params { bool temperature_kelvin; u32 max_event_log_size; const bool shadow_reg_enable; + const bool no_idle_support; }; /* * @advanced_bt_coexist: support advanced bt coexist diff --git a/drivers/net/wireless/iwlwifi/iwl-pci.c b/drivers/net/wireless/iwlwifi/iwl-pci.c index fb7e436b40c7..69d4ec467dca 100644 --- a/drivers/net/wireless/iwlwifi/iwl-pci.c +++ b/drivers/net/wireless/iwlwifi/iwl-pci.c @@ -134,6 +134,7 @@ static void iwl_pci_apm_config(struct iwl_bus *bus) static void iwl_pci_set_drv_data(struct iwl_bus *bus, void *drv_data) { bus->drv_data = drv_data; + pci_set_drvdata(IWL_BUS_GET_PCI_DEV(bus), drv_data); } static void iwl_pci_get_hw_id(struct iwl_bus *bus, char buf[], @@ -454,8 +455,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); } - pci_set_drvdata(pdev, bus); - bus->dev = &pdev->dev; bus->irq = pdev->irq; bus->ops = &pci_ops; @@ -494,11 +493,12 @@ static void iwl_pci_down(struct iwl_bus *bus) static void __devexit iwl_pci_remove(struct pci_dev *pdev) { - struct iwl_bus *bus = pci_get_drvdata(pdev); + struct iwl_priv *priv = pci_get_drvdata(pdev); + void *bus_specific = priv->bus->bus_specific; - iwl_remove(bus->drv_data); + iwl_remove(priv); - iwl_pci_down(bus); + iwl_pci_down(bus_specific); } #ifdef CONFIG_PM @@ -506,20 +506,20 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev) static int iwl_pci_suspend(struct device *device) { struct pci_dev *pdev = to_pci_dev(device); - struct iwl_bus *bus = pci_get_drvdata(pdev); + struct iwl_priv *priv = pci_get_drvdata(pdev); /* Before you put code here, think about WoWLAN. You cannot check here * whether WoWLAN is enabled or not, and your code will run even if * WoWLAN is enabled - don't kill the NIC, someone may need it in Sx. */ - return iwl_suspend(bus->drv_data); + return iwl_suspend(priv); } static int iwl_pci_resume(struct device *device) { struct pci_dev *pdev = to_pci_dev(device); - struct iwl_bus *bus = pci_get_drvdata(pdev); + struct iwl_priv *priv = pci_get_drvdata(pdev); /* Before you put code here, think about WoWLAN. You cannot check here * whether WoWLAN is enabled or not, and your code will run even if @@ -532,7 +532,7 @@ static int iwl_pci_resume(struct device *device) */ pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); - return iwl_resume(bus->drv_data); + return iwl_resume(priv); } static SIMPLE_DEV_PM_OPS(iwl_dev_pm_ops, iwl_pci_suspend, iwl_pci_resume); diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c index 3ec619c6881c..cd64df05f9ed 100644 --- a/drivers/net/wireless/iwlwifi/iwl-power.c +++ b/drivers/net/wireless/iwlwifi/iwl-power.c @@ -349,7 +349,8 @@ static void iwl_power_build_cmd(struct iwl_priv *priv, if (priv->wowlan) iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper); - else if (priv->hw->conf.flags & IEEE80211_CONF_IDLE) + else if (!priv->cfg->base_params->no_idle_support && + priv->hw->conf.flags & IEEE80211_CONF_IDLE) iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20); else if (iwl_tt_is_low_power_state(priv)) { /* in thermal throttling low power state */ diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index 84ab7d1acb6a..ef67f6786a84 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c @@ -703,8 +703,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) /* * Add space for the TXWI in front of the skb. */ - skb_push(entry->skb, TXWI_DESC_SIZE); - memset(entry->skb, 0, TXWI_DESC_SIZE); + memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE); /* * Register descriptor details in skb frame descriptor. diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h index 15cdc7e57fc4..4cdf247a870d 100644 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h @@ -355,7 +355,8 @@ static inline enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf * return CIPHER_NONE; } -static inline void rt2x00crypto_create_tx_descriptor(struct queue_entry *entry, +static inline void rt2x00crypto_create_tx_descriptor(struct rt2x00_dev *rt2x00dev, + struct sk_buff *skb, struct txentry_desc *txdesc) { } diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c index 8efab3983528..4ccf23805973 100644 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c @@ -113,7 +113,7 @@ void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) * due to possible race conditions in mac80211. */ if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) - goto exit_fail; + goto exit_free_skb; /* * Use the ATIM queue if appropriate and present. @@ -127,7 +127,7 @@ void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) ERROR(rt2x00dev, "Attempt to send packet over invalid queue %d.\n" "Please file bug report to %s.\n", qid, DRV_PROJECT); - goto exit_fail; + goto exit_free_skb; } /* @@ -159,6 +159,7 @@ void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) exit_fail: rt2x00queue_pause_queue(queue); + exit_free_skb: dev_kfree_skb_any(skb); } EXPORT_SYMBOL_GPL(rt2x00mac_tx); diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c index 5efd57833489..56f12358389d 100644 --- a/drivers/net/wireless/rtlwifi/pci.c +++ b/drivers/net/wireless/rtlwifi/pci.c @@ -1696,15 +1696,17 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); - /*find bridge info */ - pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; - for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { - if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { - pcipriv->ndis_adapter.pcibridge_vendor = tmp; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - ("Pci Bridge Vendor is found index: %d\n", - tmp)); - break; + if (bridge_pdev) { + /*find bridge info if available */ + pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; + for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { + if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { + pcipriv->ndis_adapter.pcibridge_vendor = tmp; + RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, + ("Pci Bridge Vendor is found index:" + " %d\n", tmp)); + break; + } } } diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 45e0191c35dd..1e88d4785321 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -769,4 +769,12 @@ config INTEL_OAKTRAIL enable/disable the Camera, WiFi, BT etc. devices. If in doubt, say Y here; it will only load on supported platforms. +config SAMSUNG_Q10 + tristate "Samsung Q10 Extras" + depends on SERIO_I8042 + select BACKLIGHT_CLASS_DEVICE + ---help--- + This driver provides support for backlight control on Samsung Q10 + and related laptops, including Dell Latitude X200. + endif # X86_PLATFORM_DEVICES diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile index afc1f832aa67..293a320d9faa 100644 --- a/drivers/platform/x86/Makefile +++ b/drivers/platform/x86/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_SAMSUNG_LAPTOP) += samsung-laptop.o obj-$(CONFIG_MXM_WMI) += mxm-wmi.o obj-$(CONFIG_INTEL_MID_POWER_BUTTON) += intel_mid_powerbtn.o obj-$(CONFIG_INTEL_OAKTRAIL) += intel_oaktrail.o +obj-$(CONFIG_SAMSUNG_Q10) += samsung-q10.o diff --git a/drivers/platform/x86/acer-wmi.c b/drivers/platform/x86/acer-wmi.c index e1c4938b301b..af2bb20cb2fb 100644 --- a/drivers/platform/x86/acer-wmi.c +++ b/drivers/platform/x86/acer-wmi.c @@ -99,6 +99,7 @@ enum acer_wmi_event_ids { static const struct key_entry acer_wmi_keymap[] = { {KE_KEY, 0x01, {KEY_WLAN} }, /* WiFi */ {KE_KEY, 0x03, {KEY_WLAN} }, /* WiFi */ + {KE_KEY, 0x04, {KEY_WLAN} }, /* WiFi */ {KE_KEY, 0x12, {KEY_BLUETOOTH} }, /* BT */ {KE_KEY, 0x21, {KEY_PROG1} }, /* Backup */ {KE_KEY, 0x22, {KEY_PROG2} }, /* Arcade */ @@ -304,6 +305,10 @@ static struct quirk_entry quirk_fujitsu_amilo_li_1718 = { .wireless = 2, }; +static struct quirk_entry quirk_lenovo_ideapad_s205 = { + .wireless = 3, +}; + /* The Aspire One has a dummy ACPI-WMI interface - disable it */ static struct dmi_system_id __devinitdata acer_blacklist[] = { { @@ -450,6 +455,15 @@ static struct dmi_system_id acer_quirks[] = { }, .driver_data = &quirk_medion_md_98300, }, + { + .callback = dmi_matched, + .ident = "Lenovo Ideapad S205", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_NAME, "10382LG"), + }, + .driver_data = &quirk_lenovo_ideapad_s205, + }, {} }; @@ -542,6 +556,12 @@ struct wmi_interface *iface) return AE_ERROR; *value = result & 0x1; return AE_OK; + case 3: + err = ec_read(0x78, &result); + if (err) + return AE_ERROR; + *value = result & 0x1; + return AE_OK; default: err = ec_read(0xA, &result); if (err) @@ -1266,8 +1286,13 @@ static void acer_rfkill_update(struct work_struct *ignored) acpi_status status; status = get_u32(&state, ACER_CAP_WIRELESS); - if (ACPI_SUCCESS(status)) - rfkill_set_sw_state(wireless_rfkill, !state); + if (ACPI_SUCCESS(status)) { + if (quirks->wireless == 3) { + rfkill_set_hw_state(wireless_rfkill, !state); + } else { + rfkill_set_sw_state(wireless_rfkill, !state); + } + } if (has_cap(ACER_CAP_BLUETOOTH)) { status = get_u32(&state, ACER_CAP_BLUETOOTH); @@ -1400,6 +1425,9 @@ static ssize_t show_bool_threeg(struct device *dev, { u32 result; \ acpi_status status; + + pr_info("This threeg sysfs will be removed in 2012" + " - used by: %s\n", current->comm); if (wmi_has_guid(WMID_GUID3)) status = wmid3_get_device_status(&result, ACER_WMID3_GDS_THREEG); @@ -1415,8 +1443,10 @@ static ssize_t set_bool_threeg(struct device *dev, { u32 tmp = simple_strtoul(buf, NULL, 10); acpi_status status = set_u32(tmp, ACER_CAP_THREEG); - if (ACPI_FAILURE(status)) - return -EINVAL; + pr_info("This threeg sysfs will be removed in 2012" + " - used by: %s\n", current->comm); + if (ACPI_FAILURE(status)) + return -EINVAL; return count; } static DEVICE_ATTR(threeg, S_IRUGO | S_IWUSR, show_bool_threeg, @@ -1425,6 +1455,8 @@ static DEVICE_ATTR(threeg, S_IRUGO | S_IWUSR, show_bool_threeg, static ssize_t show_interface(struct device *dev, struct device_attribute *attr, char *buf) { + pr_info("This interface sysfs will be removed in 2012" + " - used by: %s\n", current->comm); switch (interface->type) { case ACER_AMW0: return sprintf(buf, "AMW0\n"); diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c index fca3489218b7..760c6d7624fe 100644 --- a/drivers/platform/x86/acerhdf.c +++ b/drivers/platform/x86/acerhdf.c @@ -182,6 +182,7 @@ static const struct bios_settings_t bios_tbl[] = { {"Acer", "Aspire 1810T", "v1.3308", 0x55, 0x58, {0x9e, 0x00} }, {"Acer", "Aspire 1810TZ", "v1.3310", 0x55, 0x58, {0x9e, 0x00} }, {"Acer", "Aspire 1810T", "v1.3310", 0x55, 0x58, {0x9e, 0x00} }, + {"Acer", "Aspire 1810TZ", "v1.3314", 0x55, 0x58, {0x9e, 0x00} }, /* Acer 531 */ {"Acer", "AO531h", "v0.3201", 0x55, 0x58, {0x20, 0x00} }, /* Gateway */ @@ -703,15 +704,15 @@ MODULE_LICENSE("GPL"); MODULE_AUTHOR("Peter Feuerer"); MODULE_DESCRIPTION("Aspire One temperature and fan driver"); MODULE_ALIAS("dmi:*:*Acer*:pnAOA*:"); -MODULE_ALIAS("dmi:*:*Acer*:pnAspire 1410*:"); -MODULE_ALIAS("dmi:*:*Acer*:pnAspire 1810*:"); +MODULE_ALIAS("dmi:*:*Acer*:pnAspire*1410*:"); +MODULE_ALIAS("dmi:*:*Acer*:pnAspire*1810*:"); MODULE_ALIAS("dmi:*:*Acer*:pnAO531*:"); MODULE_ALIAS("dmi:*:*Gateway*:pnAOA*:"); MODULE_ALIAS("dmi:*:*Gateway*:pnLT31*:"); -MODULE_ALIAS("dmi:*:*Packard Bell*:pnAOA*:"); -MODULE_ALIAS("dmi:*:*Packard Bell*:pnDOA*:"); -MODULE_ALIAS("dmi:*:*Packard Bell*:pnDOTMU*:"); -MODULE_ALIAS("dmi:*:*Packard Bell*:pnDOTMA*:"); +MODULE_ALIAS("dmi:*:*Packard*Bell*:pnAOA*:"); +MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOA*:"); +MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOTMU*:"); +MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOTMA*:"); module_init(acerhdf_init); module_exit(acerhdf_exit); diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index d65df92e2acc..fa6d7ec68b26 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -70,11 +70,10 @@ MODULE_LICENSE("GPL"); * WAPF defines the behavior of the Fn+Fx wlan key * The significance of values is yet to be found, but * most of the time: - * 0x0 will do nothing - * 0x1 will allow to control the device with Fn+Fx key. - * 0x4 will send an ACPI event (0x88) while pressing the Fn+Fx key - * 0x5 like 0x1 or 0x4 - * So, if something doesn't work as you want, just try other values =) + * Bit | Bluetooth | WLAN + * 0 | Hardware | Hardware + * 1 | Hardware | Software + * 4 | Software | Software */ static uint wapf = 1; module_param(wapf, uint, 0444); diff --git a/drivers/platform/x86/asus-nb-wmi.c b/drivers/platform/x86/asus-nb-wmi.c index 0580d99b0798..b0859d4183e8 100644 --- a/drivers/platform/x86/asus-nb-wmi.c +++ b/drivers/platform/x86/asus-nb-wmi.c @@ -38,6 +38,24 @@ MODULE_LICENSE("GPL"); MODULE_ALIAS("wmi:"ASUS_NB_WMI_EVENT_GUID); +/* + * WAPF defines the behavior of the Fn+Fx wlan key + * The significance of values is yet to be found, but + * most of the time: + * Bit | Bluetooth | WLAN + * 0 | Hardware | Hardware + * 1 | Hardware | Software + * 4 | Software | Software + */ +static uint wapf; +module_param(wapf, uint, 0444); +MODULE_PARM_DESC(wapf, "WAPF value"); + +static void asus_nb_wmi_quirks(struct asus_wmi_driver *driver) +{ + driver->wapf = wapf; +} + static const struct key_entry asus_nb_wmi_keymap[] = { { KE_KEY, 0x30, { KEY_VOLUMEUP } }, { KE_KEY, 0x31, { KEY_VOLUMEDOWN } }, @@ -53,16 +71,16 @@ static const struct key_entry asus_nb_wmi_keymap[] = { { KE_KEY, 0x51, { KEY_WWW } }, { KE_KEY, 0x55, { KEY_CALC } }, { KE_KEY, 0x5C, { KEY_F15 } }, /* Power Gear key */ - { KE_KEY, 0x5D, { KEY_WLAN } }, - { KE_KEY, 0x5E, { KEY_WLAN } }, - { KE_KEY, 0x5F, { KEY_WLAN } }, + { KE_KEY, 0x5D, { KEY_WLAN } }, /* Wireless console Toggle */ + { KE_KEY, 0x5E, { KEY_WLAN } }, /* Wireless console Enable */ + { KE_KEY, 0x5F, { KEY_WLAN } }, /* Wireless console Disable */ { KE_KEY, 0x60, { KEY_SWITCHVIDEOMODE } }, { KE_KEY, 0x61, { KEY_SWITCHVIDEOMODE } }, { KE_KEY, 0x62, { KEY_SWITCHVIDEOMODE } }, { KE_KEY, 0x63, { KEY_SWITCHVIDEOMODE } }, { KE_KEY, 0x6B, { KEY_TOUCHPAD_TOGGLE } }, - { KE_KEY, 0x7E, { KEY_BLUETOOTH } }, { KE_KEY, 0x7D, { KEY_BLUETOOTH } }, + { KE_KEY, 0x7E, { KEY_BLUETOOTH } }, { KE_KEY, 0x82, { KEY_CAMERA } }, { KE_KEY, 0x88, { KEY_RFKILL } }, { KE_KEY, 0x8A, { KEY_PROG1 } }, @@ -81,6 +99,7 @@ static struct asus_wmi_driver asus_nb_wmi_driver = { .keymap = asus_nb_wmi_keymap, .input_name = "Asus WMI hotkeys", .input_phys = ASUS_NB_WMI_FILE "/input0", + .quirks = asus_nb_wmi_quirks, }; diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c index 65b66aa44c78..95cba9ebf6c0 100644 --- a/drivers/platform/x86/asus-wmi.c +++ b/drivers/platform/x86/asus-wmi.c @@ -44,6 +44,7 @@ #include <linux/debugfs.h> #include <linux/seq_file.h> #include <linux/platform_device.h> +#include <linux/thermal.h> #include <acpi/acpi_bus.h> #include <acpi/acpi_drivers.h> @@ -66,6 +67,8 @@ MODULE_LICENSE("GPL"); #define NOTIFY_BRNUP_MAX 0x1f #define NOTIFY_BRNDOWN_MIN 0x20 #define NOTIFY_BRNDOWN_MAX 0x2e +#define NOTIFY_KBD_BRTUP 0xc4 +#define NOTIFY_KBD_BRTDWN 0xc5 /* WMI Methods */ #define ASUS_WMI_METHODID_SPEC 0x43455053 /* BIOS SPECification */ @@ -93,6 +96,7 @@ MODULE_LICENSE("GPL"); /* Wireless */ #define ASUS_WMI_DEVID_HW_SWITCH 0x00010001 #define ASUS_WMI_DEVID_WIRELESS_LED 0x00010002 +#define ASUS_WMI_DEVID_CWAP 0x00010003 #define ASUS_WMI_DEVID_WLAN 0x00010011 #define ASUS_WMI_DEVID_BLUETOOTH 0x00010013 #define ASUS_WMI_DEVID_GPS 0x00010015 @@ -102,6 +106,12 @@ MODULE_LICENSE("GPL"); /* Leds */ /* 0x000200XX and 0x000400XX */ +#define ASUS_WMI_DEVID_LED1 0x00020011 +#define ASUS_WMI_DEVID_LED2 0x00020012 +#define ASUS_WMI_DEVID_LED3 0x00020013 +#define ASUS_WMI_DEVID_LED4 0x00020014 +#define ASUS_WMI_DEVID_LED5 0x00020015 +#define ASUS_WMI_DEVID_LED6 0x00020016 /* Backlight and Brightness */ #define ASUS_WMI_DEVID_BACKLIGHT 0x00050011 @@ -174,13 +184,18 @@ struct asus_wmi { struct led_classdev tpd_led; int tpd_led_wk; + struct led_classdev kbd_led; + int kbd_led_wk; struct workqueue_struct *led_workqueue; struct work_struct tpd_led_work; + struct work_struct kbd_led_work; struct asus_rfkill wlan; struct asus_rfkill bluetooth; struct asus_rfkill wimax; struct asus_rfkill wwan3g; + struct asus_rfkill gps; + struct asus_rfkill uwb; struct hotplug_slot *hotplug_slot; struct mutex hotplug_lock; @@ -205,6 +220,7 @@ static int asus_wmi_input_init(struct asus_wmi *asus) asus->inputdev->phys = asus->driver->input_phys; asus->inputdev->id.bustype = BUS_HOST; asus->inputdev->dev.parent = &asus->platform_device->dev; + set_bit(EV_REP, asus->inputdev->evbit); err = sparse_keymap_setup(asus->inputdev, asus->driver->keymap, NULL); if (err) @@ -359,30 +375,80 @@ static enum led_brightness tpd_led_get(struct led_classdev *led_cdev) return read_tpd_led_state(asus); } -static int asus_wmi_led_init(struct asus_wmi *asus) +static void kbd_led_update(struct work_struct *work) { - int rv; + int ctrl_param = 0; + struct asus_wmi *asus; - if (read_tpd_led_state(asus) < 0) - return 0; + asus = container_of(work, struct asus_wmi, kbd_led_work); - asus->led_workqueue = create_singlethread_workqueue("led_workqueue"); - if (!asus->led_workqueue) - return -ENOMEM; - INIT_WORK(&asus->tpd_led_work, tpd_led_update); + /* + * bits 0-2: level + * bit 7: light on/off + */ + if (asus->kbd_led_wk > 0) + ctrl_param = 0x80 | (asus->kbd_led_wk & 0x7F); - asus->tpd_led.name = "asus::touchpad"; - asus->tpd_led.brightness_set = tpd_led_set; - asus->tpd_led.brightness_get = tpd_led_get; - asus->tpd_led.max_brightness = 1; + asus_wmi_set_devstate(ASUS_WMI_DEVID_KBD_BACKLIGHT, ctrl_param, NULL); +} - rv = led_classdev_register(&asus->platform_device->dev, &asus->tpd_led); - if (rv) { - destroy_workqueue(asus->led_workqueue); - return rv; +static int kbd_led_read(struct asus_wmi *asus, int *level, int *env) +{ + int retval; + + /* + * bits 0-2: level + * bit 7: light on/off + * bit 8-10: environment (0: dark, 1: normal, 2: light) + * bit 17: status unknown + */ + retval = asus_wmi_get_devstate_bits(asus, ASUS_WMI_DEVID_KBD_BACKLIGHT, + 0xFFFF); + + /* Unknown status is considered as off */ + if (retval == 0x8000) + retval = 0; + + if (retval >= 0) { + if (level) + *level = retval & 0x80 ? retval & 0x7F : 0; + if (env) + *env = (retval >> 8) & 0x7F; + retval = 0; } - return 0; + return retval; +} + +static void kbd_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct asus_wmi *asus; + + asus = container_of(led_cdev, struct asus_wmi, kbd_led); + + if (value > asus->kbd_led.max_brightness) + value = asus->kbd_led.max_brightness; + else if (value < 0) + value = 0; + + asus->kbd_led_wk = value; + queue_work(asus->led_workqueue, &asus->kbd_led_work); +} + +static enum led_brightness kbd_led_get(struct led_classdev *led_cdev) +{ + struct asus_wmi *asus; + int retval, value; + + asus = container_of(led_cdev, struct asus_wmi, kbd_led); + + retval = kbd_led_read(asus, &value, NULL); + + if (retval < 0) + return retval; + + return value; } static void asus_wmi_led_exit(struct asus_wmi *asus) @@ -393,6 +459,48 @@ static void asus_wmi_led_exit(struct asus_wmi *asus) destroy_workqueue(asus->led_workqueue); } +static int asus_wmi_led_init(struct asus_wmi *asus) +{ + int rv = 0; + + asus->led_workqueue = create_singlethread_workqueue("led_workqueue"); + if (!asus->led_workqueue) + return -ENOMEM; + + if (read_tpd_led_state(asus) >= 0) { + INIT_WORK(&asus->tpd_led_work, tpd_led_update); + + asus->tpd_led.name = "asus::touchpad"; + asus->tpd_led.brightness_set = tpd_led_set; + asus->tpd_led.brightness_get = tpd_led_get; + asus->tpd_led.max_brightness = 1; + + rv = led_classdev_register(&asus->platform_device->dev, + &asus->tpd_led); + if (rv) + goto error; + } + + if (kbd_led_read(asus, NULL, NULL) >= 0) { + INIT_WORK(&asus->kbd_led_work, kbd_led_update); + + asus->kbd_led.name = "asus::kbd_backlight"; + asus->kbd_led.brightness_set = kbd_led_set; + asus->kbd_led.brightness_get = kbd_led_get; + asus->kbd_led.max_brightness = 3; + + rv = led_classdev_register(&asus->platform_device->dev, + &asus->kbd_led); + } + +error: + if (rv) + asus_wmi_led_exit(asus); + + return rv; +} + + /* * PCI hotplug (for wlan rfkill) */ @@ -729,6 +837,16 @@ static void asus_wmi_rfkill_exit(struct asus_wmi *asus) rfkill_destroy(asus->wwan3g.rfkill); asus->wwan3g.rfkill = NULL; } + if (asus->gps.rfkill) { + rfkill_unregister(asus->gps.rfkill); + rfkill_destroy(asus->gps.rfkill); + asus->gps.rfkill = NULL; + } + if (asus->uwb.rfkill) { + rfkill_unregister(asus->uwb.rfkill); + rfkill_destroy(asus->uwb.rfkill); + asus->uwb.rfkill = NULL; + } } static int asus_wmi_rfkill_init(struct asus_wmi *asus) @@ -763,6 +881,18 @@ static int asus_wmi_rfkill_init(struct asus_wmi *asus) if (result && result != -ENODEV) goto exit; + result = asus_new_rfkill(asus, &asus->gps, "asus-gps", + RFKILL_TYPE_GPS, ASUS_WMI_DEVID_GPS); + + if (result && result != -ENODEV) + goto exit; + + result = asus_new_rfkill(asus, &asus->uwb, "asus-uwb", + RFKILL_TYPE_UWB, ASUS_WMI_DEVID_UWB); + + if (result && result != -ENODEV) + goto exit; + if (!asus->driver->hotplug_wireless) goto exit; @@ -797,8 +927,8 @@ exit: * Hwmon device */ static ssize_t asus_hwmon_pwm1(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { struct asus_wmi *asus = dev_get_drvdata(dev); u32 value; @@ -809,7 +939,7 @@ static ssize_t asus_hwmon_pwm1(struct device *dev, if (err < 0) return err; - value |= 0xFF; + value &= 0xFF; if (value == 1) /* Low Speed */ value = 85; @@ -825,7 +955,26 @@ static ssize_t asus_hwmon_pwm1(struct device *dev, return sprintf(buf, "%d\n", value); } +static ssize_t asus_hwmon_temp1(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct asus_wmi *asus = dev_get_drvdata(dev); + u32 value; + int err; + + err = asus_wmi_get_devstate(asus, ASUS_WMI_DEVID_THERMAL_CTRL, &value); + + if (err < 0) + return err; + + value = KELVIN_TO_CELSIUS((value & 0xFFFF)) * 1000; + + return sprintf(buf, "%d\n", value); +} + static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO, asus_hwmon_pwm1, NULL, 0); +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, asus_hwmon_temp1, NULL, 0); static ssize_t show_name(struct device *dev, struct device_attribute *attr, char *buf) @@ -836,12 +985,13 @@ static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, 0); static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_pwm1.dev_attr.attr, + &sensor_dev_attr_temp1_input.dev_attr.attr, &sensor_dev_attr_name.dev_attr.attr, NULL }; static mode_t asus_hwmon_sysfs_is_visible(struct kobject *kobj, - struct attribute *attr, int idx) + struct attribute *attr, int idx) { struct device *dev = container_of(kobj, struct device, kobj); struct platform_device *pdev = to_platform_device(dev->parent); @@ -852,6 +1002,8 @@ static mode_t asus_hwmon_sysfs_is_visible(struct kobject *kobj, if (attr == &sensor_dev_attr_pwm1.dev_attr.attr) dev_id = ASUS_WMI_DEVID_FAN_CTRL; + else if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr) + dev_id = ASUS_WMI_DEVID_THERMAL_CTRL; if (dev_id != -1) { int err = asus_wmi_get_devstate(asus, dev_id, &value); @@ -869,9 +1021,13 @@ static mode_t asus_hwmon_sysfs_is_visible(struct kobject *kobj, * - reverved bits are non-zero * - sfun and presence bit are not set */ - if (value != ASUS_WMI_UNSUPPORTED_METHOD || value & 0xFFF80000 + if (value == ASUS_WMI_UNSUPPORTED_METHOD || value & 0xFFF80000 || (!asus->sfun && !(value & ASUS_WMI_DSTS_PRESENCE_BIT))) ok = false; + } else if (dev_id == ASUS_WMI_DEVID_THERMAL_CTRL) { + /* If value is zero, something is clearly wrong */ + if (value == 0) + ok = false; } return ok ? attr->mode : 0; @@ -904,6 +1060,7 @@ static int asus_wmi_hwmon_init(struct asus_wmi *asus) pr_err("Could not register asus hwmon device\n"); return PTR_ERR(hwmon); } + dev_set_drvdata(hwmon, asus); asus->hwmon_device = hwmon; result = sysfs_create_group(&hwmon->kobj, &hwmon_attribute_group); if (result) @@ -1060,6 +1217,8 @@ static void asus_wmi_notify(u32 value, void *context) acpi_status status; int code; int orig_code; + unsigned int key_value = 1; + bool autorelease = 1; status = wmi_get_event_data(value, &response); if (status != AE_OK) { @@ -1075,6 +1234,13 @@ static void asus_wmi_notify(u32 value, void *context) code = obj->integer.value; orig_code = code; + if (asus->driver->key_filter) { + asus->driver->key_filter(asus->driver, &code, &key_value, + &autorelease); + if (code == ASUS_WMI_KEY_IGNORE) + goto exit; + } + if (code >= NOTIFY_BRNUP_MIN && code <= NOTIFY_BRNUP_MAX) code = NOTIFY_BRNUP_MIN; else if (code >= NOTIFY_BRNDOWN_MIN && @@ -1084,7 +1250,8 @@ static void asus_wmi_notify(u32 value, void *context) if (code == NOTIFY_BRNUP_MIN || code == NOTIFY_BRNDOWN_MIN) { if (!acpi_video_backlight_support()) asus_wmi_backlight_notify(asus, orig_code); - } else if (!sparse_keymap_report_event(asus->inputdev, code, 1, true)) + } else if (!sparse_keymap_report_event(asus->inputdev, code, + key_value, autorelease)) pr_info("Unknown key %x pressed\n", code); exit: @@ -1164,14 +1331,18 @@ ASUS_WMI_CREATE_DEVICE_ATTR(cardr, 0644, ASUS_WMI_DEVID_CARDREADER); static ssize_t store_cpufv(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - int value; + int value, rv; if (!count || sscanf(buf, "%i", &value) != 1) return -EINVAL; if (value < 0 || value > 2) return -EINVAL; - return asus_wmi_evaluate_method(ASUS_WMI_METHODID_CFVS, value, 0, NULL); + rv = asus_wmi_evaluate_method(ASUS_WMI_METHODID_CFVS, value, 0, NULL); + if (rv < 0) + return rv; + + return count; } static DEVICE_ATTR(cpufv, S_IRUGO | S_IWUSR, NULL, store_cpufv); @@ -1234,7 +1405,7 @@ static int asus_wmi_platform_init(struct asus_wmi *asus) /* We don't know yet what to do with this version... */ if (!asus_wmi_evaluate_method(ASUS_WMI_METHODID_SPEC, 0, 0x9, &rv)) { - pr_info("BIOS WMI version: %d.%d", rv >> 8, rv & 0xFF); + pr_info("BIOS WMI version: %d.%d", rv >> 16, rv & 0xFF); asus->spec = rv; } @@ -1266,6 +1437,12 @@ static int asus_wmi_platform_init(struct asus_wmi *asus) return -ENODEV; } + /* CWAP allow to define the behavior of the Fn+F2 key, + * this method doesn't seems to be present on Eee PCs */ + if (asus->driver->wapf >= 0) + asus_wmi_set_devstate(ASUS_WMI_DEVID_CWAP, + asus->driver->wapf, NULL); + return asus_wmi_sysfs_init(asus->platform_device); } @@ -1568,6 +1745,14 @@ static int asus_hotk_restore(struct device *device) bl = !asus_wmi_get_devstate_simple(asus, ASUS_WMI_DEVID_WWAN3G); rfkill_set_sw_state(asus->wwan3g.rfkill, bl); } + if (asus->gps.rfkill) { + bl = !asus_wmi_get_devstate_simple(asus, ASUS_WMI_DEVID_GPS); + rfkill_set_sw_state(asus->gps.rfkill, bl); + } + if (asus->uwb.rfkill) { + bl = !asus_wmi_get_devstate_simple(asus, ASUS_WMI_DEVID_UWB); + rfkill_set_sw_state(asus->uwb.rfkill, bl); + } return 0; } @@ -1604,7 +1789,7 @@ static int asus_wmi_probe(struct platform_device *pdev) static bool used; -int asus_wmi_register_driver(struct asus_wmi_driver *driver) +int __init_or_module asus_wmi_register_driver(struct asus_wmi_driver *driver) { struct platform_driver *platform_driver; struct platform_device *platform_device; diff --git a/drivers/platform/x86/asus-wmi.h b/drivers/platform/x86/asus-wmi.h index c044522c8766..8147c10161cc 100644 --- a/drivers/platform/x86/asus-wmi.h +++ b/drivers/platform/x86/asus-wmi.h @@ -29,12 +29,15 @@ #include <linux/platform_device.h> +#define ASUS_WMI_KEY_IGNORE (-1) + struct module; struct key_entry; struct asus_wmi; struct asus_wmi_driver { bool hotplug_wireless; + int wapf; const char *name; struct module *owner; @@ -44,6 +47,10 @@ struct asus_wmi_driver { const struct key_entry *keymap; const char *input_name; const char *input_phys; + /* Returns new code, value, and autorelease values in arguments. + * Return ASUS_WMI_KEY_IGNORE in code if event should be ignored. */ + void (*key_filter) (struct asus_wmi_driver *driver, int *code, + unsigned int *value, bool *autorelease); int (*probe) (struct platform_device *device); void (*quirks) (struct asus_wmi_driver *driver); diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c index e39ab1d3ed87..f31fa4efa725 100644 --- a/drivers/platform/x86/dell-laptop.c +++ b/drivers/platform/x86/dell-laptop.c @@ -612,7 +612,6 @@ static int __init dell_init(void) if (!bufferpage) goto fail_buffer; buffer = page_address(bufferpage); - mutex_init(&buffer_mutex); ret = dell_setup_rfkill(); diff --git a/drivers/platform/x86/dell-wmi.c b/drivers/platform/x86/dell-wmi.c index ce790827e199..fa9a2171cc13 100644 --- a/drivers/platform/x86/dell-wmi.c +++ b/drivers/platform/x86/dell-wmi.c @@ -54,6 +54,8 @@ MODULE_ALIAS("wmi:"DELL_EVENT_GUID); */ static const struct key_entry dell_wmi_legacy_keymap[] __initconst = { + { KE_IGNORE, 0x003a, { KEY_CAPSLOCK } }, + { KE_KEY, 0xe045, { KEY_PROG1 } }, { KE_KEY, 0xe009, { KEY_EJECTCD } }, @@ -85,6 +87,11 @@ static const struct key_entry dell_wmi_legacy_keymap[] __initconst = { { KE_IGNORE, 0xe013, { KEY_RESERVED } }, { KE_IGNORE, 0xe020, { KEY_MUTE } }, + + /* Shortcut and audio panel keys */ + { KE_IGNORE, 0xe025, { KEY_RESERVED } }, + { KE_IGNORE, 0xe026, { KEY_RESERVED } }, + { KE_IGNORE, 0xe02e, { KEY_VOLUMEDOWN } }, { KE_IGNORE, 0xe030, { KEY_VOLUMEUP } }, { KE_IGNORE, 0xe033, { KEY_KBDILLUMUP } }, @@ -92,6 +99,9 @@ static const struct key_entry dell_wmi_legacy_keymap[] __initconst = { { KE_IGNORE, 0xe03a, { KEY_CAPSLOCK } }, { KE_IGNORE, 0xe045, { KEY_NUMLOCK } }, { KE_IGNORE, 0xe046, { KEY_SCROLLLOCK } }, + { KE_IGNORE, 0xe0f7, { KEY_MUTE } }, + { KE_IGNORE, 0xe0f8, { KEY_VOLUMEDOWN } }, + { KE_IGNORE, 0xe0f9, { KEY_VOLUMEUP } }, { KE_END, 0 } }; diff --git a/drivers/platform/x86/eeepc-wmi.c b/drivers/platform/x86/eeepc-wmi.c index 4aa867a9b88b..9f6e64302b45 100644 --- a/drivers/platform/x86/eeepc-wmi.c +++ b/drivers/platform/x86/eeepc-wmi.c @@ -56,6 +56,11 @@ MODULE_PARM_DESC(hotplug_wireless, "If your laptop needs that, please report to " "acpi4asus-user@lists.sourceforge.net."); +/* Values for T101MT "Home" key */ +#define HOME_PRESS 0xe4 +#define HOME_HOLD 0xea +#define HOME_RELEASE 0xe5 + static const struct key_entry eeepc_wmi_keymap[] = { /* Sleep already handled via generic ACPI code */ { KE_KEY, 0x30, { KEY_VOLUMEUP } }, @@ -71,6 +76,7 @@ static const struct key_entry eeepc_wmi_keymap[] = { { KE_KEY, 0xcc, { KEY_SWITCHVIDEOMODE } }, { KE_KEY, 0xe0, { KEY_PROG1 } }, /* Task Manager */ { KE_KEY, 0xe1, { KEY_F14 } }, /* Change Resolution */ + { KE_KEY, HOME_PRESS, { KEY_CONFIG } }, /* Home/Express gate key */ { KE_KEY, 0xe8, { KEY_SCREENLOCK } }, { KE_KEY, 0xe9, { KEY_BRIGHTNESS_ZERO } }, { KE_KEY, 0xeb, { KEY_CAMERA_ZOOMOUT } }, @@ -81,6 +87,25 @@ static const struct key_entry eeepc_wmi_keymap[] = { { KE_END, 0}, }; +static void eeepc_wmi_key_filter(struct asus_wmi_driver *asus_wmi, int *code, + unsigned int *value, bool *autorelease) +{ + switch (*code) { + case HOME_PRESS: + *value = 1; + *autorelease = 0; + break; + case HOME_HOLD: + *code = ASUS_WMI_KEY_IGNORE; + break; + case HOME_RELEASE: + *code = HOME_PRESS; + *value = 0; + *autorelease = 0; + break; + } +} + static acpi_status eeepc_wmi_parse_device(acpi_handle handle, u32 level, void *context, void **retval) { @@ -141,6 +166,7 @@ static void eeepc_dmi_check(struct asus_wmi_driver *driver) static void eeepc_wmi_quirks(struct asus_wmi_driver *driver) { driver->hotplug_wireless = hotplug_wireless; + driver->wapf = -1; eeepc_dmi_check(driver); } @@ -151,6 +177,7 @@ static struct asus_wmi_driver asus_wmi_driver = { .keymap = eeepc_wmi_keymap, .input_name = "Eee PC WMI hotkeys", .input_phys = EEEPC_WMI_FILE "/input0", + .key_filter = eeepc_wmi_key_filter, .probe = eeepc_wmi_probe, .quirks = eeepc_wmi_quirks, }; diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c index bfdda33feb26..0c595410e788 100644 --- a/drivers/platform/x86/ideapad-laptop.c +++ b/drivers/platform/x86/ideapad-laptop.c @@ -32,13 +32,22 @@ #include <linux/platform_device.h> #include <linux/input.h> #include <linux/input/sparse-keymap.h> +#include <linux/backlight.h> +#include <linux/fb.h> #define IDEAPAD_RFKILL_DEV_NUM (3) +#define CFG_BT_BIT (16) +#define CFG_3G_BIT (17) +#define CFG_WIFI_BIT (18) +#define CFG_CAMERA_BIT (19) + struct ideapad_private { struct rfkill *rfk[IDEAPAD_RFKILL_DEV_NUM]; struct platform_device *platform_device; struct input_dev *inputdev; + struct backlight_device *blightdev; + unsigned long cfg; }; static acpi_handle ideapad_handle; @@ -155,7 +164,7 @@ static int write_ec_cmd(acpi_handle handle, int cmd, unsigned long data) } /* - * camera power + * sysfs */ static ssize_t show_ideapad_cam(struct device *dev, struct device_attribute *attr, @@ -186,6 +195,44 @@ static ssize_t store_ideapad_cam(struct device *dev, static DEVICE_ATTR(camera_power, 0644, show_ideapad_cam, store_ideapad_cam); +static ssize_t show_ideapad_cfg(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ideapad_private *priv = dev_get_drvdata(dev); + + return sprintf(buf, "0x%.8lX\n", priv->cfg); +} + +static DEVICE_ATTR(cfg, 0444, show_ideapad_cfg, NULL); + +static struct attribute *ideapad_attributes[] = { + &dev_attr_camera_power.attr, + &dev_attr_cfg.attr, + NULL +}; + +static mode_t ideapad_is_visible(struct kobject *kobj, + struct attribute *attr, + int idx) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct ideapad_private *priv = dev_get_drvdata(dev); + bool supported; + + if (attr == &dev_attr_camera_power.attr) + supported = test_bit(CFG_CAMERA_BIT, &(priv->cfg)); + else + supported = true; + + return supported ? attr->mode : 0; +} + +static struct attribute_group ideapad_attribute_group = { + .is_visible = ideapad_is_visible, + .attrs = ideapad_attributes +}; + /* * Rfkill */ @@ -197,9 +244,9 @@ struct ideapad_rfk_data { }; const struct ideapad_rfk_data ideapad_rfk_data[] = { - { "ideapad_wlan", 18, 0x15, RFKILL_TYPE_WLAN }, - { "ideapad_bluetooth", 16, 0x17, RFKILL_TYPE_BLUETOOTH }, - { "ideapad_3g", 17, 0x20, RFKILL_TYPE_WWAN }, + { "ideapad_wlan", CFG_WIFI_BIT, 0x15, RFKILL_TYPE_WLAN }, + { "ideapad_bluetooth", CFG_BT_BIT, 0x17, RFKILL_TYPE_BLUETOOTH }, + { "ideapad_3g", CFG_3G_BIT, 0x20, RFKILL_TYPE_WWAN }, }; static int ideapad_rfk_set(void *data, bool blocked) @@ -265,8 +312,7 @@ static int __devinit ideapad_register_rfkill(struct acpi_device *adevice, return 0; } -static void __devexit ideapad_unregister_rfkill(struct acpi_device *adevice, - int dev) +static void ideapad_unregister_rfkill(struct acpi_device *adevice, int dev) { struct ideapad_private *priv = dev_get_drvdata(&adevice->dev); @@ -280,15 +326,6 @@ static void __devexit ideapad_unregister_rfkill(struct acpi_device *adevice, /* * Platform device */ -static struct attribute *ideapad_attributes[] = { - &dev_attr_camera_power.attr, - NULL -}; - -static struct attribute_group ideapad_attribute_group = { - .attrs = ideapad_attributes -}; - static int __devinit ideapad_platform_init(struct ideapad_private *priv) { int result; @@ -369,7 +406,7 @@ err_free_dev: return error; } -static void __devexit ideapad_input_exit(struct ideapad_private *priv) +static void ideapad_input_exit(struct ideapad_private *priv) { sparse_keymap_free(priv->inputdev); input_unregister_device(priv->inputdev); @@ -383,6 +420,98 @@ static void ideapad_input_report(struct ideapad_private *priv, } /* + * backlight + */ +static int ideapad_backlight_get_brightness(struct backlight_device *blightdev) +{ + unsigned long now; + + if (read_ec_data(ideapad_handle, 0x12, &now)) + return -EIO; + return now; +} + +static int ideapad_backlight_update_status(struct backlight_device *blightdev) +{ + if (write_ec_cmd(ideapad_handle, 0x13, blightdev->props.brightness)) + return -EIO; + if (write_ec_cmd(ideapad_handle, 0x33, + blightdev->props.power == FB_BLANK_POWERDOWN ? 0 : 1)) + return -EIO; + + return 0; +} + +static const struct backlight_ops ideapad_backlight_ops = { + .get_brightness = ideapad_backlight_get_brightness, + .update_status = ideapad_backlight_update_status, +}; + +static int ideapad_backlight_init(struct ideapad_private *priv) +{ + struct backlight_device *blightdev; + struct backlight_properties props; + unsigned long max, now, power; + + if (read_ec_data(ideapad_handle, 0x11, &max)) + return -EIO; + if (read_ec_data(ideapad_handle, 0x12, &now)) + return -EIO; + if (read_ec_data(ideapad_handle, 0x18, &power)) + return -EIO; + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = max; + props.type = BACKLIGHT_PLATFORM; + blightdev = backlight_device_register("ideapad", + &priv->platform_device->dev, + priv, + &ideapad_backlight_ops, + &props); + if (IS_ERR(blightdev)) { + pr_err("Could not register backlight device\n"); + return PTR_ERR(blightdev); + } + + priv->blightdev = blightdev; + blightdev->props.brightness = now; + blightdev->props.power = power ? FB_BLANK_UNBLANK : FB_BLANK_POWERDOWN; + backlight_update_status(blightdev); + + return 0; +} + +static void ideapad_backlight_exit(struct ideapad_private *priv) +{ + if (priv->blightdev) + backlight_device_unregister(priv->blightdev); + priv->blightdev = NULL; +} + +static void ideapad_backlight_notify_power(struct ideapad_private *priv) +{ + unsigned long power; + struct backlight_device *blightdev = priv->blightdev; + + if (read_ec_data(ideapad_handle, 0x18, &power)) + return; + blightdev->props.power = power ? FB_BLANK_UNBLANK : FB_BLANK_POWERDOWN; +} + +static void ideapad_backlight_notify_brightness(struct ideapad_private *priv) +{ + unsigned long now; + + /* if we control brightness via acpi video driver */ + if (priv->blightdev == NULL) { + read_ec_data(ideapad_handle, 0x12, &now); + return; + } + + backlight_force_update(priv->blightdev, BACKLIGHT_UPDATE_HOTKEY); +} + +/* * module init/exit */ static const struct acpi_device_id ideapad_device_ids[] = { @@ -393,10 +522,11 @@ MODULE_DEVICE_TABLE(acpi, ideapad_device_ids); static int __devinit ideapad_acpi_add(struct acpi_device *adevice) { - int ret, i, cfg; + int ret, i; + unsigned long cfg; struct ideapad_private *priv; - if (read_method_int(adevice->handle, "_CFG", &cfg)) + if (read_method_int(adevice->handle, "_CFG", (int *)&cfg)) return -ENODEV; priv = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -404,6 +534,7 @@ static int __devinit ideapad_acpi_add(struct acpi_device *adevice) return -ENOMEM; dev_set_drvdata(&adevice->dev, priv); ideapad_handle = adevice->handle; + priv->cfg = cfg; ret = ideapad_platform_init(priv); if (ret) @@ -414,15 +545,25 @@ static int __devinit ideapad_acpi_add(struct acpi_device *adevice) goto input_failed; for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++) { - if (test_bit(ideapad_rfk_data[i].cfgbit, (unsigned long *)&cfg)) + if (test_bit(ideapad_rfk_data[i].cfgbit, &cfg)) ideapad_register_rfkill(adevice, i); else priv->rfk[i] = NULL; } ideapad_sync_rfk_state(adevice); + if (!acpi_video_backlight_support()) { + ret = ideapad_backlight_init(priv); + if (ret && ret != -ENODEV) + goto backlight_failed; + } + return 0; +backlight_failed: + for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++) + ideapad_unregister_rfkill(adevice, i); + ideapad_input_exit(priv); input_failed: ideapad_platform_exit(priv); platform_failed: @@ -435,6 +576,7 @@ static int __devexit ideapad_acpi_remove(struct acpi_device *adevice, int type) struct ideapad_private *priv = dev_get_drvdata(&adevice->dev); int i; + ideapad_backlight_exit(priv); for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++) ideapad_unregister_rfkill(adevice, i); ideapad_input_exit(priv); @@ -459,12 +601,19 @@ static void ideapad_acpi_notify(struct acpi_device *adevice, u32 event) vpc1 = (vpc2 << 8) | vpc1; for (vpc_bit = 0; vpc_bit < 16; vpc_bit++) { if (test_bit(vpc_bit, &vpc1)) { - if (vpc_bit == 9) + switch (vpc_bit) { + case 9: ideapad_sync_rfk_state(adevice); - else if (vpc_bit == 4) - read_ec_data(handle, 0x12, &vpc2); - else + break; + case 4: + ideapad_backlight_notify_brightness(priv); + break; + case 2: + ideapad_backlight_notify_power(priv); + break; + default: ideapad_input_report(priv, vpc_bit); + } } } } diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c index 5ffe7c398148..809a3ae943c6 100644 --- a/drivers/platform/x86/intel_ips.c +++ b/drivers/platform/x86/intel_ips.c @@ -403,7 +403,7 @@ static void ips_cpu_raise(struct ips_driver *ips) thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); - turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN; + turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); turbo_override &= ~TURBO_TDP_MASK; @@ -438,7 +438,7 @@ static void ips_cpu_lower(struct ips_driver *ips) thm_writew(THM_MPCPC, (new_limit * 10) / 8); - turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN; + turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); turbo_override &= ~TURBO_TDP_MASK; diff --git a/drivers/platform/x86/intel_menlow.c b/drivers/platform/x86/intel_menlow.c index 809adea4965f..abddc83e9fd7 100644 --- a/drivers/platform/x86/intel_menlow.c +++ b/drivers/platform/x86/intel_menlow.c @@ -477,6 +477,8 @@ static acpi_status intel_menlow_register_sensor(acpi_handle handle, u32 lvl, return AE_ERROR; } + return AE_OK; + aux1_not_found: if (status == AE_NOT_FOUND) return AE_OK; diff --git a/drivers/platform/x86/intel_mid_thermal.c b/drivers/platform/x86/intel_mid_thermal.c index 3a578323122b..ccd7b1f83519 100644 --- a/drivers/platform/x86/intel_mid_thermal.c +++ b/drivers/platform/x86/intel_mid_thermal.c @@ -493,20 +493,30 @@ static int mid_thermal_probe(struct platform_device *pdev) /* Register each sensor with the generic thermal framework*/ for (i = 0; i < MSIC_THERMAL_SENSORS; i++) { + struct thermal_device_info *td_info = initialize_sensor(i); + + if (!td_info) { + ret = -ENOMEM; + goto err; + } pinfo->tzd[i] = thermal_zone_device_register(name[i], - 0, initialize_sensor(i), &tzd_ops, 0, 0, 0, 0); - if (IS_ERR(pinfo->tzd[i])) - goto reg_fail; + 0, td_info, &tzd_ops, 0, 0, 0, 0); + if (IS_ERR(pinfo->tzd[i])) { + kfree(td_info); + ret = PTR_ERR(pinfo->tzd[i]); + goto err; + } } pinfo->pdev = pdev; platform_set_drvdata(pdev, pinfo); return 0; -reg_fail: - ret = PTR_ERR(pinfo->tzd[i]); - while (--i >= 0) +err: + while (--i >= 0) { + kfree(pinfo->tzd[i]->devdata); thermal_zone_device_unregister(pinfo->tzd[i]); + } configure_adc(0); kfree(pinfo); return ret; @@ -524,8 +534,10 @@ static int mid_thermal_remove(struct platform_device *pdev) int i; struct platform_info *pinfo = platform_get_drvdata(pdev); - for (i = 0; i < MSIC_THERMAL_SENSORS; i++) + for (i = 0; i < MSIC_THERMAL_SENSORS; i++) { + kfree(pinfo->tzd[i]->devdata); thermal_zone_device_unregister(pinfo->tzd[i]); + } kfree(pinfo); platform_set_drvdata(pdev, NULL); diff --git a/drivers/platform/x86/intel_rar_register.c b/drivers/platform/x86/intel_rar_register.c index bde47e9080cd..c8a6aed45277 100644 --- a/drivers/platform/x86/intel_rar_register.c +++ b/drivers/platform/x86/intel_rar_register.c @@ -637,15 +637,13 @@ end_function: return error; } -const struct pci_device_id rar_pci_id_tbl[] = { +static DEFINE_PCI_DEVICE_TABLE(rar_pci_id_tbl) = { { PCI_VDEVICE(INTEL, 0x4110) }, { 0 } }; MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); -const struct pci_device_id *my_id_table = rar_pci_id_tbl; - /* field for registering driver to PCI device */ static struct pci_driver rar_pci_driver = { .name = "rar_register_driver", diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c index 940accbe28d3..c86665369a22 100644 --- a/drivers/platform/x86/intel_scu_ipc.c +++ b/drivers/platform/x86/intel_scu_ipc.c @@ -725,7 +725,7 @@ static void ipc_remove(struct pci_dev *pdev) intel_scu_devices_destroy(); } -static const struct pci_device_id pci_ids[] = { +static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)}, {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)}, { 0,} diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index 3ff629df9f01..f204643c5052 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -538,6 +538,15 @@ static struct dmi_system_id __initdata msi_load_scm_models_dmi_table[] = { }, .callback = dmi_check_cb }, + { + .ident = "MSI U270", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, + "Micro-Star International Co., Ltd."), + DMI_MATCH(DMI_PRODUCT_NAME, "U270 series"), + }, + .callback = dmi_check_cb + }, { } }; @@ -996,3 +1005,4 @@ MODULE_ALIAS("dmi:*:svnMICRO-STARINTERNATIONAL*:pnMS-N034:*"); MODULE_ALIAS("dmi:*:svnMICRO-STARINTERNATIONAL*:pnMS-N051:*"); MODULE_ALIAS("dmi:*:svnMICRO-STARINTERNATIONAL*:pnMS-N014:*"); MODULE_ALIAS("dmi:*:svnMicro-StarInternational*:pnCR620:*"); +MODULE_ALIAS("dmi:*:svnMicro-StarInternational*:pnU270series:*"); diff --git a/drivers/platform/x86/msi-wmi.c b/drivers/platform/x86/msi-wmi.c index c832e3356cd6..6f40bf202dc7 100644 --- a/drivers/platform/x86/msi-wmi.c +++ b/drivers/platform/x86/msi-wmi.c @@ -272,6 +272,7 @@ static int __init msi_wmi_init(void) err_free_backlight: backlight_device_unregister(backlight); err_free_input: + sparse_keymap_free(msi_wmi_input_dev); input_unregister_device(msi_wmi_input_dev); err_uninstall_notifier: wmi_remove_notify_handler(MSIWMI_EVENT_GUID); diff --git a/drivers/platform/x86/samsung-laptop.c b/drivers/platform/x86/samsung-laptop.c index d347116d150e..359163011044 100644 --- a/drivers/platform/x86/samsung-laptop.c +++ b/drivers/platform/x86/samsung-laptop.c @@ -521,6 +521,16 @@ static struct dmi_system_id __initdata samsung_dmi_table[] = { .callback = dmi_check_cb, }, { + .ident = "N510", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, + "SAMSUNG ELECTRONICS CO., LTD."), + DMI_MATCH(DMI_PRODUCT_NAME, "N510"), + DMI_MATCH(DMI_BOARD_NAME, "N510"), + }, + .callback = dmi_check_cb, + }, + { .ident = "X125", .matches = { DMI_MATCH(DMI_SYS_VENDOR, @@ -601,6 +611,16 @@ static struct dmi_system_id __initdata samsung_dmi_table[] = { .callback = dmi_check_cb, }, { + .ident = "N150/N210/N220", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, + "SAMSUNG ELECTRONICS CO., LTD."), + DMI_MATCH(DMI_PRODUCT_NAME, "N150/N210/N220"), + DMI_MATCH(DMI_BOARD_NAME, "N150/N210/N220"), + }, + .callback = dmi_check_cb, + }, + { .ident = "N150/N210/N220/N230", .matches = { DMI_MATCH(DMI_SYS_VENDOR, diff --git a/drivers/platform/x86/samsung-q10.c b/drivers/platform/x86/samsung-q10.c new file mode 100644 index 000000000000..1e54ae74274c --- /dev/null +++ b/drivers/platform/x86/samsung-q10.c @@ -0,0 +1,196 @@ +/* + * Driver for Samsung Q10 and related laptops: controls the backlight + * + * Copyright (c) 2011 Frederick van der Wyck <fvanderwyck@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/backlight.h> +#include <linux/i8042.h> +#include <linux/dmi.h> + +#define SAMSUNGQ10_BL_MAX_INTENSITY 255 +#define SAMSUNGQ10_BL_DEFAULT_INTENSITY 185 + +#define SAMSUNGQ10_BL_8042_CMD 0xbe +#define SAMSUNGQ10_BL_8042_DATA { 0x89, 0x91 } + +static int samsungq10_bl_brightness; + +static bool force; +module_param(force, bool, 0); +MODULE_PARM_DESC(force, + "Disable the DMI check and force the driver to be loaded"); + +static int samsungq10_bl_set_intensity(struct backlight_device *bd) +{ + + int brightness = bd->props.brightness; + unsigned char c[3] = SAMSUNGQ10_BL_8042_DATA; + + c[2] = (unsigned char)brightness; + i8042_lock_chip(); + i8042_command(c, (0x30 << 8) | SAMSUNGQ10_BL_8042_CMD); + i8042_unlock_chip(); + samsungq10_bl_brightness = brightness; + + return 0; +} + +static int samsungq10_bl_get_intensity(struct backlight_device *bd) +{ + return samsungq10_bl_brightness; +} + +static const struct backlight_ops samsungq10_bl_ops = { + .get_brightness = samsungq10_bl_get_intensity, + .update_status = samsungq10_bl_set_intensity, +}; + +#ifdef CONFIG_PM_SLEEP +static int samsungq10_suspend(struct device *dev) +{ + return 0; +} + +static int samsungq10_resume(struct device *dev) +{ + + struct backlight_device *bd = dev_get_drvdata(dev); + + samsungq10_bl_set_intensity(bd); + return 0; +} +#else +#define samsungq10_suspend NULL +#define samsungq10_resume NULL +#endif + +static SIMPLE_DEV_PM_OPS(samsungq10_pm_ops, + samsungq10_suspend, samsungq10_resume); + +static int __devinit samsungq10_probe(struct platform_device *pdev) +{ + + struct backlight_properties props; + struct backlight_device *bd; + + memset(&props, 0, sizeof(struct backlight_properties)); + props.type = BACKLIGHT_PLATFORM; + props.max_brightness = SAMSUNGQ10_BL_MAX_INTENSITY; + bd = backlight_device_register("samsung", &pdev->dev, NULL, + &samsungq10_bl_ops, &props); + if (IS_ERR(bd)) + return PTR_ERR(bd); + + platform_set_drvdata(pdev, bd); + + bd->props.brightness = SAMSUNGQ10_BL_DEFAULT_INTENSITY; + samsungq10_bl_set_intensity(bd); + + return 0; +} + +static int __devexit samsungq10_remove(struct platform_device *pdev) +{ + + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = SAMSUNGQ10_BL_DEFAULT_INTENSITY; + samsungq10_bl_set_intensity(bd); + + backlight_device_unregister(bd); + + return 0; +} + +static struct platform_driver samsungq10_driver = { + .driver = { + .name = KBUILD_MODNAME, + .owner = THIS_MODULE, + .pm = &samsungq10_pm_ops, + }, + .probe = samsungq10_probe, + .remove = __devexit_p(samsungq10_remove), +}; + +static struct platform_device *samsungq10_device; + +static int __init dmi_check_callback(const struct dmi_system_id *id) +{ + printk(KERN_INFO KBUILD_MODNAME ": found model '%s'\n", id->ident); + return 1; +} + +static struct dmi_system_id __initdata samsungq10_dmi_table[] = { + { + .ident = "Samsung Q10", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Samsung"), + DMI_MATCH(DMI_PRODUCT_NAME, "SQ10"), + }, + .callback = dmi_check_callback, + }, + { + .ident = "Samsung Q20", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG Electronics"), + DMI_MATCH(DMI_PRODUCT_NAME, "SENS Q20"), + }, + .callback = dmi_check_callback, + }, + { + .ident = "Samsung Q25", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG Electronics"), + DMI_MATCH(DMI_PRODUCT_NAME, "NQ25"), + }, + .callback = dmi_check_callback, + }, + { + .ident = "Dell Latitude X200", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"), + DMI_MATCH(DMI_PRODUCT_NAME, "X200"), + }, + .callback = dmi_check_callback, + }, + { }, +}; +MODULE_DEVICE_TABLE(dmi, samsungq10_dmi_table); + +static int __init samsungq10_init(void) +{ + if (!force && !dmi_check_system(samsungq10_dmi_table)) + return -ENODEV; + + samsungq10_device = platform_create_bundle(&samsungq10_driver, + samsungq10_probe, + NULL, 0, NULL, 0); + + if (IS_ERR(samsungq10_device)) + return PTR_ERR(samsungq10_device); + + return 0; +} + +static void __exit samsungq10_exit(void) +{ + platform_device_unregister(samsungq10_device); + platform_driver_unregister(&samsungq10_driver); +} + +module_init(samsungq10_init); +module_exit(samsungq10_exit); + +MODULE_AUTHOR("Frederick van der Wyck <fvanderwyck@gmail.com>"); +MODULE_DESCRIPTION("Samsung Q10 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index 26c5b117df22..7bd829f247eb 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c @@ -3186,8 +3186,17 @@ static int __init hotkey_init(struct ibm_init_struct *iibm) KEY_VENDOR, /* 0x17: Thinkpad/AccessIBM/Lenovo */ /* (assignments unknown, please report if found) */ + KEY_UNKNOWN, KEY_UNKNOWN, + + /* + * The mic mute button only sends 0x1a. It does not + * automatically mute the mic or change the mute light. + */ + KEY_MICMUTE, /* 0x1a: Mic mute (since ?400 or so) */ + + /* (assignments unknown, please report if found) */ KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, - KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, + KEY_UNKNOWN, }, }; diff --git a/drivers/staging/gma500/gem_glue.c b/drivers/staging/gma500/gem_glue.c index 779ac1a12d24..daac12120653 100644 --- a/drivers/staging/gma500/gem_glue.c +++ b/drivers/staging/gma500/gem_glue.c @@ -20,26 +20,6 @@ #include <drm/drmP.h> #include <drm/drm.h> -/** - * Initialize an already allocated GEM object of the specified size with - * no GEM provided backing store. Instead the caller is responsible for - * backing the object and handling it. - */ -int drm_gem_private_object_init(struct drm_device *dev, - struct drm_gem_object *obj, size_t size) -{ - BUG_ON((size & (PAGE_SIZE - 1)) != 0); - - obj->dev = dev; - obj->filp = NULL; - - kref_init(&obj->refcount); - atomic_set(&obj->handle_count, 0); - obj->size = size; - - return 0; -} - void drm_gem_object_release_wrap(struct drm_gem_object *obj) { /* Remove the list map if one is present */ @@ -51,8 +31,7 @@ void drm_gem_object_release_wrap(struct drm_gem_object *obj) kfree(list->map); list->map = NULL; } - if (obj->filp) - drm_gem_object_release(obj); + drm_gem_object_release(obj); } /** diff --git a/drivers/staging/gma500/gem_glue.h b/drivers/staging/gma500/gem_glue.h index a0f2bc4e4ae7..ce5ce30f74db 100644 --- a/drivers/staging/gma500/gem_glue.h +++ b/drivers/staging/gma500/gem_glue.h @@ -1,4 +1,2 @@ extern void drm_gem_object_release_wrap(struct drm_gem_object *obj); -extern int drm_gem_private_object_init(struct drm_device *dev, - struct drm_gem_object *obj, size_t size); extern int gem_create_mmap_offset(struct drm_gem_object *obj); diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index d0a56235c50e..2ec57b2fb278 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1889,7 +1889,7 @@ static int __devinit sci_init_single(struct platform_device *dev, if (p->regtype == SCIx_PROBE_REGTYPE) { ret = sci_probe_regmap(p); - if (unlikely(!ret)) + if (unlikely(ret)) return ret; } diff --git a/drivers/video/savage/savagefb.h b/drivers/video/savage/savagefb.h index 32549d177b19..dcaab9012ca2 100644 --- a/drivers/video/savage/savagefb.h +++ b/drivers/video/savage/savagefb.h @@ -55,7 +55,7 @@ #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) -#define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) || (chip<=S3_PROSAVAGEDDR)) +#define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR)) #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig index f815283667af..5f7ff8e2fc14 100644 --- a/drivers/xen/Kconfig +++ b/drivers/xen/Kconfig @@ -11,7 +11,7 @@ config XEN_BALLOON config XEN_SELFBALLOONING bool "Dynamically self-balloon kernel memory to target" - depends on XEN && XEN_BALLOON && CLEANCACHE && SWAP + depends on XEN && XEN_BALLOON && CLEANCACHE && SWAP && XEN_TMEM default n help Self-ballooning dynamically balloons available kernel memory driven diff --git a/fs/autofs4/autofs_i.h b/fs/autofs4/autofs_i.h index 475f9c597cb7..326dc08d3e3f 100644 --- a/fs/autofs4/autofs_i.h +++ b/fs/autofs4/autofs_i.h @@ -39,27 +39,17 @@ /* #define DEBUG */ -#ifdef DEBUG -#define DPRINTK(fmt, args...) \ -do { \ - printk(KERN_DEBUG "pid %d: %s: " fmt "\n", \ - current->pid, __func__, ##args); \ -} while (0) -#else -#define DPRINTK(fmt, args...) do {} while (0) -#endif - -#define AUTOFS_WARN(fmt, args...) \ -do { \ +#define DPRINTK(fmt, ...) \ + pr_debug("pid %d: %s: " fmt "\n", \ + current->pid, __func__, ##__VA_ARGS__) + +#define AUTOFS_WARN(fmt, ...) \ printk(KERN_WARNING "pid %d: %s: " fmt "\n", \ - current->pid, __func__, ##args); \ -} while (0) + current->pid, __func__, ##__VA_ARGS__) -#define AUTOFS_ERROR(fmt, args...) \ -do { \ +#define AUTOFS_ERROR(fmt, ...) \ printk(KERN_ERR "pid %d: %s: " fmt "\n", \ - current->pid, __func__, ##args); \ -} while (0) + current->pid, __func__, ##__VA_ARGS__) /* Unified info structure. This is pointed to by both the dentry and inode structures. Each file in the filesystem has an instance of this diff --git a/fs/autofs4/waitq.c b/fs/autofs4/waitq.c index 25435987d6ae..e1fbdeef85db 100644 --- a/fs/autofs4/waitq.c +++ b/fs/autofs4/waitq.c @@ -104,7 +104,7 @@ static void autofs4_notify_daemon(struct autofs_sb_info *sbi, size_t pktsz; DPRINTK("wait id = 0x%08lx, name = %.*s, type=%d", - wq->wait_queue_token, wq->name.len, wq->name.name, type); + (unsigned long) wq->wait_queue_token, wq->name.len, wq->name.name, type); memset(&pkt,0,sizeof pkt); /* For security reasons */ diff --git a/fs/block_dev.c b/fs/block_dev.c index f28680553288..ff77262e887c 100644 --- a/fs/block_dev.c +++ b/fs/block_dev.c @@ -387,6 +387,10 @@ int blkdev_fsync(struct file *filp, loff_t start, loff_t end, int datasync) struct inode *bd_inode = filp->f_mapping->host; struct block_device *bdev = I_BDEV(bd_inode); int error; + + error = filemap_write_and_wait_range(filp->f_mapping, start, end); + if (error) + return error; /* * There is no need to serialise calls to blkdev_issue_flush with diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c index 8d8f28c94c0f..6873bb634a97 100644 --- a/fs/cifs/cifs_dfs_ref.c +++ b/fs/cifs/cifs_dfs_ref.c @@ -141,10 +141,11 @@ char *cifs_compose_mount_options(const char *sb_mountdata, rc = dns_resolve_server_name_to_ip(*devname, &srvIP); if (rc < 0) { - cERROR(1, "%s: Failed to resolve server part of %s to IP: %d", - __func__, *devname, rc); + cFYI(1, "%s: Failed to resolve server part of %s to IP: %d", + __func__, *devname, rc); goto compose_mount_options_err; } + /* md_len = strlen(...) + 12 for 'sep+prefixpath=' * assuming that we have 'unc=' and 'ip=' in * the original sb_mountdata diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 212e5629cc1d..f93eb948d071 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -563,6 +563,10 @@ cifs_get_root(struct smb_vol *vol, struct super_block *sb) mutex_unlock(&dir->i_mutex); dput(dentry); dentry = child; + if (!dentry->d_inode) { + dput(dentry); + dentry = ERR_PTR(-ENOENT); + } } while (!IS_ERR(dentry)); _FreeXid(xid); kfree(full_path); diff --git a/fs/cifs/dns_resolve.c b/fs/cifs/dns_resolve.c index 548f06230a6d..1d2d91d9bf65 100644 --- a/fs/cifs/dns_resolve.c +++ b/fs/cifs/dns_resolve.c @@ -79,8 +79,8 @@ dns_resolve_server_name_to_ip(const char *unc, char **ip_addr) /* Perform the upcall */ rc = dns_query(NULL, hostname, len, NULL, ip_addr, NULL); if (rc < 0) - cERROR(1, "%s: unable to resolve: %*.*s", - __func__, len, len, hostname); + cFYI(1, "%s: unable to resolve: %*.*s", + __func__, len, len, hostname); else cFYI(1, "%s: resolved: %*.*s to %s", __func__, len, len, hostname, *ip_addr); diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index 9b018c8334fa..a7b2dcd4a53e 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -764,20 +764,10 @@ char *cifs_build_path_to_root(struct smb_vol *vol, struct cifs_sb_info *cifs_sb, if (full_path == NULL) return full_path; - if (dfsplen) { + if (dfsplen) strncpy(full_path, tcon->treeName, dfsplen); - /* switch slash direction in prepath depending on whether - * windows or posix style path names - */ - if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_POSIX_PATHS) { - int i; - for (i = 0; i < dfsplen; i++) { - if (full_path[i] == '\\') - full_path[i] = '/'; - } - } - } strncpy(full_path + dfsplen, vol->prepath, pplen); + convert_delimiter(full_path, CIFS_DIR_SEP(cifs_sb)); full_path[dfsplen + pplen] = 0; /* add trailing null */ return full_path; } diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c index 243d58720513..d3e619692ee0 100644 --- a/fs/cifs/sess.c +++ b/fs/cifs/sess.c @@ -124,8 +124,7 @@ static __u32 cifs_ssetup_hdr(struct cifs_ses *ses, SESSION_SETUP_ANDX *pSMB) /* that we use in next few lines */ /* Note that header is initialized to zero in header_assemble */ pSMB->req.AndXCommand = 0xFF; - pSMB->req.MaxBufferSize = cpu_to_le16(min_t(u32, CIFSMaxBufSize - 4, - USHRT_MAX)); + pSMB->req.MaxBufferSize = cpu_to_le16(ses->server->maxBuf); pSMB->req.MaxMpxCount = cpu_to_le16(ses->server->maxReq); pSMB->req.VcNumber = get_next_vcnum(ses); diff --git a/fs/cifs/transport.c b/fs/cifs/transport.c index 147aa22c3c3a..c1b9c4b10739 100644 --- a/fs/cifs/transport.c +++ b/fs/cifs/transport.c @@ -362,6 +362,8 @@ cifs_call_async(struct TCP_Server_Info *server, struct kvec *iov, mid = AllocMidQEntry(hdr, server); if (mid == NULL) { mutex_unlock(&server->srv_mutex); + atomic_dec(&server->inFlight); + wake_up(&server->request_q); return -ENOMEM; } diff --git a/fs/dcache.c b/fs/dcache.c index c83cae19161e..a88948b8bd17 100644 --- a/fs/dcache.c +++ b/fs/dcache.c @@ -1729,7 +1729,7 @@ seqretry: */ if (read_seqcount_retry(&dentry->d_seq, *seq)) goto seqretry; - if (parent->d_flags & DCACHE_OP_COMPARE) { + if (unlikely(parent->d_flags & DCACHE_OP_COMPARE)) { if (parent->d_op->d_compare(parent, *inode, dentry, i, tlen, tname, name)) diff --git a/fs/ecryptfs/Kconfig b/fs/ecryptfs/Kconfig index 1cd6d9d3e29a..cc16562654de 100644 --- a/fs/ecryptfs/Kconfig +++ b/fs/ecryptfs/Kconfig @@ -1,6 +1,6 @@ config ECRYPT_FS tristate "eCrypt filesystem layer support (EXPERIMENTAL)" - depends on EXPERIMENTAL && KEYS && CRYPTO + depends on EXPERIMENTAL && KEYS && CRYPTO && (ENCRYPTED_KEYS || ENCRYPTED_KEYS=n) select CRYPTO_ECB select CRYPTO_CBC select CRYPTO_MD5 diff --git a/fs/ecryptfs/keystore.c b/fs/ecryptfs/keystore.c index 08a2b52bf565..ac1ad48c2376 100644 --- a/fs/ecryptfs/keystore.c +++ b/fs/ecryptfs/keystore.c @@ -1973,7 +1973,7 @@ pki_encrypt_session_key(struct key *auth_tok_key, { struct ecryptfs_msg_ctx *msg_ctx = NULL; char *payload = NULL; - size_t payload_len; + size_t payload_len = 0; struct ecryptfs_message *msg; int rc; diff --git a/fs/ecryptfs/main.c b/fs/ecryptfs/main.c index 9f1bb747d77d..b4a6befb1216 100644 --- a/fs/ecryptfs/main.c +++ b/fs/ecryptfs/main.c @@ -175,6 +175,7 @@ enum { ecryptfs_opt_sig, ecryptfs_opt_ecryptfs_sig, ecryptfs_opt_encrypted_view, ecryptfs_opt_fnek_sig, ecryptfs_opt_fn_cipher, ecryptfs_opt_fn_cipher_key_bytes, ecryptfs_opt_unlink_sigs, ecryptfs_opt_mount_auth_tok_only, + ecryptfs_opt_check_dev_ruid, ecryptfs_opt_err }; static const match_table_t tokens = { @@ -191,6 +192,7 @@ static const match_table_t tokens = { {ecryptfs_opt_fn_cipher_key_bytes, "ecryptfs_fn_key_bytes=%u"}, {ecryptfs_opt_unlink_sigs, "ecryptfs_unlink_sigs"}, {ecryptfs_opt_mount_auth_tok_only, "ecryptfs_mount_auth_tok_only"}, + {ecryptfs_opt_check_dev_ruid, "ecryptfs_check_dev_ruid"}, {ecryptfs_opt_err, NULL} }; @@ -236,6 +238,7 @@ static void ecryptfs_init_mount_crypt_stat( * ecryptfs_parse_options * @sb: The ecryptfs super block * @options: The options passed to the kernel + * @check_ruid: set to 1 if device uid should be checked against the ruid * * Parse mount options: * debug=N - ecryptfs_verbosity level for debug output @@ -251,7 +254,8 @@ static void ecryptfs_init_mount_crypt_stat( * * Returns zero on success; non-zero on error */ -static int ecryptfs_parse_options(struct ecryptfs_sb_info *sbi, char *options) +static int ecryptfs_parse_options(struct ecryptfs_sb_info *sbi, char *options, + uid_t *check_ruid) { char *p; int rc = 0; @@ -276,6 +280,8 @@ static int ecryptfs_parse_options(struct ecryptfs_sb_info *sbi, char *options) char *cipher_key_bytes_src; char *fn_cipher_key_bytes_src; + *check_ruid = 0; + if (!options) { rc = -EINVAL; goto out; @@ -380,6 +386,9 @@ static int ecryptfs_parse_options(struct ecryptfs_sb_info *sbi, char *options) mount_crypt_stat->flags |= ECRYPTFS_GLOBAL_MOUNT_AUTH_TOK_ONLY; break; + case ecryptfs_opt_check_dev_ruid: + *check_ruid = 1; + break; case ecryptfs_opt_err: default: printk(KERN_WARNING @@ -475,6 +484,7 @@ static struct dentry *ecryptfs_mount(struct file_system_type *fs_type, int flags const char *err = "Getting sb failed"; struct inode *inode; struct path path; + uid_t check_ruid; int rc; sbi = kmem_cache_zalloc(ecryptfs_sb_info_cache, GFP_KERNEL); @@ -483,7 +493,7 @@ static struct dentry *ecryptfs_mount(struct file_system_type *fs_type, int flags goto out; } - rc = ecryptfs_parse_options(sbi, raw_data); + rc = ecryptfs_parse_options(sbi, raw_data, &check_ruid); if (rc) { err = "Error parsing options"; goto out; @@ -521,6 +531,15 @@ static struct dentry *ecryptfs_mount(struct file_system_type *fs_type, int flags "known incompatibilities\n"); goto out_free; } + + if (check_ruid && path.dentry->d_inode->i_uid != current_uid()) { + rc = -EPERM; + printk(KERN_ERR "Mount of device (uid: %d) not owned by " + "requested user (uid: %d)\n", + path.dentry->d_inode->i_uid, current_uid()); + goto out_free; + } + ecryptfs_set_superblock_lower(s, path.dentry->d_sb); s->s_maxbytes = path.dentry->d_sb->s_maxbytes; s->s_blocksize = path.dentry->d_sb->s_blocksize; diff --git a/fs/ecryptfs/read_write.c b/fs/ecryptfs/read_write.c index 85d430963116..3745f7c2b9c2 100644 --- a/fs/ecryptfs/read_write.c +++ b/fs/ecryptfs/read_write.c @@ -39,15 +39,16 @@ int ecryptfs_write_lower(struct inode *ecryptfs_inode, char *data, loff_t offset, size_t size) { - struct ecryptfs_inode_info *inode_info; + struct file *lower_file; mm_segment_t fs_save; ssize_t rc; - inode_info = ecryptfs_inode_to_private(ecryptfs_inode); - BUG_ON(!inode_info->lower_file); + lower_file = ecryptfs_inode_to_private(ecryptfs_inode)->lower_file; + if (!lower_file) + return -EIO; fs_save = get_fs(); set_fs(get_ds()); - rc = vfs_write(inode_info->lower_file, data, size, &offset); + rc = vfs_write(lower_file, data, size, &offset); set_fs(fs_save); mark_inode_dirty_sync(ecryptfs_inode); return rc; @@ -225,15 +226,16 @@ out: int ecryptfs_read_lower(char *data, loff_t offset, size_t size, struct inode *ecryptfs_inode) { - struct ecryptfs_inode_info *inode_info = - ecryptfs_inode_to_private(ecryptfs_inode); + struct file *lower_file; mm_segment_t fs_save; ssize_t rc; - BUG_ON(!inode_info->lower_file); + lower_file = ecryptfs_inode_to_private(ecryptfs_inode)->lower_file; + if (!lower_file) + return -EIO; fs_save = get_fs(); set_fs(get_ds()); - rc = vfs_read(inode_info->lower_file, data, size, &offset); + rc = vfs_read(lower_file, data, size, &offset); set_fs(fs_save); return rc; } diff --git a/fs/exofs/Kbuild b/fs/exofs/Kbuild index 2d0f757fda3e..c5a5855a6c44 100644 --- a/fs/exofs/Kbuild +++ b/fs/exofs/Kbuild @@ -12,5 +12,8 @@ # Kbuild - Gets included from the Kernels Makefile and build system # -exofs-y := ios.o inode.o file.o symlink.o namei.o dir.o super.o +# ore module library +obj-$(CONFIG_ORE) += ore.o + +exofs-y := inode.o file.o symlink.o namei.o dir.o super.o obj-$(CONFIG_EXOFS_FS) += exofs.o diff --git a/fs/exofs/Kconfig b/fs/exofs/Kconfig index 86194b2f799d..70bae4149291 100644 --- a/fs/exofs/Kconfig +++ b/fs/exofs/Kconfig @@ -1,6 +1,10 @@ +config ORE + tristate + config EXOFS_FS tristate "exofs: OSD based file system support" depends on SCSI_OSD_ULD + select ORE help EXOFS is a file system that uses an OSD storage device, as its backing storage. diff --git a/fs/exofs/exofs.h b/fs/exofs/exofs.h index c965806c2821..f4e442ec7445 100644 --- a/fs/exofs/exofs.h +++ b/fs/exofs/exofs.h @@ -36,12 +36,9 @@ #include <linux/fs.h> #include <linux/time.h> #include <linux/backing-dev.h> -#include "common.h" +#include <scsi/osd_ore.h> -/* FIXME: Remove once pnfs hits mainline - * #include <linux/exportfs/pnfs_osd_xdr.h> - */ -#include "pnfs.h" +#include "common.h" #define EXOFS_ERR(fmt, a...) printk(KERN_ERR "exofs: " fmt, ##a) @@ -56,27 +53,11 @@ /* u64 has problems with printk this will cast it to unsigned long long */ #define _LLU(x) (unsigned long long)(x) -struct exofs_layout { - osd_id s_pid; /* partition ID of file system*/ - - /* Our way of looking at the data_map */ - unsigned stripe_unit; - unsigned mirrors_p1; - - unsigned group_width; - u64 group_depth; - unsigned group_count; - - enum exofs_inode_layout_gen_functions lay_func; - - unsigned s_numdevs; /* Num of devices in array */ - struct osd_dev *s_ods[0]; /* Variable length */ -}; - /* * our extension to the in-memory superblock */ struct exofs_sb_info { + struct backing_dev_info bdi; /* register our bdi with VFS */ struct exofs_sb_stats s_ess; /* Written often, pre-allocate*/ int s_timeout; /* timeout for OSD operations */ uint64_t s_nextid; /* highest object ID used */ @@ -84,16 +65,13 @@ struct exofs_sb_info { spinlock_t s_next_gen_lock; /* spinlock for gen # update */ u32 s_next_generation; /* next gen # to use */ atomic_t s_curr_pending; /* number of pending commands */ - uint8_t s_cred[OSD_CAP_LEN]; /* credential for the fscb */ - struct backing_dev_info bdi; /* register our bdi with VFS */ struct pnfs_osd_data_map data_map; /* Default raid to use * FIXME: Needed ? */ -/* struct exofs_layout dir_layout;*/ /* Default dir layout */ - struct exofs_layout layout; /* Default files layout, - * contains the variable osd_dev - * array. Keep last */ + struct ore_layout layout; /* Default files layout */ + struct ore_comp one_comp; /* id & cred of partition id=0*/ + struct ore_components comps; /* comps for the partition */ struct osd_dev *_min_one_dev[1]; /* Place holder for one dev */ }; @@ -107,7 +85,8 @@ struct exofs_i_info { uint32_t i_data[EXOFS_IDATA];/*short symlink names and device #s*/ uint32_t i_dir_start_lookup; /* which page to start lookup */ uint64_t i_commit_size; /* the object's written length */ - uint8_t i_cred[OSD_CAP_LEN];/* all-powerful credential */ + struct ore_comp one_comp; /* same component for all devices */ + struct ore_components comps; /* inode view of the device table */ }; static inline osd_id exofs_oi_objno(struct exofs_i_info *oi) @@ -115,52 +94,6 @@ static inline osd_id exofs_oi_objno(struct exofs_i_info *oi) return oi->vfs_inode.i_ino + EXOFS_OBJ_OFF; } -struct exofs_io_state; -typedef void (*exofs_io_done_fn)(struct exofs_io_state *or, void *private); - -struct exofs_io_state { - struct kref kref; - - void *private; - exofs_io_done_fn done; - - struct exofs_layout *layout; - struct osd_obj_id obj; - u8 *cred; - - /* Global read/write IO*/ - loff_t offset; - unsigned long length; - void *kern_buff; - - struct page **pages; - unsigned nr_pages; - unsigned pgbase; - unsigned pages_consumed; - - /* Attributes */ - unsigned in_attr_len; - struct osd_attr *in_attr; - unsigned out_attr_len; - struct osd_attr *out_attr; - - /* Variable array of size numdevs */ - unsigned numdevs; - struct exofs_per_dev_state { - struct osd_request *or; - struct bio *bio; - loff_t offset; - unsigned length; - unsigned dev; - } per_dev[]; -}; - -static inline unsigned exofs_io_state_size(unsigned numdevs) -{ - return sizeof(struct exofs_io_state) + - sizeof(struct exofs_per_dev_state) * numdevs; -} - /* * our inode flags */ @@ -205,12 +138,6 @@ static inline struct exofs_i_info *exofs_i(struct inode *inode) } /* - * Given a layout, object_number and stripe_index return the associated global - * dev_index - */ -unsigned exofs_layout_od_id(struct exofs_layout *layout, - osd_id obj_no, unsigned layout_index); -/* * Maximum count of links to a file */ #define EXOFS_LINK_MAX 32000 @@ -219,44 +146,8 @@ unsigned exofs_layout_od_id(struct exofs_layout *layout, * function declarations * *************************/ -/* ios.c */ -void exofs_make_credential(u8 cred_a[OSD_CAP_LEN], - const struct osd_obj_id *obj); -int exofs_read_kern(struct osd_dev *od, u8 *cred, struct osd_obj_id *obj, - u64 offset, void *p, unsigned length); - -int exofs_get_io_state(struct exofs_layout *layout, - struct exofs_io_state **ios); -void exofs_put_io_state(struct exofs_io_state *ios); - -int exofs_check_io(struct exofs_io_state *ios, u64 *resid); - -int exofs_sbi_create(struct exofs_io_state *ios); -int exofs_sbi_remove(struct exofs_io_state *ios); -int exofs_sbi_write(struct exofs_io_state *ios); -int exofs_sbi_read(struct exofs_io_state *ios); - -int extract_attr_from_ios(struct exofs_io_state *ios, struct osd_attr *attr); - -int exofs_oi_truncate(struct exofs_i_info *oi, u64 new_len); -static inline int exofs_oi_write(struct exofs_i_info *oi, - struct exofs_io_state *ios) -{ - ios->obj.id = exofs_oi_objno(oi); - ios->cred = oi->i_cred; - return exofs_sbi_write(ios); -} - -static inline int exofs_oi_read(struct exofs_i_info *oi, - struct exofs_io_state *ios) -{ - ios->obj.id = exofs_oi_objno(oi); - ios->cred = oi->i_cred; - return exofs_sbi_read(ios); -} - /* inode.c */ -unsigned exofs_max_io_pages(struct exofs_layout *layout, +unsigned exofs_max_io_pages(struct ore_layout *layout, unsigned expected_pages); int exofs_setattr(struct dentry *, struct iattr *); int exofs_write_begin(struct file *file, struct address_space *mapping, @@ -281,6 +172,8 @@ int exofs_set_link(struct inode *, struct exofs_dir_entry *, struct page *, struct inode *); /* super.c */ +void exofs_make_credential(u8 cred_a[OSD_CAP_LEN], + const struct osd_obj_id *obj); int exofs_sbi_write_stats(struct exofs_sb_info *sbi); /********************* @@ -295,7 +188,6 @@ extern const struct file_operations exofs_file_operations; /* inode.c */ extern const struct address_space_operations exofs_aops; -extern const struct osd_attr g_attr_logical_length; /* namei.c */ extern const struct inode_operations exofs_dir_inode_operations; @@ -305,4 +197,33 @@ extern const struct inode_operations exofs_special_inode_operations; extern const struct inode_operations exofs_symlink_inode_operations; extern const struct inode_operations exofs_fast_symlink_inode_operations; +/* exofs_init_comps will initialize an ore_components device array + * pointing to a single ore_comp struct, and a round-robin view + * of the device table. + * The first device of each inode is the [inode->ino % num_devices] + * and the rest of the devices sequentially following where the + * first device is after the last device. + * It is assumed that the global device array at @sbi is twice + * bigger and that the device table repeats twice. + * See: exofs_read_lookup_dev_table() + */ +static inline void exofs_init_comps(struct ore_components *comps, + struct ore_comp *one_comp, + struct exofs_sb_info *sbi, osd_id oid) +{ + unsigned dev_mod = (unsigned)oid, first_dev; + + one_comp->obj.partition = sbi->one_comp.obj.partition; + one_comp->obj.id = oid; + exofs_make_credential(one_comp->cred, &one_comp->obj); + + comps->numdevs = sbi->comps.numdevs; + comps->single_comp = EC_SINGLE_COMP; + comps->comps = one_comp; + + /* Round robin device view of the table */ + first_dev = (dev_mod * sbi->layout.mirrors_p1) % sbi->comps.numdevs; + comps->ods = sbi->comps.ods + first_dev; +} + #endif diff --git a/fs/exofs/inode.c b/fs/exofs/inode.c index 8472c098445d..f39a38fc2349 100644 --- a/fs/exofs/inode.c +++ b/fs/exofs/inode.c @@ -43,7 +43,7 @@ enum { BIO_MAX_PAGES_KMALLOC = PAGE_SIZE / sizeof(struct page *), }; -unsigned exofs_max_io_pages(struct exofs_layout *layout, +unsigned exofs_max_io_pages(struct ore_layout *layout, unsigned expected_pages) { unsigned pages = min_t(unsigned, expected_pages, MAX_PAGES_KMALLOC); @@ -58,7 +58,7 @@ struct page_collect { struct exofs_sb_info *sbi; struct inode *inode; unsigned expected_pages; - struct exofs_io_state *ios; + struct ore_io_state *ios; struct page **pages; unsigned alloc_pages; @@ -110,13 +110,6 @@ static int pcol_try_alloc(struct page_collect *pcol) { unsigned pages; - if (!pcol->ios) { /* First time allocate io_state */ - int ret = exofs_get_io_state(&pcol->sbi->layout, &pcol->ios); - - if (ret) - return ret; - } - /* TODO: easily support bio chaining */ pages = exofs_max_io_pages(&pcol->sbi->layout, pcol->expected_pages); @@ -140,7 +133,7 @@ static void pcol_free(struct page_collect *pcol) pcol->pages = NULL; if (pcol->ios) { - exofs_put_io_state(pcol->ios); + ore_put_io_state(pcol->ios); pcol->ios = NULL; } } @@ -200,7 +193,7 @@ static int __readpages_done(struct page_collect *pcol) u64 resid; u64 good_bytes; u64 length = 0; - int ret = exofs_check_io(pcol->ios, &resid); + int ret = ore_check_io(pcol->ios, &resid); if (likely(!ret)) good_bytes = pcol->length; @@ -241,7 +234,7 @@ static int __readpages_done(struct page_collect *pcol) } /* callback of async reads */ -static void readpages_done(struct exofs_io_state *ios, void *p) +static void readpages_done(struct ore_io_state *ios, void *p) { struct page_collect *pcol = p; @@ -269,20 +262,28 @@ static void _unlock_pcol_pages(struct page_collect *pcol, int ret, int rw) static int read_exec(struct page_collect *pcol) { struct exofs_i_info *oi = exofs_i(pcol->inode); - struct exofs_io_state *ios = pcol->ios; + struct ore_io_state *ios; struct page_collect *pcol_copy = NULL; int ret; if (!pcol->pages) return 0; + if (!pcol->ios) { + int ret = ore_get_rw_state(&pcol->sbi->layout, &oi->comps, true, + pcol->pg_first << PAGE_CACHE_SHIFT, + pcol->length, &pcol->ios); + + if (ret) + return ret; + } + + ios = pcol->ios; ios->pages = pcol->pages; ios->nr_pages = pcol->nr_pages; - ios->length = pcol->length; - ios->offset = pcol->pg_first << PAGE_CACHE_SHIFT; if (pcol->read_4_write) { - exofs_oi_read(oi, pcol->ios); + ore_read(pcol->ios); return __readpages_done(pcol); } @@ -295,14 +296,14 @@ static int read_exec(struct page_collect *pcol) *pcol_copy = *pcol; ios->done = readpages_done; ios->private = pcol_copy; - ret = exofs_oi_read(oi, ios); + ret = ore_read(ios); if (unlikely(ret)) goto err; atomic_inc(&pcol->sbi->s_curr_pending); EXOFS_DBGMSG2("read_exec obj=0x%llx start=0x%llx length=0x%lx\n", - ios->obj.id, _LLU(ios->offset), pcol->length); + oi->one_comp.obj.id, _LLU(ios->offset), pcol->length); /* pages ownership was passed to pcol_copy */ _pcol_reset(pcol); @@ -457,14 +458,14 @@ static int exofs_readpage(struct file *file, struct page *page) } /* Callback for osd_write. All writes are asynchronous */ -static void writepages_done(struct exofs_io_state *ios, void *p) +static void writepages_done(struct ore_io_state *ios, void *p) { struct page_collect *pcol = p; int i; u64 resid; u64 good_bytes; u64 length = 0; - int ret = exofs_check_io(ios, &resid); + int ret = ore_check_io(ios, &resid); atomic_dec(&pcol->sbi->s_curr_pending); @@ -507,13 +508,21 @@ static void writepages_done(struct exofs_io_state *ios, void *p) static int write_exec(struct page_collect *pcol) { struct exofs_i_info *oi = exofs_i(pcol->inode); - struct exofs_io_state *ios = pcol->ios; + struct ore_io_state *ios; struct page_collect *pcol_copy = NULL; int ret; if (!pcol->pages) return 0; + BUG_ON(pcol->ios); + ret = ore_get_rw_state(&pcol->sbi->layout, &oi->comps, false, + pcol->pg_first << PAGE_CACHE_SHIFT, + pcol->length, &pcol->ios); + + if (unlikely(ret)) + goto err; + pcol_copy = kmalloc(sizeof(*pcol_copy), GFP_KERNEL); if (!pcol_copy) { EXOFS_ERR("write_exec: Failed to kmalloc(pcol)\n"); @@ -523,16 +532,15 @@ static int write_exec(struct page_collect *pcol) *pcol_copy = *pcol; + ios = pcol->ios; ios->pages = pcol_copy->pages; ios->nr_pages = pcol_copy->nr_pages; - ios->offset = pcol_copy->pg_first << PAGE_CACHE_SHIFT; - ios->length = pcol_copy->length; ios->done = writepages_done; ios->private = pcol_copy; - ret = exofs_oi_write(oi, ios); + ret = ore_write(ios); if (unlikely(ret)) { - EXOFS_ERR("write_exec: exofs_oi_write() Failed\n"); + EXOFS_ERR("write_exec: ore_write() Failed\n"); goto err; } @@ -844,17 +852,15 @@ static inline int exofs_inode_is_fast_symlink(struct inode *inode) return S_ISLNK(inode->i_mode) && (oi->i_data[0] != 0); } -const struct osd_attr g_attr_logical_length = ATTR_DEF( - OSD_APAGE_OBJECT_INFORMATION, OSD_ATTR_OI_LOGICAL_LENGTH, 8); - static int _do_truncate(struct inode *inode, loff_t newsize) { struct exofs_i_info *oi = exofs_i(inode); + struct exofs_sb_info *sbi = inode->i_sb->s_fs_info; int ret; inode->i_mtime = inode->i_ctime = CURRENT_TIME; - ret = exofs_oi_truncate(oi, (u64)newsize); + ret = ore_truncate(&sbi->layout, &oi->comps, (u64)newsize); if (likely(!ret)) truncate_setsize(inode, newsize); @@ -917,30 +923,26 @@ static int exofs_get_inode(struct super_block *sb, struct exofs_i_info *oi, [1] = g_attr_inode_file_layout, [2] = g_attr_inode_dir_layout, }; - struct exofs_io_state *ios; + struct ore_io_state *ios; struct exofs_on_disk_inode_layout *layout; int ret; - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &oi->comps, &ios); if (unlikely(ret)) { - EXOFS_ERR("%s: exofs_get_io_state failed.\n", __func__); + EXOFS_ERR("%s: ore_get_io_state failed.\n", __func__); return ret; } - ios->obj.id = exofs_oi_objno(oi); - exofs_make_credential(oi->i_cred, &ios->obj); - ios->cred = oi->i_cred; - - attrs[1].len = exofs_on_disk_inode_layout_size(sbi->layout.s_numdevs); - attrs[2].len = exofs_on_disk_inode_layout_size(sbi->layout.s_numdevs); + attrs[1].len = exofs_on_disk_inode_layout_size(sbi->comps.numdevs); + attrs[2].len = exofs_on_disk_inode_layout_size(sbi->comps.numdevs); ios->in_attr = attrs; ios->in_attr_len = ARRAY_SIZE(attrs); - ret = exofs_sbi_read(ios); + ret = ore_read(ios); if (unlikely(ret)) { EXOFS_ERR("object(0x%llx) corrupted, return empty file=>%d\n", - _LLU(ios->obj.id), ret); + _LLU(oi->one_comp.obj.id), ret); memset(inode, 0, sizeof(*inode)); inode->i_mode = 0040000 | (0777 & ~022); /* If object is lost on target we might as well enable it's @@ -990,7 +992,7 @@ static int exofs_get_inode(struct super_block *sb, struct exofs_i_info *oi, } out: - exofs_put_io_state(ios); + ore_put_io_state(ios); return ret; } @@ -1016,6 +1018,8 @@ struct inode *exofs_iget(struct super_block *sb, unsigned long ino) return inode; oi = exofs_i(inode); __oi_init(oi); + exofs_init_comps(&oi->comps, &oi->one_comp, sb->s_fs_info, + exofs_oi_objno(oi)); /* read the inode from the osd */ ret = exofs_get_inode(sb, oi, &fcb); @@ -1107,21 +1111,22 @@ int __exofs_wait_obj_created(struct exofs_i_info *oi) * set the obj_created flag so that other methods know that the object exists on * the OSD. */ -static void create_done(struct exofs_io_state *ios, void *p) +static void create_done(struct ore_io_state *ios, void *p) { struct inode *inode = p; struct exofs_i_info *oi = exofs_i(inode); struct exofs_sb_info *sbi = inode->i_sb->s_fs_info; int ret; - ret = exofs_check_io(ios, NULL); - exofs_put_io_state(ios); + ret = ore_check_io(ios, NULL); + ore_put_io_state(ios); atomic_dec(&sbi->s_curr_pending); if (unlikely(ret)) { EXOFS_ERR("object=0x%llx creation failed in pid=0x%llx", - _LLU(exofs_oi_objno(oi)), _LLU(sbi->layout.s_pid)); + _LLU(exofs_oi_objno(oi)), + _LLU(oi->one_comp.obj.partition)); /*TODO: When FS is corrupted creation can fail, object already * exist. Get rid of this asynchronous creation, if exist * increment the obj counter and try the next object. Until we @@ -1140,14 +1145,13 @@ static void create_done(struct exofs_io_state *ios, void *p) */ struct inode *exofs_new_inode(struct inode *dir, int mode) { - struct super_block *sb; + struct super_block *sb = dir->i_sb; + struct exofs_sb_info *sbi = sb->s_fs_info; struct inode *inode; struct exofs_i_info *oi; - struct exofs_sb_info *sbi; - struct exofs_io_state *ios; + struct ore_io_state *ios; int ret; - sb = dir->i_sb; inode = new_inode(sb); if (!inode) return ERR_PTR(-ENOMEM); @@ -1157,8 +1161,6 @@ struct inode *exofs_new_inode(struct inode *dir, int mode) set_obj_2bcreated(oi); - sbi = sb->s_fs_info; - inode->i_mapping->backing_dev_info = sb->s_bdi; inode_init_owner(inode, dir, mode); inode->i_ino = sbi->s_nextid++; @@ -1170,25 +1172,24 @@ struct inode *exofs_new_inode(struct inode *dir, int mode) spin_unlock(&sbi->s_next_gen_lock); insert_inode_hash(inode); + exofs_init_comps(&oi->comps, &oi->one_comp, sb->s_fs_info, + exofs_oi_objno(oi)); exofs_sbi_write_stats(sbi); /* Make sure new sbi->s_nextid is on disk */ mark_inode_dirty(inode); - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &oi->comps, &ios); if (unlikely(ret)) { - EXOFS_ERR("exofs_new_inode: exofs_get_io_state failed\n"); + EXOFS_ERR("exofs_new_inode: ore_get_io_state failed\n"); return ERR_PTR(ret); } - ios->obj.id = exofs_oi_objno(oi); - exofs_make_credential(oi->i_cred, &ios->obj); - ios->done = create_done; ios->private = inode; - ios->cred = oi->i_cred; - ret = exofs_sbi_create(ios); + + ret = ore_create(ios); if (ret) { - exofs_put_io_state(ios); + ore_put_io_state(ios); return ERR_PTR(ret); } atomic_inc(&sbi->s_curr_pending); @@ -1207,11 +1208,11 @@ struct updatei_args { /* * Callback function from exofs_update_inode(). */ -static void updatei_done(struct exofs_io_state *ios, void *p) +static void updatei_done(struct ore_io_state *ios, void *p) { struct updatei_args *args = p; - exofs_put_io_state(ios); + ore_put_io_state(ios); atomic_dec(&args->sbi->s_curr_pending); @@ -1227,7 +1228,7 @@ static int exofs_update_inode(struct inode *inode, int do_sync) struct exofs_i_info *oi = exofs_i(inode); struct super_block *sb = inode->i_sb; struct exofs_sb_info *sbi = sb->s_fs_info; - struct exofs_io_state *ios; + struct ore_io_state *ios; struct osd_attr attr; struct exofs_fcb *fcb; struct updatei_args *args; @@ -1266,9 +1267,9 @@ static int exofs_update_inode(struct inode *inode, int do_sync) } else memcpy(fcb->i_data, oi->i_data, sizeof(fcb->i_data)); - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &oi->comps, &ios); if (unlikely(ret)) { - EXOFS_ERR("%s: exofs_get_io_state failed.\n", __func__); + EXOFS_ERR("%s: ore_get_io_state failed.\n", __func__); goto free_args; } @@ -1285,13 +1286,13 @@ static int exofs_update_inode(struct inode *inode, int do_sync) ios->private = args; } - ret = exofs_oi_write(oi, ios); + ret = ore_write(ios); if (!do_sync && !ret) { atomic_inc(&sbi->s_curr_pending); goto out; /* deallocation in updatei_done */ } - exofs_put_io_state(ios); + ore_put_io_state(ios); free_args: kfree(args); out: @@ -1310,11 +1311,11 @@ int exofs_write_inode(struct inode *inode, struct writeback_control *wbc) * Callback function from exofs_delete_inode() - don't have much cleaning up to * do. */ -static void delete_done(struct exofs_io_state *ios, void *p) +static void delete_done(struct ore_io_state *ios, void *p) { struct exofs_sb_info *sbi = p; - exofs_put_io_state(ios); + ore_put_io_state(ios); atomic_dec(&sbi->s_curr_pending); } @@ -1329,7 +1330,7 @@ void exofs_evict_inode(struct inode *inode) struct exofs_i_info *oi = exofs_i(inode); struct super_block *sb = inode->i_sb; struct exofs_sb_info *sbi = sb->s_fs_info; - struct exofs_io_state *ios; + struct ore_io_state *ios; int ret; truncate_inode_pages(&inode->i_data, 0); @@ -1349,20 +1350,19 @@ void exofs_evict_inode(struct inode *inode) /* ignore the error, attempt a remove anyway */ /* Now Remove the OSD objects */ - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &oi->comps, &ios); if (unlikely(ret)) { - EXOFS_ERR("%s: exofs_get_io_state failed\n", __func__); + EXOFS_ERR("%s: ore_get_io_state failed\n", __func__); return; } - ios->obj.id = exofs_oi_objno(oi); ios->done = delete_done; ios->private = sbi; - ios->cred = oi->i_cred; - ret = exofs_sbi_remove(ios); + + ret = ore_remove(ios); if (ret) { - EXOFS_ERR("%s: exofs_sbi_remove failed\n", __func__); - exofs_put_io_state(ios); + EXOFS_ERR("%s: ore_remove failed\n", __func__); + ore_put_io_state(ios); return; } atomic_inc(&sbi->s_curr_pending); diff --git a/fs/exofs/ios.c b/fs/exofs/ore.c index f74a2ec027a6..25305af88198 100644 --- a/fs/exofs/ios.c +++ b/fs/exofs/ore.c @@ -23,81 +23,87 @@ */ #include <linux/slab.h> -#include <scsi/scsi_device.h> #include <asm/div64.h> -#include "exofs.h" +#include <scsi/osd_ore.h> -#define EXOFS_DBGMSG2(M...) do {} while (0) -/* #define EXOFS_DBGMSG2 EXOFS_DBGMSG */ +#define ORE_ERR(fmt, a...) printk(KERN_ERR "ore: " fmt, ##a) -void exofs_make_credential(u8 cred_a[OSD_CAP_LEN], const struct osd_obj_id *obj) -{ - osd_sec_init_nosec_doall_caps(cred_a, obj, false, true); -} +#ifdef CONFIG_EXOFS_DEBUG +#define ORE_DBGMSG(fmt, a...) \ + printk(KERN_NOTICE "ore @%s:%d: " fmt, __func__, __LINE__, ##a) +#else +#define ORE_DBGMSG(fmt, a...) \ + do { if (0) printk(fmt, ##a); } while (0) +#endif -int exofs_read_kern(struct osd_dev *od, u8 *cred, struct osd_obj_id *obj, - u64 offset, void *p, unsigned length) -{ - struct osd_request *or = osd_start_request(od, GFP_KERNEL); -/* struct osd_sense_info osi = {.key = 0};*/ - int ret; +/* u64 has problems with printk this will cast it to unsigned long long */ +#define _LLU(x) (unsigned long long)(x) - if (unlikely(!or)) { - EXOFS_DBGMSG("%s: osd_start_request failed.\n", __func__); - return -ENOMEM; - } - ret = osd_req_read_kern(or, obj, offset, p, length); - if (unlikely(ret)) { - EXOFS_DBGMSG("%s: osd_req_read_kern failed.\n", __func__); - goto out; - } +#define ORE_DBGMSG2(M...) do {} while (0) +/* #define ORE_DBGMSG2 ORE_DBGMSG */ - ret = osd_finalize_request(or, 0, cred, NULL); - if (unlikely(ret)) { - EXOFS_DBGMSG("Failed to osd_finalize_request() => %d\n", ret); - goto out; - } +MODULE_AUTHOR("Boaz Harrosh <bharrosh@panasas.com>"); +MODULE_DESCRIPTION("Objects Raid Engine ore.ko"); +MODULE_LICENSE("GPL"); - ret = osd_execute_request(or); - if (unlikely(ret)) - EXOFS_DBGMSG("osd_execute_request() => %d\n", ret); - /* osd_req_decode_sense(or, ret); */ +static u8 *_ios_cred(struct ore_io_state *ios, unsigned index) +{ + return ios->comps->comps[index & ios->comps->single_comp].cred; +} -out: - osd_end_request(or); - return ret; +static struct osd_obj_id *_ios_obj(struct ore_io_state *ios, unsigned index) +{ + return &ios->comps->comps[index & ios->comps->single_comp].obj; } -int exofs_get_io_state(struct exofs_layout *layout, - struct exofs_io_state **pios) +static struct osd_dev *_ios_od(struct ore_io_state *ios, unsigned index) { - struct exofs_io_state *ios; + return ios->comps->ods[index]; +} + +int ore_get_rw_state(struct ore_layout *layout, struct ore_components *comps, + bool is_reading, u64 offset, u64 length, + struct ore_io_state **pios) +{ + struct ore_io_state *ios; /*TODO: Maybe use kmem_cach per sbi of size * exofs_io_state_size(layout->s_numdevs) */ - ios = kzalloc(exofs_io_state_size(layout->s_numdevs), GFP_KERNEL); + ios = kzalloc(ore_io_state_size(comps->numdevs), GFP_KERNEL); if (unlikely(!ios)) { - EXOFS_DBGMSG("Failed kzalloc bytes=%d\n", - exofs_io_state_size(layout->s_numdevs)); + ORE_DBGMSG("Failed kzalloc bytes=%d\n", + ore_io_state_size(comps->numdevs)); *pios = NULL; return -ENOMEM; } ios->layout = layout; - ios->obj.partition = layout->s_pid; + ios->comps = comps; + ios->offset = offset; + ios->length = length; + ios->reading = is_reading; + *pios = ios; return 0; } +EXPORT_SYMBOL(ore_get_rw_state); + +int ore_get_io_state(struct ore_layout *layout, struct ore_components *comps, + struct ore_io_state **ios) +{ + return ore_get_rw_state(layout, comps, true, 0, 0, ios); +} +EXPORT_SYMBOL(ore_get_io_state); -void exofs_put_io_state(struct exofs_io_state *ios) +void ore_put_io_state(struct ore_io_state *ios) { if (ios) { unsigned i; for (i = 0; i < ios->numdevs; i++) { - struct exofs_per_dev_state *per_dev = &ios->per_dev[i]; + struct ore_per_dev_state *per_dev = &ios->per_dev[i]; if (per_dev->or) osd_end_request(per_dev->or); @@ -108,31 +114,9 @@ void exofs_put_io_state(struct exofs_io_state *ios) kfree(ios); } } +EXPORT_SYMBOL(ore_put_io_state); -unsigned exofs_layout_od_id(struct exofs_layout *layout, - osd_id obj_no, unsigned layout_index) -{ -/* switch (layout->lay_func) { - case LAYOUT_MOVING_WINDOW: - {*/ - unsigned dev_mod = obj_no; - - return (layout_index + dev_mod * layout->mirrors_p1) % - layout->s_numdevs; -/* } - case LAYOUT_FUNC_IMPLICT: - return layout->devs[layout_index]; - }*/ -} - -static inline struct osd_dev *exofs_ios_od(struct exofs_io_state *ios, - unsigned layout_index) -{ - return ios->layout->s_ods[ - exofs_layout_od_id(ios->layout, ios->obj.id, layout_index)]; -} - -static void _sync_done(struct exofs_io_state *ios, void *p) +static void _sync_done(struct ore_io_state *ios, void *p) { struct completion *waiting = p; @@ -141,20 +125,20 @@ static void _sync_done(struct exofs_io_state *ios, void *p) static void _last_io(struct kref *kref) { - struct exofs_io_state *ios = container_of( - kref, struct exofs_io_state, kref); + struct ore_io_state *ios = container_of( + kref, struct ore_io_state, kref); ios->done(ios, ios->private); } static void _done_io(struct osd_request *or, void *p) { - struct exofs_io_state *ios = p; + struct ore_io_state *ios = p; kref_put(&ios->kref, _last_io); } -static int exofs_io_execute(struct exofs_io_state *ios) +static int ore_io_execute(struct ore_io_state *ios) { DECLARE_COMPLETION_ONSTACK(wait); bool sync = (ios->done == NULL); @@ -170,9 +154,9 @@ static int exofs_io_execute(struct exofs_io_state *ios) if (unlikely(!or)) continue; - ret = osd_finalize_request(or, 0, ios->cred, NULL); + ret = osd_finalize_request(or, 0, _ios_cred(ios, i), NULL); if (unlikely(ret)) { - EXOFS_DBGMSG("Failed to osd_finalize_request() => %d\n", + ORE_DBGMSG("Failed to osd_finalize_request() => %d\n", ret); return ret; } @@ -194,7 +178,7 @@ static int exofs_io_execute(struct exofs_io_state *ios) if (sync) { wait_for_completion(&wait); - ret = exofs_check_io(ios, NULL); + ret = ore_check_io(ios, NULL); } return ret; } @@ -214,7 +198,7 @@ static void _clear_bio(struct bio *bio) } } -int exofs_check_io(struct exofs_io_state *ios, u64 *resid) +int ore_check_io(struct ore_io_state *ios, u64 *resid) { enum osd_err_priority acumulated_osd_err = 0; int acumulated_lin_err = 0; @@ -235,7 +219,7 @@ int exofs_check_io(struct exofs_io_state *ios, u64 *resid) if (OSD_ERR_PRI_CLEAR_PAGES == osi.osd_err_pri) { /* start read offset passed endof file */ _clear_bio(ios->per_dev[i].bio); - EXOFS_DBGMSG("start read offset passed end of file " + ORE_DBGMSG("start read offset passed end of file " "offset=0x%llx, length=0x%llx\n", _LLU(ios->per_dev[i].offset), _LLU(ios->per_dev[i].length)); @@ -259,6 +243,7 @@ int exofs_check_io(struct exofs_io_state *ios, u64 *resid) return acumulated_lin_err; } +EXPORT_SYMBOL(ore_check_io); /* * L - logical offset into the file @@ -305,20 +290,21 @@ int exofs_check_io(struct exofs_io_state *ios, u64 *resid) struct _striping_info { u64 obj_offset; u64 group_length; + u64 M; /* for truncate */ unsigned dev; unsigned unit_off; }; -static void _calc_stripe_info(struct exofs_io_state *ios, u64 file_offset, +static void _calc_stripe_info(struct ore_layout *layout, u64 file_offset, struct _striping_info *si) { - u32 stripe_unit = ios->layout->stripe_unit; - u32 group_width = ios->layout->group_width; - u64 group_depth = ios->layout->group_depth; + u32 stripe_unit = layout->stripe_unit; + u32 group_width = layout->group_width; + u64 group_depth = layout->group_depth; u32 U = stripe_unit * group_width; u64 T = U * group_depth; - u64 S = T * ios->layout->group_count; + u64 S = T * layout->group_count; u64 M = div64_u64(file_offset, S); /* @@ -333,7 +319,7 @@ static void _calc_stripe_info(struct exofs_io_state *ios, u64 file_offset, /* "H - (N * U)" is just "H % U" so it's bound to u32 */ si->dev = (u32)(H - (N * U)) / stripe_unit + G * group_width; - si->dev *= ios->layout->mirrors_p1; + si->dev *= layout->mirrors_p1; div_u64_rem(file_offset, stripe_unit, &si->unit_off); @@ -341,15 +327,16 @@ static void _calc_stripe_info(struct exofs_io_state *ios, u64 file_offset, (M * group_depth * stripe_unit); si->group_length = T - H; + si->M = M; } -static int _add_stripe_unit(struct exofs_io_state *ios, unsigned *cur_pg, - unsigned pgbase, struct exofs_per_dev_state *per_dev, +static int _add_stripe_unit(struct ore_io_state *ios, unsigned *cur_pg, + unsigned pgbase, struct ore_per_dev_state *per_dev, int cur_len) { unsigned pg = *cur_pg; struct request_queue *q = - osd_request_queue(exofs_ios_od(ios, per_dev->dev)); + osd_request_queue(_ios_od(ios, per_dev->dev)); per_dev->length += cur_len; @@ -361,7 +348,7 @@ static int _add_stripe_unit(struct exofs_io_state *ios, unsigned *cur_pg, per_dev->bio = bio_kmalloc(GFP_KERNEL, bio_size); if (unlikely(!per_dev->bio)) { - EXOFS_DBGMSG("Failed to allocate BIO size=%u\n", + ORE_DBGMSG("Failed to allocate BIO size=%u\n", bio_size); return -ENOMEM; } @@ -387,7 +374,7 @@ static int _add_stripe_unit(struct exofs_io_state *ios, unsigned *cur_pg, return 0; } -static int _prepare_one_group(struct exofs_io_state *ios, u64 length, +static int _prepare_one_group(struct ore_io_state *ios, u64 length, struct _striping_info *si) { unsigned stripe_unit = ios->layout->stripe_unit; @@ -400,7 +387,7 @@ static int _prepare_one_group(struct exofs_io_state *ios, u64 length, int ret = 0; while (length) { - struct exofs_per_dev_state *per_dev = &ios->per_dev[dev]; + struct ore_per_dev_state *per_dev = &ios->per_dev[dev]; unsigned cur_len, page_off = 0; if (!per_dev->length) { @@ -443,7 +430,7 @@ out: return ret; } -static int _prepare_for_striping(struct exofs_io_state *ios) +static int _prepare_for_striping(struct ore_io_state *ios) { u64 length = ios->length; u64 offset = ios->offset; @@ -452,9 +439,9 @@ static int _prepare_for_striping(struct exofs_io_state *ios) if (!ios->pages) { if (ios->kern_buff) { - struct exofs_per_dev_state *per_dev = &ios->per_dev[0]; + struct ore_per_dev_state *per_dev = &ios->per_dev[0]; - _calc_stripe_info(ios, ios->offset, &si); + _calc_stripe_info(ios->layout, ios->offset, &si); per_dev->offset = si.obj_offset; per_dev->dev = si.dev; @@ -468,7 +455,7 @@ static int _prepare_for_striping(struct exofs_io_state *ios) } while (length) { - _calc_stripe_info(ios, offset, &si); + _calc_stripe_info(ios->layout, offset, &si); if (length < si.group_length) si.group_length = length; @@ -485,57 +472,59 @@ out: return ret; } -int exofs_sbi_create(struct exofs_io_state *ios) +int ore_create(struct ore_io_state *ios) { int i, ret; - for (i = 0; i < ios->layout->s_numdevs; i++) { + for (i = 0; i < ios->comps->numdevs; i++) { struct osd_request *or; - or = osd_start_request(exofs_ios_od(ios, i), GFP_KERNEL); + or = osd_start_request(_ios_od(ios, i), GFP_KERNEL); if (unlikely(!or)) { - EXOFS_ERR("%s: osd_start_request failed\n", __func__); + ORE_ERR("%s: osd_start_request failed\n", __func__); ret = -ENOMEM; goto out; } ios->per_dev[i].or = or; ios->numdevs++; - osd_req_create_object(or, &ios->obj); + osd_req_create_object(or, _ios_obj(ios, i)); } - ret = exofs_io_execute(ios); + ret = ore_io_execute(ios); out: return ret; } +EXPORT_SYMBOL(ore_create); -int exofs_sbi_remove(struct exofs_io_state *ios) +int ore_remove(struct ore_io_state *ios) { int i, ret; - for (i = 0; i < ios->layout->s_numdevs; i++) { + for (i = 0; i < ios->comps->numdevs; i++) { struct osd_request *or; - or = osd_start_request(exofs_ios_od(ios, i), GFP_KERNEL); + or = osd_start_request(_ios_od(ios, i), GFP_KERNEL); if (unlikely(!or)) { - EXOFS_ERR("%s: osd_start_request failed\n", __func__); + ORE_ERR("%s: osd_start_request failed\n", __func__); ret = -ENOMEM; goto out; } ios->per_dev[i].or = or; ios->numdevs++; - osd_req_remove_object(or, &ios->obj); + osd_req_remove_object(or, _ios_obj(ios, i)); } - ret = exofs_io_execute(ios); + ret = ore_io_execute(ios); out: return ret; } +EXPORT_SYMBOL(ore_remove); -static int _sbi_write_mirror(struct exofs_io_state *ios, int cur_comp) +static int _write_mirror(struct ore_io_state *ios, int cur_comp) { - struct exofs_per_dev_state *master_dev = &ios->per_dev[cur_comp]; + struct ore_per_dev_state *master_dev = &ios->per_dev[cur_comp]; unsigned dev = ios->per_dev[cur_comp].dev; unsigned last_comp = cur_comp + ios->layout->mirrors_p1; int ret = 0; @@ -544,12 +533,12 @@ static int _sbi_write_mirror(struct exofs_io_state *ios, int cur_comp) return 0; /* Just an empty slot */ for (; cur_comp < last_comp; ++cur_comp, ++dev) { - struct exofs_per_dev_state *per_dev = &ios->per_dev[cur_comp]; + struct ore_per_dev_state *per_dev = &ios->per_dev[cur_comp]; struct osd_request *or; - or = osd_start_request(exofs_ios_od(ios, dev), GFP_KERNEL); + or = osd_start_request(_ios_od(ios, dev), GFP_KERNEL); if (unlikely(!or)) { - EXOFS_ERR("%s: osd_start_request failed\n", __func__); + ORE_ERR("%s: osd_start_request failed\n", __func__); ret = -ENOMEM; goto out; } @@ -563,7 +552,7 @@ static int _sbi_write_mirror(struct exofs_io_state *ios, int cur_comp) bio = bio_kmalloc(GFP_KERNEL, master_dev->bio->bi_max_vecs); if (unlikely(!bio)) { - EXOFS_DBGMSG( + ORE_DBGMSG( "Failed to allocate BIO size=%u\n", master_dev->bio->bi_max_vecs); ret = -ENOMEM; @@ -582,25 +571,29 @@ static int _sbi_write_mirror(struct exofs_io_state *ios, int cur_comp) bio->bi_rw |= REQ_WRITE; } - osd_req_write(or, &ios->obj, per_dev->offset, bio, - per_dev->length); - EXOFS_DBGMSG("write(0x%llx) offset=0x%llx " + osd_req_write(or, _ios_obj(ios, dev), per_dev->offset, + bio, per_dev->length); + ORE_DBGMSG("write(0x%llx) offset=0x%llx " "length=0x%llx dev=%d\n", - _LLU(ios->obj.id), _LLU(per_dev->offset), + _LLU(_ios_obj(ios, dev)->id), + _LLU(per_dev->offset), _LLU(per_dev->length), dev); } else if (ios->kern_buff) { - ret = osd_req_write_kern(or, &ios->obj, per_dev->offset, - ios->kern_buff, ios->length); + ret = osd_req_write_kern(or, _ios_obj(ios, dev), + per_dev->offset, + ios->kern_buff, ios->length); if (unlikely(ret)) goto out; - EXOFS_DBGMSG2("write_kern(0x%llx) offset=0x%llx " + ORE_DBGMSG2("write_kern(0x%llx) offset=0x%llx " "length=0x%llx dev=%d\n", - _LLU(ios->obj.id), _LLU(per_dev->offset), + _LLU(_ios_obj(ios, dev)->id), + _LLU(per_dev->offset), _LLU(ios->length), dev); } else { - osd_req_set_attributes(or, &ios->obj); - EXOFS_DBGMSG2("obj(0x%llx) set_attributes=%d dev=%d\n", - _LLU(ios->obj.id), ios->out_attr_len, dev); + osd_req_set_attributes(or, _ios_obj(ios, dev)); + ORE_DBGMSG2("obj(0x%llx) set_attributes=%d dev=%d\n", + _LLU(_ios_obj(ios, dev)->id), + ios->out_attr_len, dev); } if (ios->out_attr) @@ -616,7 +609,7 @@ out: return ret; } -int exofs_sbi_write(struct exofs_io_state *ios) +int ore_write(struct ore_io_state *ios) { int i; int ret; @@ -626,52 +619,55 @@ int exofs_sbi_write(struct exofs_io_state *ios) return ret; for (i = 0; i < ios->numdevs; i += ios->layout->mirrors_p1) { - ret = _sbi_write_mirror(ios, i); + ret = _write_mirror(ios, i); if (unlikely(ret)) return ret; } - ret = exofs_io_execute(ios); + ret = ore_io_execute(ios); return ret; } +EXPORT_SYMBOL(ore_write); -static int _sbi_read_mirror(struct exofs_io_state *ios, unsigned cur_comp) +static int _read_mirror(struct ore_io_state *ios, unsigned cur_comp) { struct osd_request *or; - struct exofs_per_dev_state *per_dev = &ios->per_dev[cur_comp]; - unsigned first_dev = (unsigned)ios->obj.id; + struct ore_per_dev_state *per_dev = &ios->per_dev[cur_comp]; + struct osd_obj_id *obj = _ios_obj(ios, cur_comp); + unsigned first_dev = (unsigned)obj->id; if (ios->pages && !per_dev->length) return 0; /* Just an empty slot */ first_dev = per_dev->dev + first_dev % ios->layout->mirrors_p1; - or = osd_start_request(exofs_ios_od(ios, first_dev), GFP_KERNEL); + or = osd_start_request(_ios_od(ios, first_dev), GFP_KERNEL); if (unlikely(!or)) { - EXOFS_ERR("%s: osd_start_request failed\n", __func__); + ORE_ERR("%s: osd_start_request failed\n", __func__); return -ENOMEM; } per_dev->or = or; if (ios->pages) { - osd_req_read(or, &ios->obj, per_dev->offset, + osd_req_read(or, obj, per_dev->offset, per_dev->bio, per_dev->length); - EXOFS_DBGMSG("read(0x%llx) offset=0x%llx length=0x%llx" - " dev=%d\n", _LLU(ios->obj.id), + ORE_DBGMSG("read(0x%llx) offset=0x%llx length=0x%llx" + " dev=%d\n", _LLU(obj->id), _LLU(per_dev->offset), _LLU(per_dev->length), first_dev); } else if (ios->kern_buff) { - int ret = osd_req_read_kern(or, &ios->obj, per_dev->offset, + int ret = osd_req_read_kern(or, obj, per_dev->offset, ios->kern_buff, ios->length); - EXOFS_DBGMSG2("read_kern(0x%llx) offset=0x%llx " + ORE_DBGMSG2("read_kern(0x%llx) offset=0x%llx " "length=0x%llx dev=%d ret=>%d\n", - _LLU(ios->obj.id), _LLU(per_dev->offset), + _LLU(obj->id), _LLU(per_dev->offset), _LLU(ios->length), first_dev, ret); if (unlikely(ret)) return ret; } else { - osd_req_get_attributes(or, &ios->obj); - EXOFS_DBGMSG2("obj(0x%llx) get_attributes=%d dev=%d\n", - _LLU(ios->obj.id), ios->in_attr_len, first_dev); + osd_req_get_attributes(or, obj); + ORE_DBGMSG2("obj(0x%llx) get_attributes=%d dev=%d\n", + _LLU(obj->id), + ios->in_attr_len, first_dev); } if (ios->out_attr) osd_req_add_set_attr_list(or, ios->out_attr, ios->out_attr_len); @@ -682,7 +678,7 @@ static int _sbi_read_mirror(struct exofs_io_state *ios, unsigned cur_comp) return 0; } -int exofs_sbi_read(struct exofs_io_state *ios) +int ore_read(struct ore_io_state *ios) { int i; int ret; @@ -692,16 +688,17 @@ int exofs_sbi_read(struct exofs_io_state *ios) return ret; for (i = 0; i < ios->numdevs; i += ios->layout->mirrors_p1) { - ret = _sbi_read_mirror(ios, i); + ret = _read_mirror(ios, i); if (unlikely(ret)) return ret; } - ret = exofs_io_execute(ios); + ret = ore_io_execute(ios); return ret; } +EXPORT_SYMBOL(ore_read); -int extract_attr_from_ios(struct exofs_io_state *ios, struct osd_attr *attr) +int extract_attr_from_ios(struct ore_io_state *ios, struct osd_attr *attr) { struct osd_attr cur_attr = {.attr_page = 0}; /* start with zeros */ void *iter = NULL; @@ -721,83 +718,118 @@ int extract_attr_from_ios(struct exofs_io_state *ios, struct osd_attr *attr) return -EIO; } +EXPORT_SYMBOL(extract_attr_from_ios); -static int _truncate_mirrors(struct exofs_io_state *ios, unsigned cur_comp, +static int _truncate_mirrors(struct ore_io_state *ios, unsigned cur_comp, struct osd_attr *attr) { int last_comp = cur_comp + ios->layout->mirrors_p1; for (; cur_comp < last_comp; ++cur_comp) { - struct exofs_per_dev_state *per_dev = &ios->per_dev[cur_comp]; + struct ore_per_dev_state *per_dev = &ios->per_dev[cur_comp]; struct osd_request *or; - or = osd_start_request(exofs_ios_od(ios, cur_comp), GFP_KERNEL); + or = osd_start_request(_ios_od(ios, cur_comp), GFP_KERNEL); if (unlikely(!or)) { - EXOFS_ERR("%s: osd_start_request failed\n", __func__); + ORE_ERR("%s: osd_start_request failed\n", __func__); return -ENOMEM; } per_dev->or = or; - osd_req_set_attributes(or, &ios->obj); + osd_req_set_attributes(or, _ios_obj(ios, cur_comp)); osd_req_add_set_attr_list(or, attr, 1); } return 0; } -int exofs_oi_truncate(struct exofs_i_info *oi, u64 size) +struct _trunc_info { + struct _striping_info si; + u64 prev_group_obj_off; + u64 next_group_obj_off; + + unsigned first_group_dev; + unsigned nex_group_dev; + unsigned max_devs; +}; + +void _calc_trunk_info(struct ore_layout *layout, u64 file_offset, + struct _trunc_info *ti) +{ + unsigned stripe_unit = layout->stripe_unit; + + _calc_stripe_info(layout, file_offset, &ti->si); + + ti->prev_group_obj_off = ti->si.M * stripe_unit; + ti->next_group_obj_off = ti->si.M ? (ti->si.M - 1) * stripe_unit : 0; + + ti->first_group_dev = ti->si.dev - (ti->si.dev % layout->group_width); + ti->nex_group_dev = ti->first_group_dev + layout->group_width; + ti->max_devs = layout->group_width * layout->group_count; +} + +int ore_truncate(struct ore_layout *layout, struct ore_components *comps, + u64 size) { - struct exofs_sb_info *sbi = oi->vfs_inode.i_sb->s_fs_info; - struct exofs_io_state *ios; + struct ore_io_state *ios; struct exofs_trunc_attr { struct osd_attr attr; __be64 newsize; } *size_attrs; - struct _striping_info si; + struct _trunc_info ti; int i, ret; - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(layout, comps, &ios); if (unlikely(ret)) return ret; - size_attrs = kcalloc(ios->layout->group_width, sizeof(*size_attrs), + _calc_trunk_info(ios->layout, size, &ti); + + size_attrs = kcalloc(ti.max_devs, sizeof(*size_attrs), GFP_KERNEL); if (unlikely(!size_attrs)) { ret = -ENOMEM; goto out; } - ios->obj.id = exofs_oi_objno(oi); - ios->cred = oi->i_cred; + ios->numdevs = ios->comps->numdevs; - ios->numdevs = ios->layout->s_numdevs; - _calc_stripe_info(ios, size, &si); - - for (i = 0; i < ios->layout->group_width; ++i) { + for (i = 0; i < ti.max_devs; ++i) { struct exofs_trunc_attr *size_attr = &size_attrs[i]; u64 obj_size; - if (i < si.dev) - obj_size = si.obj_offset + - ios->layout->stripe_unit - si.unit_off; - else if (i == si.dev) - obj_size = si.obj_offset; - else /* i > si.dev */ - obj_size = si.obj_offset - si.unit_off; + if (i < ti.first_group_dev) + obj_size = ti.prev_group_obj_off; + else if (i >= ti.nex_group_dev) + obj_size = ti.next_group_obj_off; + else if (i < ti.si.dev) /* dev within this group */ + obj_size = ti.si.obj_offset + + ios->layout->stripe_unit - ti.si.unit_off; + else if (i == ti.si.dev) + obj_size = ti.si.obj_offset; + else /* i > ti.dev */ + obj_size = ti.si.obj_offset - ti.si.unit_off; size_attr->newsize = cpu_to_be64(obj_size); size_attr->attr = g_attr_logical_length; size_attr->attr.val_ptr = &size_attr->newsize; + ORE_DBGMSG("trunc(0x%llx) obj_offset=0x%llx dev=%d\n", + _LLU(comps->comps->obj.id), _LLU(obj_size), i); ret = _truncate_mirrors(ios, i * ios->layout->mirrors_p1, &size_attr->attr); if (unlikely(ret)) goto out; } - ret = exofs_io_execute(ios); + ret = ore_io_execute(ios); out: kfree(size_attrs); - exofs_put_io_state(ios); + ore_put_io_state(ios); return ret; } +EXPORT_SYMBOL(ore_truncate); + +const struct osd_attr g_attr_logical_length = ATTR_DEF( + OSD_APAGE_OBJECT_INFORMATION, OSD_ATTR_OI_LOGICAL_LENGTH, 8); +EXPORT_SYMBOL(g_attr_logical_length); diff --git a/fs/exofs/pnfs.h b/fs/exofs/pnfs.h deleted file mode 100644 index c52e9888b8ab..000000000000 --- a/fs/exofs/pnfs.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2008, 2009 - * Boaz Harrosh <bharrosh@panasas.com> - * - * This file is part of exofs. - * - * exofs is free software; you can redistribute it and/or modify it under the - * terms of the GNU General Public License version 2 as published by the Free - * Software Foundation. - * - */ - -/* FIXME: Remove this file once pnfs hits mainline */ - -#ifndef __EXOFS_PNFS_H__ -#define __EXOFS_PNFS_H__ - -#if ! defined(__PNFS_OSD_XDR_H__) - -enum pnfs_iomode { - IOMODE_READ = 1, - IOMODE_RW = 2, - IOMODE_ANY = 3, -}; - -/* Layout Structure */ -enum pnfs_osd_raid_algorithm4 { - PNFS_OSD_RAID_0 = 1, - PNFS_OSD_RAID_4 = 2, - PNFS_OSD_RAID_5 = 3, - PNFS_OSD_RAID_PQ = 4 /* Reed-Solomon P+Q */ -}; - -struct pnfs_osd_data_map { - u32 odm_num_comps; - u64 odm_stripe_unit; - u32 odm_group_width; - u32 odm_group_depth; - u32 odm_mirror_cnt; - u32 odm_raid_algorithm; -}; - -#endif /* ! defined(__PNFS_OSD_XDR_H__) */ - -#endif /* __EXOFS_PNFS_H__ */ diff --git a/fs/exofs/super.c b/fs/exofs/super.c index c57beddcc217..274894053b02 100644 --- a/fs/exofs/super.c +++ b/fs/exofs/super.c @@ -40,6 +40,8 @@ #include "exofs.h" +#define EXOFS_DBGMSG2(M...) do {} while (0) + /****************************************************************************** * MOUNT OPTIONS *****************************************************************************/ @@ -208,10 +210,48 @@ static void destroy_inodecache(void) } /****************************************************************************** - * SUPERBLOCK FUNCTIONS + * Some osd helpers *****************************************************************************/ -static const struct super_operations exofs_sops; -static const struct export_operations exofs_export_ops; +void exofs_make_credential(u8 cred_a[OSD_CAP_LEN], const struct osd_obj_id *obj) +{ + osd_sec_init_nosec_doall_caps(cred_a, obj, false, true); +} + +static int exofs_read_kern(struct osd_dev *od, u8 *cred, struct osd_obj_id *obj, + u64 offset, void *p, unsigned length) +{ + struct osd_request *or = osd_start_request(od, GFP_KERNEL); +/* struct osd_sense_info osi = {.key = 0};*/ + int ret; + + if (unlikely(!or)) { + EXOFS_DBGMSG("%s: osd_start_request failed.\n", __func__); + return -ENOMEM; + } + ret = osd_req_read_kern(or, obj, offset, p, length); + if (unlikely(ret)) { + EXOFS_DBGMSG("%s: osd_req_read_kern failed.\n", __func__); + goto out; + } + + ret = osd_finalize_request(or, 0, cred, NULL); + if (unlikely(ret)) { + EXOFS_DBGMSG("Failed to osd_finalize_request() => %d\n", ret); + goto out; + } + + ret = osd_execute_request(or); + if (unlikely(ret)) + EXOFS_DBGMSG("osd_execute_request() => %d\n", ret); + /* osd_req_decode_sense(or, ret); */ + +out: + osd_end_request(or); + EXOFS_DBGMSG2("read_kern(0x%llx) offset=0x%llx " + "length=0x%llx dev=%p ret=>%d\n", + _LLU(obj->id), _LLU(offset), _LLU(length), od, ret); + return ret; +} static const struct osd_attr g_attr_sb_stats = ATTR_DEF( EXOFS_APAGE_SB_DATA, @@ -223,21 +263,19 @@ static int __sbi_read_stats(struct exofs_sb_info *sbi) struct osd_attr attrs[] = { [0] = g_attr_sb_stats, }; - struct exofs_io_state *ios; + struct ore_io_state *ios; int ret; - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &sbi->comps, &ios); if (unlikely(ret)) { - EXOFS_ERR("%s: exofs_get_io_state failed.\n", __func__); + EXOFS_ERR("%s: ore_get_io_state failed.\n", __func__); return ret; } - ios->cred = sbi->s_cred; - ios->in_attr = attrs; ios->in_attr_len = ARRAY_SIZE(attrs); - ret = exofs_sbi_read(ios); + ret = ore_read(ios); if (unlikely(ret)) { EXOFS_ERR("Error reading super_block stats => %d\n", ret); goto out; @@ -264,13 +302,13 @@ static int __sbi_read_stats(struct exofs_sb_info *sbi) } out: - exofs_put_io_state(ios); + ore_put_io_state(ios); return ret; } -static void stats_done(struct exofs_io_state *ios, void *p) +static void stats_done(struct ore_io_state *ios, void *p) { - exofs_put_io_state(ios); + ore_put_io_state(ios); /* Good thanks nothing to do anymore */ } @@ -280,12 +318,12 @@ int exofs_sbi_write_stats(struct exofs_sb_info *sbi) struct osd_attr attrs[] = { [0] = g_attr_sb_stats, }; - struct exofs_io_state *ios; + struct ore_io_state *ios; int ret; - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &sbi->comps, &ios); if (unlikely(ret)) { - EXOFS_ERR("%s: exofs_get_io_state failed.\n", __func__); + EXOFS_ERR("%s: ore_get_io_state failed.\n", __func__); return ret; } @@ -293,21 +331,27 @@ int exofs_sbi_write_stats(struct exofs_sb_info *sbi) sbi->s_ess.s_numfiles = cpu_to_le64(sbi->s_numfiles); attrs[0].val_ptr = &sbi->s_ess; - ios->cred = sbi->s_cred; + ios->done = stats_done; ios->private = sbi; ios->out_attr = attrs; ios->out_attr_len = ARRAY_SIZE(attrs); - ret = exofs_sbi_write(ios); + ret = ore_write(ios); if (unlikely(ret)) { - EXOFS_ERR("%s: exofs_sbi_write failed.\n", __func__); - exofs_put_io_state(ios); + EXOFS_ERR("%s: ore_write failed.\n", __func__); + ore_put_io_state(ios); } return ret; } +/****************************************************************************** + * SUPERBLOCK FUNCTIONS + *****************************************************************************/ +static const struct super_operations exofs_sops; +static const struct export_operations exofs_export_ops; + /* * Write the superblock to the OSD */ @@ -315,7 +359,9 @@ int exofs_sync_fs(struct super_block *sb, int wait) { struct exofs_sb_info *sbi; struct exofs_fscb *fscb; - struct exofs_io_state *ios; + struct ore_comp one_comp; + struct ore_components comps; + struct ore_io_state *ios; int ret = -ENOMEM; fscb = kmalloc(sizeof(*fscb), GFP_KERNEL); @@ -331,7 +377,10 @@ int exofs_sync_fs(struct super_block *sb, int wait) * version). Otherwise the exofs_fscb is read-only from mkfs time. All * the writeable info is set in exofs_sbi_write_stats() above. */ - ret = exofs_get_io_state(&sbi->layout, &ios); + + exofs_init_comps(&comps, &one_comp, sbi, EXOFS_SUPER_ID); + + ret = ore_get_io_state(&sbi->layout, &comps, &ios); if (unlikely(ret)) goto out; @@ -345,14 +394,12 @@ int exofs_sync_fs(struct super_block *sb, int wait) fscb->s_newfs = 0; fscb->s_version = EXOFS_FSCB_VER; - ios->obj.id = EXOFS_SUPER_ID; ios->offset = 0; ios->kern_buff = fscb; - ios->cred = sbi->s_cred; - ret = exofs_sbi_write(ios); + ret = ore_write(ios); if (unlikely(ret)) - EXOFS_ERR("%s: exofs_sbi_write failed.\n", __func__); + EXOFS_ERR("%s: ore_write failed.\n", __func__); else sb->s_dirt = 0; @@ -360,7 +407,7 @@ int exofs_sync_fs(struct super_block *sb, int wait) unlock_super(sb); out: EXOFS_DBGMSG("s_nextid=0x%llx ret=%d\n", _LLU(sbi->s_nextid), ret); - exofs_put_io_state(ios); + ore_put_io_state(ios); kfree(fscb); return ret; } @@ -384,15 +431,17 @@ static void _exofs_print_device(const char *msg, const char *dev_path, void exofs_free_sbi(struct exofs_sb_info *sbi) { - while (sbi->layout.s_numdevs) { - int i = --sbi->layout.s_numdevs; - struct osd_dev *od = sbi->layout.s_ods[i]; + while (sbi->comps.numdevs) { + int i = --sbi->comps.numdevs; + struct osd_dev *od = sbi->comps.ods[i]; if (od) { - sbi->layout.s_ods[i] = NULL; + sbi->comps.ods[i] = NULL; osduld_put_device(od); } } + if (sbi->comps.ods != sbi->_min_one_dev) + kfree(sbi->comps.ods); kfree(sbi); } @@ -419,8 +468,8 @@ static void exofs_put_super(struct super_block *sb) msecs_to_jiffies(100)); } - _exofs_print_device("Unmounting", NULL, sbi->layout.s_ods[0], - sbi->layout.s_pid); + _exofs_print_device("Unmounting", NULL, sbi->comps.ods[0], + sbi->one_comp.obj.partition); bdi_destroy(&sbi->bdi); exofs_free_sbi(sbi); @@ -501,10 +550,19 @@ static int _read_and_match_data_map(struct exofs_sb_info *sbi, unsigned numdevs, return -EINVAL; } + EXOFS_DBGMSG("exofs: layout: " + "num_comps=%u stripe_unit=0x%x group_width=%u " + "group_depth=0x%llx mirrors_p1=%u raid_algorithm=%u\n", + numdevs, + sbi->layout.stripe_unit, + sbi->layout.group_width, + _LLU(sbi->layout.group_depth), + sbi->layout.mirrors_p1, + sbi->data_map.odm_raid_algorithm); return 0; } -static unsigned __ra_pages(struct exofs_layout *layout) +static unsigned __ra_pages(struct ore_layout *layout) { const unsigned _MIN_RA = 32; /* min 128K read-ahead */ unsigned ra_pages = layout->group_width * layout->stripe_unit / @@ -547,13 +605,11 @@ static int exofs_devs_2_odi(struct exofs_dt_device_info *dt_dev, return !(odi->systemid_len || odi->osdname_len); } -static int exofs_read_lookup_dev_table(struct exofs_sb_info **psbi, +static int exofs_read_lookup_dev_table(struct exofs_sb_info *sbi, + struct osd_dev *fscb_od, unsigned table_count) { - struct exofs_sb_info *sbi = *psbi; - struct osd_dev *fscb_od; - struct osd_obj_id obj = {.partition = sbi->layout.s_pid, - .id = EXOFS_DEVTABLE_ID}; + struct ore_comp comp; struct exofs_device_table *dt; unsigned table_bytes = table_count * sizeof(dt->dt_dev_table[0]) + sizeof(*dt); @@ -567,10 +623,14 @@ static int exofs_read_lookup_dev_table(struct exofs_sb_info **psbi, return -ENOMEM; } - fscb_od = sbi->layout.s_ods[0]; - sbi->layout.s_ods[0] = NULL; - sbi->layout.s_numdevs = 0; - ret = exofs_read_kern(fscb_od, sbi->s_cred, &obj, 0, dt, table_bytes); + sbi->comps.numdevs = 0; + + comp.obj.partition = sbi->one_comp.obj.partition; + comp.obj.id = EXOFS_DEVTABLE_ID; + exofs_make_credential(comp.cred, &comp.obj); + + ret = exofs_read_kern(fscb_od, comp.cred, &comp.obj, 0, dt, + table_bytes); if (unlikely(ret)) { EXOFS_ERR("ERROR: reading device table\n"); goto out; @@ -588,16 +648,18 @@ static int exofs_read_lookup_dev_table(struct exofs_sb_info **psbi, goto out; if (likely(numdevs > 1)) { - unsigned size = numdevs * sizeof(sbi->layout.s_ods[0]); + unsigned size = numdevs * sizeof(sbi->comps.ods[0]); - sbi = krealloc(sbi, sizeof(*sbi) + size, GFP_KERNEL); - if (unlikely(!sbi)) { + /* Twice bigger table: See exofs_init_comps() and below + * comment + */ + sbi->comps.ods = kzalloc(size + size - 1, GFP_KERNEL); + if (unlikely(!sbi->comps.ods)) { + EXOFS_ERR("ERROR: faild allocating Device array[%d]\n", + numdevs); ret = -ENOMEM; goto out; } - memset(&sbi->layout.s_ods[1], 0, - size - sizeof(sbi->layout.s_ods[0])); - *psbi = sbi; } for (i = 0; i < numdevs; i++) { @@ -619,8 +681,8 @@ static int exofs_read_lookup_dev_table(struct exofs_sb_info **psbi, * line. We always keep them in device-table order. */ if (fscb_od && osduld_device_same(fscb_od, &odi)) { - sbi->layout.s_ods[i] = fscb_od; - ++sbi->layout.s_numdevs; + sbi->comps.ods[i] = fscb_od; + ++sbi->comps.numdevs; fscb_od = NULL; continue; } @@ -633,13 +695,13 @@ static int exofs_read_lookup_dev_table(struct exofs_sb_info **psbi, goto out; } - sbi->layout.s_ods[i] = od; - ++sbi->layout.s_numdevs; + sbi->comps.ods[i] = od; + ++sbi->comps.numdevs; /* Read the fscb of the other devices to make sure the FS * partition is there. */ - ret = exofs_read_kern(od, sbi->s_cred, &obj, 0, &fscb, + ret = exofs_read_kern(od, comp.cred, &comp.obj, 0, &fscb, sizeof(fscb)); if (unlikely(ret)) { EXOFS_ERR("ERROR: Malformed participating device " @@ -656,13 +718,22 @@ static int exofs_read_lookup_dev_table(struct exofs_sb_info **psbi, out: kfree(dt); - if (unlikely(!ret && fscb_od)) { - EXOFS_ERR( - "ERROR: Bad device-table container device not present\n"); - osduld_put_device(fscb_od); - ret = -EINVAL; - } + if (likely(!ret)) { + unsigned numdevs = sbi->comps.numdevs; + if (unlikely(fscb_od)) { + EXOFS_ERR("ERROR: Bad device-table container device not present\n"); + osduld_put_device(fscb_od); + return -EINVAL; + } + /* exofs round-robins the device table view according to inode + * number. We hold a: twice bigger table hence inodes can point + * to any device and have a sequential view of the table + * starting at this device. See exofs_init_comps() + */ + for (i = 0; i < numdevs - 1; ++i) + sbi->comps.ods[i + numdevs] = sbi->comps.ods[i]; + } return ret; } @@ -676,7 +747,7 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) struct exofs_sb_info *sbi; /*extended info */ struct osd_dev *od; /* Master device */ struct exofs_fscb fscb; /*on-disk superblock info */ - struct osd_obj_id obj; + struct ore_comp comp; unsigned table_count; int ret; @@ -684,10 +755,6 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) if (!sbi) return -ENOMEM; - ret = bdi_setup_and_register(&sbi->bdi, "exofs", BDI_CAP_MAP_COPY); - if (ret) - goto free_bdi; - /* use mount options to fill superblock */ if (opts->is_osdname) { struct osd_dev_info odi = {.systemid_len = 0}; @@ -695,6 +762,8 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) odi.osdname_len = strlen(opts->dev_name); odi.osdname = (u8 *)opts->dev_name; od = osduld_info_lookup(&odi); + kfree(opts->dev_name); + opts->dev_name = NULL; } else { od = osduld_path_lookup(opts->dev_name); } @@ -709,11 +778,16 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) sbi->layout.group_width = 1; sbi->layout.group_depth = -1; sbi->layout.group_count = 1; - sbi->layout.s_ods[0] = od; - sbi->layout.s_numdevs = 1; - sbi->layout.s_pid = opts->pid; sbi->s_timeout = opts->timeout; + sbi->one_comp.obj.partition = opts->pid; + sbi->one_comp.obj.id = 0; + exofs_make_credential(sbi->one_comp.cred, &sbi->one_comp.obj); + sbi->comps.numdevs = 1; + sbi->comps.single_comp = EC_SINGLE_COMP; + sbi->comps.comps = &sbi->one_comp; + sbi->comps.ods = sbi->_min_one_dev; + /* fill in some other data by hand */ memset(sb->s_id, 0, sizeof(sb->s_id)); strcpy(sb->s_id, "exofs"); @@ -724,11 +798,11 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) sb->s_bdev = NULL; sb->s_dev = 0; - obj.partition = sbi->layout.s_pid; - obj.id = EXOFS_SUPER_ID; - exofs_make_credential(sbi->s_cred, &obj); + comp.obj.partition = sbi->one_comp.obj.partition; + comp.obj.id = EXOFS_SUPER_ID; + exofs_make_credential(comp.cred, &comp.obj); - ret = exofs_read_kern(od, sbi->s_cred, &obj, 0, &fscb, sizeof(fscb)); + ret = exofs_read_kern(od, comp.cred, &comp.obj, 0, &fscb, sizeof(fscb)); if (unlikely(ret)) goto free_sbi; @@ -757,9 +831,11 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) table_count = le64_to_cpu(fscb.s_dev_table_count); if (table_count) { - ret = exofs_read_lookup_dev_table(&sbi, table_count); + ret = exofs_read_lookup_dev_table(sbi, od, table_count); if (unlikely(ret)) goto free_sbi; + } else { + sbi->comps.ods[0] = od; } __sbi_read_stats(sbi); @@ -793,20 +869,20 @@ static int exofs_fill_super(struct super_block *sb, void *data, int silent) goto free_sbi; } - _exofs_print_device("Mounting", opts->dev_name, sbi->layout.s_ods[0], - sbi->layout.s_pid); - if (opts->is_osdname) - kfree(opts->dev_name); + ret = bdi_setup_and_register(&sbi->bdi, "exofs", BDI_CAP_MAP_COPY); + if (ret) { + EXOFS_DBGMSG("Failed to bdi_setup_and_register\n"); + goto free_sbi; + } + + _exofs_print_device("Mounting", opts->dev_name, sbi->comps.ods[0], + sbi->one_comp.obj.partition); return 0; free_sbi: - bdi_destroy(&sbi->bdi); -free_bdi: EXOFS_ERR("Unable to mount exofs on %s pid=0x%llx err=%d\n", - opts->dev_name, sbi->layout.s_pid, ret); + opts->dev_name, sbi->one_comp.obj.partition, ret); exofs_free_sbi(sbi); - if (opts->is_osdname) - kfree(opts->dev_name); return ret; } @@ -837,7 +913,7 @@ static int exofs_statfs(struct dentry *dentry, struct kstatfs *buf) { struct super_block *sb = dentry->d_sb; struct exofs_sb_info *sbi = sb->s_fs_info; - struct exofs_io_state *ios; + struct ore_io_state *ios; struct osd_attr attrs[] = { ATTR_DEF(OSD_APAGE_PARTITION_QUOTAS, OSD_ATTR_PQ_CAPACITY_QUOTA, sizeof(__be64)), @@ -846,21 +922,18 @@ static int exofs_statfs(struct dentry *dentry, struct kstatfs *buf) }; uint64_t capacity = ULLONG_MAX; uint64_t used = ULLONG_MAX; - uint8_t cred_a[OSD_CAP_LEN]; int ret; - ret = exofs_get_io_state(&sbi->layout, &ios); + ret = ore_get_io_state(&sbi->layout, &sbi->comps, &ios); if (ret) { - EXOFS_DBGMSG("exofs_get_io_state failed.\n"); + EXOFS_DBGMSG("ore_get_io_state failed.\n"); return ret; } - exofs_make_credential(cred_a, &ios->obj); - ios->cred = sbi->s_cred; ios->in_attr = attrs; ios->in_attr_len = ARRAY_SIZE(attrs); - ret = exofs_sbi_read(ios); + ret = ore_read(ios); if (unlikely(ret)) goto out; @@ -889,7 +962,7 @@ static int exofs_statfs(struct dentry *dentry, struct kstatfs *buf) buf->f_namelen = EXOFS_NAME_LEN; out: - exofs_put_io_state(ios); + ore_put_io_state(ios); return ret; } diff --git a/fs/inode.c b/fs/inode.c index 5aab80dc008c..73920d555c88 100644 --- a/fs/inode.c +++ b/fs/inode.c @@ -143,6 +143,7 @@ int inode_init_always(struct super_block *sb, struct inode *inode) inode->i_op = &empty_iops; inode->i_fop = &empty_fops; inode->i_nlink = 1; + inode->i_opflags = 0; inode->i_uid = 0; inode->i_gid = 0; atomic_set(&inode->i_writecount, 0); diff --git a/fs/namei.c b/fs/namei.c index 445fd5da11fa..2826db35dc25 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -179,19 +179,14 @@ static int check_acl(struct inode *inode, int mask) #ifdef CONFIG_FS_POSIX_ACL struct posix_acl *acl; - /* - * Under RCU walk, we cannot even do a "get_cached_acl()", - * because that involves locking and getting a refcount on - * a cached ACL. - * - * So the only case we handle during RCU walking is the - * case of a cached "no ACL at all", which needs no locks - * or refcounts. - */ if (mask & MAY_NOT_BLOCK) { - if (negative_cached_acl(inode, ACL_TYPE_ACCESS)) + acl = get_cached_acl_rcu(inode, ACL_TYPE_ACCESS); + if (!acl) return -EAGAIN; - return -ECHILD; + /* no ->get_acl() calls in RCU mode... */ + if (acl == ACL_NOT_CACHED) + return -ECHILD; + return posix_acl_permission(inode, acl, mask & ~MAY_NOT_BLOCK); } acl = get_cached_acl(inode, ACL_TYPE_ACCESS); @@ -313,6 +308,26 @@ int generic_permission(struct inode *inode, int mask) return -EACCES; } +/* + * We _really_ want to just do "generic_permission()" without + * even looking at the inode->i_op values. So we keep a cache + * flag in inode->i_opflags, that says "this has not special + * permission function, use the fast case". + */ +static inline int do_inode_permission(struct inode *inode, int mask) +{ + if (unlikely(!(inode->i_opflags & IOP_FASTPERM))) { + if (likely(inode->i_op->permission)) + return inode->i_op->permission(inode, mask); + + /* This gets set once for the inode lifetime */ + spin_lock(&inode->i_lock); + inode->i_opflags |= IOP_FASTPERM; + spin_unlock(&inode->i_lock); + } + return generic_permission(inode, mask); +} + /** * inode_permission - check for access rights to a given inode * @inode: inode to check permission on @@ -327,7 +342,7 @@ int inode_permission(struct inode *inode, int mask) { int retval; - if (mask & MAY_WRITE) { + if (unlikely(mask & MAY_WRITE)) { umode_t mode = inode->i_mode; /* @@ -344,11 +359,7 @@ int inode_permission(struct inode *inode, int mask) return -EACCES; } - if (inode->i_op->permission) - retval = inode->i_op->permission(inode, mask); - else - retval = generic_permission(inode, mask); - + retval = do_inode_permission(inode, mask); if (retval) return retval; @@ -1250,6 +1261,26 @@ static void terminate_walk(struct nameidata *nd) } } +/* + * Do we need to follow links? We _really_ want to be able + * to do this check without having to look at inode->i_op, + * so we keep a cache of "no, this doesn't need follow_link" + * for the common case. + */ +static inline int should_follow_link(struct inode *inode, int follow) +{ + if (unlikely(!(inode->i_opflags & IOP_NOFOLLOW))) { + if (likely(inode->i_op->follow_link)) + return follow; + + /* This gets set once for the inode lifetime */ + spin_lock(&inode->i_lock); + inode->i_opflags |= IOP_NOFOLLOW; + spin_unlock(&inode->i_lock); + } + return 0; +} + static inline int walk_component(struct nameidata *nd, struct path *path, struct qstr *name, int type, int follow) { @@ -1272,7 +1303,7 @@ static inline int walk_component(struct nameidata *nd, struct path *path, terminate_walk(nd); return -ENOENT; } - if (unlikely(inode->i_op->follow_link) && follow) { + if (should_follow_link(inode, follow)) { if (nd->flags & LOOKUP_RCU) { if (unlikely(unlazy_walk(nd, path->dentry))) { terminate_walk(nd); @@ -1325,6 +1356,26 @@ static inline int nested_symlink(struct path *path, struct nameidata *nd) } /* + * We really don't want to look at inode->i_op->lookup + * when we don't have to. So we keep a cache bit in + * the inode ->i_opflags field that says "yes, we can + * do lookup on this inode". + */ +static inline int can_lookup(struct inode *inode) +{ + if (likely(inode->i_opflags & IOP_LOOKUP)) + return 1; + if (likely(!inode->i_op->lookup)) + return 0; + + /* We do this once for the lifetime of the inode */ + spin_lock(&inode->i_lock); + inode->i_opflags |= IOP_LOOKUP; + spin_unlock(&inode->i_lock); + return 1; +} + +/* * Name resolution. * This is the basic name resolution function, turning a pathname into * the final dentry. We expect 'base' to be positive and a directory. @@ -1403,10 +1454,10 @@ static int link_path_walk(const char *name, struct nameidata *nd) if (err) return err; } + if (can_lookup(nd->inode)) + continue; err = -ENOTDIR; - if (!nd->inode->i_op->lookup) - break; - continue; + break; /* here ends the main loop */ last_component: diff --git a/fs/proc/base.c b/fs/proc/base.c index 08e3eccf9a12..5eb02069e1b8 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -1118,7 +1118,7 @@ static ssize_t oom_adjust_write(struct file *file, const char __user *buf, * Warn that /proc/pid/oom_adj is deprecated, see * Documentation/feature-removal-schedule.txt. */ - WARN_ONCE(1, "%s (%d): /proc/%d/oom_adj is deprecated, please use /proc/%d/oom_score_adj instead.\n", + printk_once(KERN_WARNING "%s (%d): /proc/%d/oom_adj is deprecated, please use /proc/%d/oom_score_adj instead.\n", current->comm, task_pid_nr(current), task_pid_nr(task), task_pid_nr(task)); task->signal->oom_adj = oom_adjust; @@ -1919,6 +1919,14 @@ static int proc_fd_info(struct inode *inode, struct path *path, char *info) spin_lock(&files->file_lock); file = fcheck_files(files, fd); if (file) { + unsigned int f_flags; + struct fdtable *fdt; + + fdt = files_fdtable(files); + f_flags = file->f_flags & ~O_CLOEXEC; + if (FD_ISSET(fd, fdt->close_on_exec)) + f_flags |= O_CLOEXEC; + if (path) { *path = file->f_path; path_get(&file->f_path); @@ -1928,7 +1936,7 @@ static int proc_fd_info(struct inode *inode, struct path *path, char *info) "pos:\t%lli\n" "flags:\t0%o\n", (long long) file->f_pos, - file->f_flags); + f_flags); spin_unlock(&files->file_lock); put_files_struct(files); return 0; diff --git a/fs/stat.c b/fs/stat.c index 961039121cb8..ba5316ffac61 100644 --- a/fs/stat.c +++ b/fs/stat.c @@ -27,12 +27,12 @@ void generic_fillattr(struct inode *inode, struct kstat *stat) stat->uid = inode->i_uid; stat->gid = inode->i_gid; stat->rdev = inode->i_rdev; + stat->size = i_size_read(inode); stat->atime = inode->i_atime; stat->mtime = inode->i_mtime; stat->ctime = inode->i_ctime; - stat->size = i_size_read(inode); - stat->blocks = inode->i_blocks; stat->blksize = (1 << inode->i_blkbits); + stat->blocks = inode->i_blocks; } EXPORT_SYMBOL(generic_fillattr); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 33d12f87f0e0..44335e57eaaa 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -205,6 +205,8 @@ struct drm_display_info { enum subpixel_order subpixel_order; u32 color_formats; + u8 cea_rev; + char *raw_edid; /* if any */ }; @@ -802,6 +804,7 @@ extern struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev, extern int drm_add_modes_noedid(struct drm_connector *connector, int hdisplay, int vdisplay); +extern int drm_edid_header_is_valid(const u8 *raw_edid); extern bool drm_edid_is_valid(struct edid *edid); struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh); diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index c4d6dbfa3ff4..28c0d114cb52 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -237,7 +237,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) +#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) /* Allow drivers to submit batchbuffers directly to hardware, relying diff --git a/include/linux/cred.h b/include/linux/cred.h index 48e82af1159b..40308969ed00 100644 --- a/include/linux/cred.h +++ b/include/linux/cred.h @@ -265,10 +265,11 @@ static inline void put_cred(const struct cred *_cred) /** * current_cred - Access the current task's subjective credentials * - * Access the subjective credentials of the current task. + * Access the subjective credentials of the current task. RCU-safe, + * since nobody else can modify it. */ #define current_cred() \ - (current->cred) + rcu_dereference_protected(current->cred, 1) /** * __task_cred - Access a task's objective credentials @@ -306,8 +307,8 @@ static inline void put_cred(const struct cred *_cred) #define get_current_user() \ ({ \ struct user_struct *__u; \ - struct cred *__cred; \ - __cred = (struct cred *) current_cred(); \ + const struct cred *__cred; \ + __cred = current_cred(); \ __u = get_uid(__cred->user); \ __u; \ }) @@ -321,8 +322,8 @@ static inline void put_cred(const struct cred *_cred) #define get_current_groups() \ ({ \ struct group_info *__groups; \ - struct cred *__cred; \ - __cred = (struct cred *) current_cred(); \ + const struct cred *__cred; \ + __cred = current_cred(); \ __groups = get_group_info(__cred->group_info); \ __groups; \ }) @@ -341,7 +342,7 @@ static inline void put_cred(const struct cred *_cred) #define current_cred_xxx(xxx) \ ({ \ - current->cred->xxx; \ + current_cred()->xxx; \ }) #define current_uid() (current_cred_xxx(uid)) diff --git a/include/linux/cryptohash.h b/include/linux/cryptohash.h index ec78a4bbe1d5..2cd9f1cf9fa3 100644 --- a/include/linux/cryptohash.h +++ b/include/linux/cryptohash.h @@ -3,11 +3,16 @@ #define SHA_DIGEST_WORDS 5 #define SHA_MESSAGE_BYTES (512 /*bits*/ / 8) -#define SHA_WORKSPACE_WORDS 80 +#define SHA_WORKSPACE_WORDS 16 void sha_init(__u32 *buf); void sha_transform(__u32 *digest, const char *data, __u32 *W); +#define MD5_DIGEST_WORDS 4 +#define MD5_MESSAGE_BYTES 64 + +void md5_transform(__u32 *hash, __u32 const *in); + __u32 half_md4_transform(__u32 buf[4], __u32 const in[8]); #endif diff --git a/include/linux/dcache.h b/include/linux/dcache.h index d37d2a793099..62157c03caf7 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -180,12 +180,12 @@ struct dentry_operations { */ /* d_flags entries */ -#define DCACHE_AUTOFS_PENDING 0x0001 /* autofs: "under construction" */ -#define DCACHE_NFSFS_RENAMED 0x0002 - /* this dentry has been "silly renamed" and has to be deleted on the last - * dput() */ +#define DCACHE_OP_HASH 0x0001 +#define DCACHE_OP_COMPARE 0x0002 +#define DCACHE_OP_REVALIDATE 0x0004 +#define DCACHE_OP_DELETE 0x0008 -#define DCACHE_DISCONNECTED 0x0004 +#define DCACHE_DISCONNECTED 0x0010 /* This dentry is possibly not currently connected to the dcache tree, in * which case its parent will either be itself, or will have this flag as * well. nfsd will not use a dentry with this bit set, but will first @@ -196,22 +196,18 @@ struct dentry_operations { * dentry into place and return that dentry rather than the passed one, * typically using d_splice_alias. */ -#define DCACHE_REFERENCED 0x0008 /* Recently used, don't discard. */ -#define DCACHE_RCUACCESS 0x0010 /* Entry has ever been RCU-visible */ -#define DCACHE_INOTIFY_PARENT_WATCHED 0x0020 - /* Parent inode is watched by inotify */ - -#define DCACHE_COOKIE 0x0040 /* For use by dcookie subsystem */ -#define DCACHE_FSNOTIFY_PARENT_WATCHED 0x0080 - /* Parent inode is watched by some fsnotify listener */ +#define DCACHE_REFERENCED 0x0020 /* Recently used, don't discard. */ +#define DCACHE_RCUACCESS 0x0040 /* Entry has ever been RCU-visible */ #define DCACHE_CANT_MOUNT 0x0100 #define DCACHE_GENOCIDE 0x0200 -#define DCACHE_OP_HASH 0x1000 -#define DCACHE_OP_COMPARE 0x2000 -#define DCACHE_OP_REVALIDATE 0x4000 -#define DCACHE_OP_DELETE 0x8000 +#define DCACHE_NFSFS_RENAMED 0x1000 + /* this dentry has been "silly renamed" and has to be deleted on the last + * dput() */ +#define DCACHE_COOKIE 0x2000 /* For use by dcookie subsystem */ +#define DCACHE_FSNOTIFY_PARENT_WATCHED 0x4000 + /* Parent inode is watched by some fsnotify listener */ #define DCACHE_MOUNTED 0x10000 /* is a mountpoint */ #define DCACHE_NEED_AUTOMOUNT 0x20000 /* handle automount on this dir */ diff --git a/include/linux/fs.h b/include/linux/fs.h index 786b3b1113cf..178cdb4f1d4a 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -738,22 +738,54 @@ static inline int mapping_writably_mapped(struct address_space *mapping) struct posix_acl; #define ACL_NOT_CACHED ((void *)(-1)) +#define IOP_FASTPERM 0x0001 +#define IOP_LOOKUP 0x0002 +#define IOP_NOFOLLOW 0x0004 + +/* + * Keep mostly read-only and often accessed (especially for + * the RCU path lookup and 'stat' data) fields at the beginning + * of the 'struct inode' + */ struct inode { - /* RCU path lookup touches following: */ umode_t i_mode; + unsigned short i_opflags; uid_t i_uid; gid_t i_gid; + unsigned int i_flags; + +#ifdef CONFIG_FS_POSIX_ACL + struct posix_acl *i_acl; + struct posix_acl *i_default_acl; +#endif + const struct inode_operations *i_op; struct super_block *i_sb; + struct address_space *i_mapping; - spinlock_t i_lock; /* i_blocks, i_bytes, maybe i_size */ - unsigned int i_flags; - unsigned long i_state; #ifdef CONFIG_SECURITY void *i_security; #endif - struct mutex i_mutex; + /* Stat data, not accessed from path walking */ + unsigned long i_ino; + unsigned int i_nlink; + dev_t i_rdev; + loff_t i_size; + struct timespec i_atime; + struct timespec i_mtime; + struct timespec i_ctime; + unsigned int i_blkbits; + blkcnt_t i_blocks; + +#ifdef __NEED_I_SIZE_ORDERED + seqcount_t i_size_seqcount; +#endif + + /* Misc */ + unsigned long i_state; + spinlock_t i_lock; /* i_blocks, i_bytes, maybe i_size */ + struct mutex i_mutex; unsigned long dirtied_when; /* jiffies of first dirtying */ @@ -765,25 +797,12 @@ struct inode { struct list_head i_dentry; struct rcu_head i_rcu; }; - unsigned long i_ino; atomic_t i_count; - unsigned int i_nlink; - dev_t i_rdev; - unsigned int i_blkbits; u64 i_version; - loff_t i_size; -#ifdef __NEED_I_SIZE_ORDERED - seqcount_t i_size_seqcount; -#endif - struct timespec i_atime; - struct timespec i_mtime; - struct timespec i_ctime; - blkcnt_t i_blocks; unsigned short i_bytes; atomic_t i_dio_count; const struct file_operations *i_fop; /* former ->i_op->default_file_ops */ struct file_lock *i_flock; - struct address_space *i_mapping; struct address_space i_data; #ifdef CONFIG_QUOTA struct dquot *i_dquot[MAXQUOTAS]; @@ -806,10 +825,6 @@ struct inode { atomic_t i_readcount; /* struct files open RO */ #endif atomic_t i_writecount; -#ifdef CONFIG_FS_POSIX_ACL - struct posix_acl *i_acl; - struct posix_acl *i_default_acl; -#endif void *i_private; /* fs or device private pointer */ }; diff --git a/include/linux/input.h b/include/linux/input.h index 068784e17972..a637e7814334 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -438,6 +438,8 @@ struct input_keymap_entry { #define KEY_WIMAX 246 #define KEY_RFKILL 247 /* Key that controls all radios */ +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 diff --git a/include/linux/mm.h b/include/linux/mm.h index f2690cf49827..fd599f4bb846 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -962,6 +962,8 @@ int invalidate_inode_page(struct page *page); #ifdef CONFIG_MMU extern int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, unsigned int flags); +extern int fixup_user_fault(struct task_struct *tsk, struct mm_struct *mm, + unsigned long address, unsigned int fault_flags); #else static inline int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, @@ -971,6 +973,14 @@ static inline int handle_mm_fault(struct mm_struct *mm, BUG(); return VM_FAULT_SIGBUS; } +static inline int fixup_user_fault(struct task_struct *tsk, + struct mm_struct *mm, unsigned long address, + unsigned int fault_flags) +{ + /* should never happen if there's no MMU */ + BUG(); + return -EFAULT; +} #endif extern int make_pages_present(unsigned long addr, unsigned long end); @@ -988,8 +998,6 @@ int get_user_pages(struct task_struct *tsk, struct mm_struct *mm, int get_user_pages_fast(unsigned long start, int nr_pages, int write, struct page **pages); struct page *get_dump_page(unsigned long addr); -extern int fixup_user_fault(struct task_struct *tsk, struct mm_struct *mm, - unsigned long address, unsigned int fault_flags); extern int try_to_release_page(struct page * page, gfp_t gfp_mask); extern void do_invalidatepage(struct page *page, unsigned long offset); diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 569ea5b76fda..abd615d74a29 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -773,6 +773,11 @@ struct nfs3_getaclres { struct posix_acl * acl_default; }; +struct nfs4_string { + unsigned int len; + char *data; +}; + #ifdef CONFIG_NFS_V4 typedef u64 clientid4; @@ -963,11 +968,6 @@ struct nfs4_server_caps_res { struct nfs4_sequence_res seq_res; }; -struct nfs4_string { - unsigned int len; - char *data; -}; - #define NFS4_PATHNAME_MAXCOMPONENTS 512 struct nfs4_pathname { unsigned int ncomponents; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index b00c4ec5056e..ae96bbe54518 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2709,6 +2709,16 @@ #define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f +#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e +#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 diff --git a/include/linux/posix_acl.h b/include/linux/posix_acl.h index 951bba82d50d..b7681102a4b9 100644 --- a/include/linux/posix_acl.h +++ b/include/linux/posix_acl.h @@ -9,6 +9,7 @@ #define __LINUX_POSIX_ACL_H #include <linux/slab.h> +#include <linux/rcupdate.h> #define ACL_UNDEFINED_ID (-1) @@ -38,7 +39,10 @@ struct posix_acl_entry { }; struct posix_acl { - atomic_t a_refcount; + union { + atomic_t a_refcount; + struct rcu_head a_rcu; + }; unsigned int a_count; struct posix_acl_entry a_entries[0]; }; @@ -65,7 +69,7 @@ static inline void posix_acl_release(struct posix_acl *acl) { if (acl && atomic_dec_and_test(&acl->a_refcount)) - kfree(acl); + kfree_rcu(acl, a_rcu); } @@ -84,20 +88,22 @@ extern struct posix_acl *get_posix_acl(struct inode *, int); extern int set_posix_acl(struct inode *, int, struct posix_acl *); #ifdef CONFIG_FS_POSIX_ACL -static inline struct posix_acl *get_cached_acl(struct inode *inode, int type) +static inline struct posix_acl **acl_by_type(struct inode *inode, int type) { - struct posix_acl **p, *acl; switch (type) { case ACL_TYPE_ACCESS: - p = &inode->i_acl; - break; + return &inode->i_acl; case ACL_TYPE_DEFAULT: - p = &inode->i_default_acl; - break; + return &inode->i_default_acl; default: - return ERR_PTR(-EINVAL); + BUG(); } - acl = ACCESS_ONCE(*p); +} + +static inline struct posix_acl *get_cached_acl(struct inode *inode, int type) +{ + struct posix_acl **p = acl_by_type(inode, type); + struct posix_acl *acl = ACCESS_ONCE(*p); if (acl) { spin_lock(&inode->i_lock); acl = *p; @@ -108,41 +114,20 @@ static inline struct posix_acl *get_cached_acl(struct inode *inode, int type) return acl; } -static inline int negative_cached_acl(struct inode *inode, int type) +static inline struct posix_acl *get_cached_acl_rcu(struct inode *inode, int type) { - struct posix_acl **p, *acl; - switch (type) { - case ACL_TYPE_ACCESS: - p = &inode->i_acl; - break; - case ACL_TYPE_DEFAULT: - p = &inode->i_default_acl; - break; - default: - BUG(); - } - acl = ACCESS_ONCE(*p); - if (acl) - return 0; - return 1; + return rcu_dereference(*acl_by_type(inode, type)); } static inline void set_cached_acl(struct inode *inode, int type, struct posix_acl *acl) { - struct posix_acl *old = NULL; + struct posix_acl **p = acl_by_type(inode, type); + struct posix_acl *old; spin_lock(&inode->i_lock); - switch (type) { - case ACL_TYPE_ACCESS: - old = inode->i_acl; - inode->i_acl = posix_acl_dup(acl); - break; - case ACL_TYPE_DEFAULT: - old = inode->i_default_acl; - inode->i_default_acl = posix_acl_dup(acl); - break; - } + old = *p; + rcu_assign_pointer(*p, posix_acl_dup(acl)); spin_unlock(&inode->i_lock); if (old != ACL_NOT_CACHED) posix_acl_release(old); @@ -150,18 +135,11 @@ static inline void set_cached_acl(struct inode *inode, static inline void forget_cached_acl(struct inode *inode, int type) { - struct posix_acl *old = NULL; + struct posix_acl **p = acl_by_type(inode, type); + struct posix_acl *old; spin_lock(&inode->i_lock); - switch (type) { - case ACL_TYPE_ACCESS: - old = inode->i_acl; - inode->i_acl = ACL_NOT_CACHED; - break; - case ACL_TYPE_DEFAULT: - old = inode->i_default_acl; - inode->i_default_acl = ACL_NOT_CACHED; - break; - } + old = *p; + *p = ACL_NOT_CACHED; spin_unlock(&inode->i_lock); if (old != ACL_NOT_CACHED) posix_acl_release(old); diff --git a/include/linux/random.h b/include/linux/random.h index ce29a040c8dc..d13059f3ea32 100644 --- a/include/linux/random.h +++ b/include/linux/random.h @@ -57,18 +57,6 @@ extern void add_interrupt_randomness(int irq); extern void get_random_bytes(void *buf, int nbytes); void generate_random_uuid(unsigned char uuid_out[16]); -extern __u32 secure_ip_id(__be32 daddr); -extern __u32 secure_ipv6_id(const __be32 daddr[4]); -extern u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); -extern u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, - __be16 dport); -extern __u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr, - __be16 sport, __be16 dport); -extern __u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr, - __be16 sport, __be16 dport); -extern u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr, - __be16 sport, __be16 dport); - #ifndef MODULE extern const struct file_operations random_fops, urandom_fops; #endif diff --git a/include/net/cipso_ipv4.h b/include/net/cipso_ipv4.h index 3b938743514b..9808877c2ab9 100644 --- a/include/net/cipso_ipv4.h +++ b/include/net/cipso_ipv4.h @@ -8,7 +8,7 @@ * have chosen to adopt the protocol and over the years it has become a * de-facto standard for labeled networking. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/include/net/dst.h b/include/net/dst.h index 29e255796ce1..13d507d69ddb 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -37,7 +37,7 @@ struct dst_entry { unsigned long _metrics; unsigned long expires; struct dst_entry *path; - struct neighbour *_neighbour; + struct neighbour __rcu *_neighbour; #ifdef CONFIG_XFRM struct xfrm_state *xfrm; #else @@ -88,12 +88,17 @@ struct dst_entry { static inline struct neighbour *dst_get_neighbour(struct dst_entry *dst) { - return dst->_neighbour; + return rcu_dereference(dst->_neighbour); +} + +static inline struct neighbour *dst_get_neighbour_raw(struct dst_entry *dst) +{ + return rcu_dereference_raw(dst->_neighbour); } static inline void dst_set_neighbour(struct dst_entry *dst, struct neighbour *neigh) { - dst->_neighbour = neigh; + rcu_assign_pointer(dst->_neighbour, neigh); } extern u32 *dst_cow_metrics_generic(struct dst_entry *dst, unsigned long old); @@ -382,8 +387,12 @@ static inline void dst_rcu_free(struct rcu_head *head) static inline void dst_confirm(struct dst_entry *dst) { if (dst) { - struct neighbour *n = dst_get_neighbour(dst); + struct neighbour *n; + + rcu_read_lock(); + n = dst_get_neighbour(dst); neigh_confirm(n); + rcu_read_unlock(); } } diff --git a/include/net/netlabel.h b/include/net/netlabel.h index f21a16ee3705..f67440970d7e 100644 --- a/include/net/netlabel.h +++ b/include/net/netlabel.h @@ -4,7 +4,7 @@ * The NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/include/net/secure_seq.h b/include/net/secure_seq.h new file mode 100644 index 000000000000..d97f6892c019 --- /dev/null +++ b/include/net/secure_seq.h @@ -0,0 +1,20 @@ +#ifndef _NET_SECURE_SEQ +#define _NET_SECURE_SEQ + +#include <linux/types.h> + +extern __u32 secure_ip_id(__be32 daddr); +extern __u32 secure_ipv6_id(const __be32 daddr[4]); +extern u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); +extern u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, + __be16 dport); +extern __u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr, + __be16 sport, __be16 dport); +extern __u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr, + __be16 sport, __be16 dport); +extern u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr, + __be16 sport, __be16 dport); +extern u64 secure_dccpv6_sequence_number(__be32 *saddr, __be32 *daddr, + __be16 sport, __be16 dport); + +#endif /* _NET_SECURE_SEQ */ diff --git a/include/scsi/osd_ore.h b/include/scsi/osd_ore.h new file mode 100644 index 000000000000..c5c5e008e6de --- /dev/null +++ b/include/scsi/osd_ore.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2011 + * Boaz Harrosh <bharrosh@panasas.com> + * + * Public Declarations of the ORE API + * + * This file is part of the ORE (Object Raid Engine) library. + * + * ORE is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. (GPL v2) + * + * ORE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with the ORE; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ORE_H__ +#define __ORE_H__ + +#include <scsi/osd_initiator.h> +#include <scsi/osd_attributes.h> +#include <scsi/osd_sec.h> +#include <linux/pnfs_osd_xdr.h> + +struct ore_comp { + struct osd_obj_id obj; + u8 cred[OSD_CAP_LEN]; +}; + +struct ore_layout { + /* Our way of looking at the data_map */ + unsigned stripe_unit; + unsigned mirrors_p1; + + unsigned group_width; + u64 group_depth; + unsigned group_count; +}; + +struct ore_components { + unsigned numdevs; /* Num of devices in array */ + /* If @single_comp == EC_SINGLE_COMP, @comps points to a single + * component. else there are @numdevs components + */ + enum EC_COMP_USAGE { + EC_SINGLE_COMP = 0, EC_MULTPLE_COMPS = 0xffffffff + } single_comp; + struct ore_comp *comps; + struct osd_dev **ods; /* osd_dev array */ +}; + +struct ore_io_state; +typedef void (*ore_io_done_fn)(struct ore_io_state *ios, void *private); + +struct ore_io_state { + struct kref kref; + + void *private; + ore_io_done_fn done; + + struct ore_layout *layout; + struct ore_components *comps; + + /* Global read/write IO*/ + loff_t offset; + unsigned long length; + void *kern_buff; + + struct page **pages; + unsigned nr_pages; + unsigned pgbase; + unsigned pages_consumed; + + /* Attributes */ + unsigned in_attr_len; + struct osd_attr *in_attr; + unsigned out_attr_len; + struct osd_attr *out_attr; + + bool reading; + + /* Variable array of size numdevs */ + unsigned numdevs; + struct ore_per_dev_state { + struct osd_request *or; + struct bio *bio; + loff_t offset; + unsigned length; + unsigned dev; + } per_dev[]; +}; + +static inline unsigned ore_io_state_size(unsigned numdevs) +{ + return sizeof(struct ore_io_state) + + sizeof(struct ore_per_dev_state) * numdevs; +} + +/* ore.c */ +int ore_get_rw_state(struct ore_layout *layout, struct ore_components *comps, + bool is_reading, u64 offset, u64 length, + struct ore_io_state **ios); +int ore_get_io_state(struct ore_layout *layout, struct ore_components *comps, + struct ore_io_state **ios); +void ore_put_io_state(struct ore_io_state *ios); + +int ore_check_io(struct ore_io_state *ios, u64 *resid); + +int ore_create(struct ore_io_state *ios); +int ore_remove(struct ore_io_state *ios); +int ore_write(struct ore_io_state *ios); +int ore_read(struct ore_io_state *ios); +int ore_truncate(struct ore_layout *layout, struct ore_components *comps, + u64 size); + +int extract_attr_from_ios(struct ore_io_state *ios, struct osd_attr *attr); + +extern const struct osd_attr g_attr_logical_length; + +#endif diff --git a/include/sound/wm8915.h b/include/sound/wm8996.h index 5817d762f6f3..ea4d88f43975 100644 --- a/include/sound/wm8915.h +++ b/include/sound/wm8996.h @@ -1,5 +1,5 @@ /* - * linux/sound/wm8915.h -- Platform data for WM8915 + * linux/sound/wm8996.h -- Platform data for WM8996 * * Copyright 2011 Wolfson Microelectronics. PLC. * @@ -8,14 +8,14 @@ * published by the Free Software Foundation. */ -#ifndef __LINUX_SND_WM8903_H -#define __LINUX_SND_WM8903_H +#ifndef __LINUX_SND_WM8996_H +#define __LINUX_SND_WM8996_H -enum wm8915_inmode { - WM8915_DIFFERRENTIAL_1 = 0, /* IN1xP - IN1xN */ - WM8915_INVERTING = 1, /* IN1xN */ - WM8915_NON_INVERTING = 2, /* IN1xP */ - WM8915_DIFFERENTIAL_2 = 3, /* IN2xP - IN2xP */ +enum wm8996_inmode { + WM8996_DIFFERRENTIAL_1 = 0, /* IN1xP - IN1xN */ + WM8996_INVERTING = 1, /* IN1xN */ + WM8996_NON_INVERTING = 2, /* IN1xP */ + WM8996_DIFFERENTIAL_2 = 3, /* IN2xP - IN2xP */ }; /** @@ -25,23 +25,23 @@ enum wm8915_inmode { * Configurations are expected to be generated using the ReTune Mobile * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/ */ -struct wm8915_retune_mobile_config { +struct wm8996_retune_mobile_config { const char *name; int rate; u16 regs[20]; }; -#define WM8915_SET_DEFAULT 0x10000 +#define WM8996_SET_DEFAULT 0x10000 -struct wm8915_pdata { +struct wm8996_pdata { int irq_flags; /** Set IRQ trigger flags; default active low */ int ldo_ena; /** GPIO for LDO1; -1 for none */ int micdet_def; /** Default MICDET_SRC/HP1FB_SRC/MICD_BIAS */ - enum wm8915_inmode inl_mode; - enum wm8915_inmode inr_mode; + enum wm8996_inmode inl_mode; + enum wm8996_inmode inr_mode; u32 spkmute_seq; /** Value for register 0x802 */ @@ -49,7 +49,7 @@ struct wm8915_pdata { u32 gpio_default[5]; int num_retune_mobile_cfgs; - struct wm8915_retune_mobile_config *retune_mobile_cfgs; + struct wm8996_retune_mobile_config *retune_mobile_cfgs; }; #endif diff --git a/ipc/shm.c b/ipc/shm.c index b5bae9d945b6..02ecf2c078fc 100644 --- a/ipc/shm.c +++ b/ipc/shm.c @@ -105,9 +105,16 @@ void shm_exit_ns(struct ipc_namespace *ns) } #endif -void __init shm_init (void) +static int __init ipc_ns_init(void) { shm_init_ns(&init_ipc_ns); + return 0; +} + +pure_initcall(ipc_ns_init); + +void __init shm_init (void) +{ ipc_init_proc_interface("sysvipc/shm", #if BITS_PER_LONG <= 32 " key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime rss swap\n", diff --git a/kernel/futex.c b/kernel/futex.c index 0a308970c24a..11cbe052b2e8 100644 --- a/kernel/futex.c +++ b/kernel/futex.c @@ -218,6 +218,8 @@ static void drop_futex_key_refs(union futex_key *key) * @uaddr: virtual address of the futex * @fshared: 0 for a PROCESS_PRIVATE futex, 1 for PROCESS_SHARED * @key: address where result is stored. + * @rw: mapping needs to be read/write (values: VERIFY_READ, + * VERIFY_WRITE) * * Returns a negative error code or 0 * The key words are stored in *key on success. @@ -229,12 +231,12 @@ static void drop_futex_key_refs(union futex_key *key) * lock_page() might sleep, the caller should not hold a spinlock. */ static int -get_futex_key(u32 __user *uaddr, int fshared, union futex_key *key) +get_futex_key(u32 __user *uaddr, int fshared, union futex_key *key, int rw) { unsigned long address = (unsigned long)uaddr; struct mm_struct *mm = current->mm; struct page *page, *page_head; - int err; + int err, ro = 0; /* * The futex address must be "naturally" aligned. @@ -262,8 +264,18 @@ get_futex_key(u32 __user *uaddr, int fshared, union futex_key *key) again: err = get_user_pages_fast(address, 1, 1, &page); + /* + * If write access is not required (eg. FUTEX_WAIT), try + * and get read-only access. + */ + if (err == -EFAULT && rw == VERIFY_READ) { + err = get_user_pages_fast(address, 1, 0, &page); + ro = 1; + } if (err < 0) return err; + else + err = 0; #ifdef CONFIG_TRANSPARENT_HUGEPAGE page_head = page; @@ -305,6 +317,13 @@ again: if (!page_head->mapping) { unlock_page(page_head); put_page(page_head); + /* + * ZERO_PAGE pages don't have a mapping. Avoid a busy loop + * trying to find one. RW mapping would have COW'd (and thus + * have a mapping) so this page is RO and won't ever change. + */ + if ((page_head == ZERO_PAGE(address))) + return -EFAULT; goto again; } @@ -316,6 +335,15 @@ again: * the object not the particular process. */ if (PageAnon(page_head)) { + /* + * A RO anonymous page will never change and thus doesn't make + * sense for futex operations. + */ + if (ro) { + err = -EFAULT; + goto out; + } + key->both.offset |= FUT_OFF_MMSHARED; /* ref taken on mm */ key->private.mm = mm; key->private.address = address; @@ -327,9 +355,10 @@ again: get_futex_key_refs(key); +out: unlock_page(page_head); put_page(page_head); - return 0; + return err; } static inline void put_futex_key(union futex_key *key) @@ -940,7 +969,7 @@ futex_wake(u32 __user *uaddr, unsigned int flags, int nr_wake, u32 bitset) if (!bitset) return -EINVAL; - ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &key); + ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &key, VERIFY_READ); if (unlikely(ret != 0)) goto out; @@ -986,10 +1015,10 @@ futex_wake_op(u32 __user *uaddr1, unsigned int flags, u32 __user *uaddr2, int ret, op_ret; retry: - ret = get_futex_key(uaddr1, flags & FLAGS_SHARED, &key1); + ret = get_futex_key(uaddr1, flags & FLAGS_SHARED, &key1, VERIFY_READ); if (unlikely(ret != 0)) goto out; - ret = get_futex_key(uaddr2, flags & FLAGS_SHARED, &key2); + ret = get_futex_key(uaddr2, flags & FLAGS_SHARED, &key2, VERIFY_WRITE); if (unlikely(ret != 0)) goto out_put_key1; @@ -1243,10 +1272,11 @@ retry: pi_state = NULL; } - ret = get_futex_key(uaddr1, flags & FLAGS_SHARED, &key1); + ret = get_futex_key(uaddr1, flags & FLAGS_SHARED, &key1, VERIFY_READ); if (unlikely(ret != 0)) goto out; - ret = get_futex_key(uaddr2, flags & FLAGS_SHARED, &key2); + ret = get_futex_key(uaddr2, flags & FLAGS_SHARED, &key2, + requeue_pi ? VERIFY_WRITE : VERIFY_READ); if (unlikely(ret != 0)) goto out_put_key1; @@ -1790,7 +1820,7 @@ static int futex_wait_setup(u32 __user *uaddr, u32 val, unsigned int flags, * while the syscall executes. */ retry: - ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &q->key); + ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &q->key, VERIFY_READ); if (unlikely(ret != 0)) return ret; @@ -1941,7 +1971,7 @@ static int futex_lock_pi(u32 __user *uaddr, unsigned int flags, int detect, } retry: - ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &q.key); + ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &q.key, VERIFY_WRITE); if (unlikely(ret != 0)) goto out; @@ -2060,7 +2090,7 @@ retry: if ((uval & FUTEX_TID_MASK) != vpid) return -EPERM; - ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &key); + ret = get_futex_key(uaddr, flags & FLAGS_SHARED, &key, VERIFY_WRITE); if (unlikely(ret != 0)) goto out; @@ -2249,7 +2279,7 @@ static int futex_wait_requeue_pi(u32 __user *uaddr, unsigned int flags, debug_rt_mutex_init_waiter(&rt_waiter); rt_waiter.task = NULL; - ret = get_futex_key(uaddr2, flags & FLAGS_SHARED, &key2); + ret = get_futex_key(uaddr2, flags & FLAGS_SHARED, &key2, VERIFY_WRITE); if (unlikely(ret != 0)) goto out; diff --git a/kernel/lockdep.c b/kernel/lockdep.c index 3956f5149e25..8c24294e477f 100644 --- a/kernel/lockdep.c +++ b/kernel/lockdep.c @@ -2468,7 +2468,7 @@ mark_held_locks(struct task_struct *curr, enum mark_type mark) BUG_ON(usage_bit >= LOCK_USAGE_STATES); - if (hlock_class(hlock)->key == &__lockdep_no_validate__) + if (hlock_class(hlock)->key == __lockdep_no_validate__.subkeys) continue; if (!mark_lock(curr, hlock, usage_bit)) @@ -2485,23 +2485,9 @@ static void __trace_hardirqs_on_caller(unsigned long ip) { struct task_struct *curr = current; - if (DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled))) - return; - - if (unlikely(curr->hardirqs_enabled)) { - /* - * Neither irq nor preemption are disabled here - * so this is racy by nature but losing one hit - * in a stat is not a big deal. - */ - __debug_atomic_inc(redundant_hardirqs_on); - return; - } /* we'll do an OFF -> ON transition: */ curr->hardirqs_enabled = 1; - if (DEBUG_LOCKS_WARN_ON(current->hardirq_context)) - return; /* * We are going to turn hardirqs on, so set the * usage bit for all held locks: @@ -2529,9 +2515,25 @@ void trace_hardirqs_on_caller(unsigned long ip) if (unlikely(!debug_locks || current->lockdep_recursion)) return; + if (unlikely(current->hardirqs_enabled)) { + /* + * Neither irq nor preemption are disabled here + * so this is racy by nature but losing one hit + * in a stat is not a big deal. + */ + __debug_atomic_inc(redundant_hardirqs_on); + return; + } + if (DEBUG_LOCKS_WARN_ON(!irqs_disabled())) return; + if (DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled))) + return; + + if (DEBUG_LOCKS_WARN_ON(current->hardirq_context)) + return; + current->lockdep_recursion = 1; __trace_hardirqs_on_caller(ip); current->lockdep_recursion = 0; @@ -2872,10 +2874,7 @@ static int mark_lock(struct task_struct *curr, struct held_lock *this, void lockdep_init_map(struct lockdep_map *lock, const char *name, struct lock_class_key *key, int subclass) { - int i; - - for (i = 0; i < NR_LOCKDEP_CACHING_CLASSES; i++) - lock->class_cache[i] = NULL; + memset(lock, 0, sizeof(*lock)); #ifdef CONFIG_LOCK_STAT lock->cpu = raw_smp_processor_id(); diff --git a/kernel/printk.c b/kernel/printk.c index 37dff3429adb..836a2ae0ac31 100644 --- a/kernel/printk.c +++ b/kernel/printk.c @@ -318,8 +318,10 @@ static int check_syslog_permissions(int type, bool from_file) return 0; /* For historical reasons, accept CAP_SYS_ADMIN too, with a warning */ if (capable(CAP_SYS_ADMIN)) { - WARN_ONCE(1, "Attempt to access syslog with CAP_SYS_ADMIN " - "but no CAP_SYSLOG (deprecated).\n"); + printk_once(KERN_WARNING "%s (%d): " + "Attempt to access syslog with CAP_SYS_ADMIN " + "but no CAP_SYSLOG (deprecated).\n", + current->comm, task_pid_nr(current)); return 0; } return -EPERM; diff --git a/lib/Makefile b/lib/Makefile index 6457af4a7caf..d5d175c8a6ca 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -10,7 +10,7 @@ endif lib-y := ctype.o string.o vsprintf.o cmdline.o \ rbtree.o radix-tree.o dump_stack.o timerqueue.o\ idr.o int_sqrt.o extable.o prio_tree.o \ - sha1.o irq_regs.o reciprocal_div.o argv_split.o \ + sha1.o md5.o irq_regs.o reciprocal_div.o argv_split.o \ proportions.o prio_heap.o ratelimit.o show_mem.o \ is_single_threaded.o plist.o decompress.o find_next_bit.o diff --git a/lib/md5.c b/lib/md5.c new file mode 100644 index 000000000000..c777180e1f2f --- /dev/null +++ b/lib/md5.c @@ -0,0 +1,95 @@ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/cryptohash.h> + +#define F1(x, y, z) (z ^ (x & (y ^ z))) +#define F2(x, y, z) F1(z, x, y) +#define F3(x, y, z) (x ^ y ^ z) +#define F4(x, y, z) (y ^ (x | ~z)) + +#define MD5STEP(f, w, x, y, z, in, s) \ + (w += f(x, y, z) + in, w = (w<<s | w>>(32-s)) + x) + +void md5_transform(__u32 *hash, __u32 const *in) +{ + u32 a, b, c, d; + + a = hash[0]; + b = hash[1]; + c = hash[2]; + d = hash[3]; + + MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); + MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); + MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); + MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); + MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); + MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); + MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); + MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); + MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); + MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); + MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); + MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); + MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); + MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); + MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); + MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); + + MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); + MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); + MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); + MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); + MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); + MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); + MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); + MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); + MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); + MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); + MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); + MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); + MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); + MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); + MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); + MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); + + MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); + MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); + MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); + MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); + MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); + MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); + MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); + MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); + MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); + MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); + MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); + MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); + MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); + MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); + MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); + MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); + + MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); + MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); + MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); + MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); + MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); + MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); + MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); + MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); + MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); + MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); + MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); + MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); + MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); + MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); + MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); + MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); + + hash[0] += a; + hash[1] += b; + hash[2] += c; + hash[3] += d; +} +EXPORT_SYMBOL(md5_transform); diff --git a/lib/sha1.c b/lib/sha1.c index 4c45fd50e913..f33271dd00cb 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -1,31 +1,72 @@ /* - * SHA transform algorithm, originally taken from code written by - * Peter Gutmann, and placed in the public domain. + * SHA1 routine optimized to do word accesses rather than byte accesses, + * and to avoid unnecessary copies into the context array. + * + * This was based on the git SHA1 implementation. */ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/cryptohash.h> +#include <linux/bitops.h> +#include <asm/unaligned.h> -/* The SHA f()-functions. */ +/* + * If you have 32 registers or more, the compiler can (and should) + * try to change the array[] accesses into registers. However, on + * machines with less than ~25 registers, that won't really work, + * and at least gcc will make an unholy mess of it. + * + * So to avoid that mess which just slows things down, we force + * the stores to memory to actually happen (we might be better off + * with a 'W(t)=(val);asm("":"+m" (W(t))' there instead, as + * suggested by Artur Skawina - that will also make gcc unable to + * try to do the silly "optimize away loads" part because it won't + * see what the value will be). + * + * Ben Herrenschmidt reports that on PPC, the C version comes close + * to the optimized asm with this (ie on PPC you don't want that + * 'volatile', since there are lots of registers). + * + * On ARM we get the best code generation by forcing a full memory barrier + * between each SHA_ROUND, otherwise gcc happily get wild with spilling and + * the stack frame size simply explode and performance goes down the drain. + */ -#define f1(x,y,z) (z ^ (x & (y ^ z))) /* x ? y : z */ -#define f2(x,y,z) (x ^ y ^ z) /* XOR */ -#define f3(x,y,z) ((x & y) + (z & (x ^ y))) /* majority */ +#ifdef CONFIG_X86 + #define setW(x, val) (*(volatile __u32 *)&W(x) = (val)) +#elif defined(CONFIG_ARM) + #define setW(x, val) do { W(x) = (val); __asm__("":::"memory"); } while (0) +#else + #define setW(x, val) (W(x) = (val)) +#endif -/* The SHA Mysterious Constants */ +/* This "rolls" over the 512-bit array */ +#define W(x) (array[(x)&15]) -#define K1 0x5A827999L /* Rounds 0-19: sqrt(2) * 2^30 */ -#define K2 0x6ED9EBA1L /* Rounds 20-39: sqrt(3) * 2^30 */ -#define K3 0x8F1BBCDCL /* Rounds 40-59: sqrt(5) * 2^30 */ -#define K4 0xCA62C1D6L /* Rounds 60-79: sqrt(10) * 2^30 */ +/* + * Where do we get the source from? The first 16 iterations get it from + * the input data, the next mix it from the 512-bit array. + */ +#define SHA_SRC(t) get_unaligned_be32((__u32 *)data + t) +#define SHA_MIX(t) rol32(W(t+13) ^ W(t+8) ^ W(t+2) ^ W(t), 1) + +#define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ + __u32 TEMP = input(t); setW(t, TEMP); \ + E += TEMP + rol32(A,5) + (fn) + (constant); \ + B = ror32(B, 2); } while (0) + +#define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) +#define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) +#define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) +#define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D, E ) +#define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) /** * sha_transform - single block SHA1 transform * * @digest: 160 bit digest to update * @data: 512 bits of data to hash - * @W: 80 words of workspace (see note) + * @array: 16 words of workspace (see note) * * This function generates a SHA1 digest for a single 512-bit block. * Be warned, it does not handle padding and message digest, do not @@ -36,47 +77,111 @@ * to clear the workspace. This is left to the caller to avoid * unnecessary clears between chained hashing operations. */ -void sha_transform(__u32 *digest, const char *in, __u32 *W) +void sha_transform(__u32 *digest, const char *data, __u32 *array) { - __u32 a, b, c, d, e, t, i; - - for (i = 0; i < 16; i++) - W[i] = be32_to_cpu(((const __be32 *)in)[i]); - - for (i = 0; i < 64; i++) - W[i+16] = rol32(W[i+13] ^ W[i+8] ^ W[i+2] ^ W[i], 1); - - a = digest[0]; - b = digest[1]; - c = digest[2]; - d = digest[3]; - e = digest[4]; - - for (i = 0; i < 20; i++) { - t = f1(b, c, d) + K1 + rol32(a, 5) + e + W[i]; - e = d; d = c; c = rol32(b, 30); b = a; a = t; - } - - for (; i < 40; i ++) { - t = f2(b, c, d) + K2 + rol32(a, 5) + e + W[i]; - e = d; d = c; c = rol32(b, 30); b = a; a = t; - } - - for (; i < 60; i ++) { - t = f3(b, c, d) + K3 + rol32(a, 5) + e + W[i]; - e = d; d = c; c = rol32(b, 30); b = a; a = t; - } - - for (; i < 80; i ++) { - t = f2(b, c, d) + K4 + rol32(a, 5) + e + W[i]; - e = d; d = c; c = rol32(b, 30); b = a; a = t; - } - - digest[0] += a; - digest[1] += b; - digest[2] += c; - digest[3] += d; - digest[4] += e; + __u32 A, B, C, D, E; + + A = digest[0]; + B = digest[1]; + C = digest[2]; + D = digest[3]; + E = digest[4]; + + /* Round 1 - iterations 0-16 take their input from 'data' */ + T_0_15( 0, A, B, C, D, E); + T_0_15( 1, E, A, B, C, D); + T_0_15( 2, D, E, A, B, C); + T_0_15( 3, C, D, E, A, B); + T_0_15( 4, B, C, D, E, A); + T_0_15( 5, A, B, C, D, E); + T_0_15( 6, E, A, B, C, D); + T_0_15( 7, D, E, A, B, C); + T_0_15( 8, C, D, E, A, B); + T_0_15( 9, B, C, D, E, A); + T_0_15(10, A, B, C, D, E); + T_0_15(11, E, A, B, C, D); + T_0_15(12, D, E, A, B, C); + T_0_15(13, C, D, E, A, B); + T_0_15(14, B, C, D, E, A); + T_0_15(15, A, B, C, D, E); + + /* Round 1 - tail. Input from 512-bit mixing array */ + T_16_19(16, E, A, B, C, D); + T_16_19(17, D, E, A, B, C); + T_16_19(18, C, D, E, A, B); + T_16_19(19, B, C, D, E, A); + + /* Round 2 */ + T_20_39(20, A, B, C, D, E); + T_20_39(21, E, A, B, C, D); + T_20_39(22, D, E, A, B, C); + T_20_39(23, C, D, E, A, B); + T_20_39(24, B, C, D, E, A); + T_20_39(25, A, B, C, D, E); + T_20_39(26, E, A, B, C, D); + T_20_39(27, D, E, A, B, C); + T_20_39(28, C, D, E, A, B); + T_20_39(29, B, C, D, E, A); + T_20_39(30, A, B, C, D, E); + T_20_39(31, E, A, B, C, D); + T_20_39(32, D, E, A, B, C); + T_20_39(33, C, D, E, A, B); + T_20_39(34, B, C, D, E, A); + T_20_39(35, A, B, C, D, E); + T_20_39(36, E, A, B, C, D); + T_20_39(37, D, E, A, B, C); + T_20_39(38, C, D, E, A, B); + T_20_39(39, B, C, D, E, A); + + /* Round 3 */ + T_40_59(40, A, B, C, D, E); + T_40_59(41, E, A, B, C, D); + T_40_59(42, D, E, A, B, C); + T_40_59(43, C, D, E, A, B); + T_40_59(44, B, C, D, E, A); + T_40_59(45, A, B, C, D, E); + T_40_59(46, E, A, B, C, D); + T_40_59(47, D, E, A, B, C); + T_40_59(48, C, D, E, A, B); + T_40_59(49, B, C, D, E, A); + T_40_59(50, A, B, C, D, E); + T_40_59(51, E, A, B, C, D); + T_40_59(52, D, E, A, B, C); + T_40_59(53, C, D, E, A, B); + T_40_59(54, B, C, D, E, A); + T_40_59(55, A, B, C, D, E); + T_40_59(56, E, A, B, C, D); + T_40_59(57, D, E, A, B, C); + T_40_59(58, C, D, E, A, B); + T_40_59(59, B, C, D, E, A); + + /* Round 4 */ + T_60_79(60, A, B, C, D, E); + T_60_79(61, E, A, B, C, D); + T_60_79(62, D, E, A, B, C); + T_60_79(63, C, D, E, A, B); + T_60_79(64, B, C, D, E, A); + T_60_79(65, A, B, C, D, E); + T_60_79(66, E, A, B, C, D); + T_60_79(67, D, E, A, B, C); + T_60_79(68, C, D, E, A, B); + T_60_79(69, B, C, D, E, A); + T_60_79(70, A, B, C, D, E); + T_60_79(71, E, A, B, C, D); + T_60_79(72, D, E, A, B, C); + T_60_79(73, C, D, E, A, B); + T_60_79(74, B, C, D, E, A); + T_60_79(75, A, B, C, D, E); + T_60_79(76, E, A, B, C, D); + T_60_79(77, D, E, A, B, C); + T_60_79(78, C, D, E, A, B); + T_60_79(79, B, C, D, E, A); + + digest[0] += A; + digest[1] += B; + digest[2] += C; + digest[3] += D; + digest[4] += E; } EXPORT_SYMBOL(sha_transform); @@ -92,4 +197,3 @@ void sha_init(__u32 *buf) buf[3] = 0x10325476; buf[4] = 0xc3d2e1f0; } - diff --git a/mm/memcontrol.c b/mm/memcontrol.c index f4ec4e7ca4cd..930de9437271 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -2091,6 +2091,7 @@ struct memcg_stock_pcp { #define FLUSHING_CACHED_CHARGE (0) }; static DEFINE_PER_CPU(struct memcg_stock_pcp, memcg_stock); +static DEFINE_MUTEX(percpu_charge_mutex); /* * Try to consume stocked charge on this cpu. If success, one page is consumed @@ -2197,8 +2198,7 @@ static void drain_all_stock(struct mem_cgroup *root_mem, bool sync) for_each_online_cpu(cpu) { struct memcg_stock_pcp *stock = &per_cpu(memcg_stock, cpu); - if (mem_cgroup_same_or_subtree(root_mem, stock->cached) && - test_bit(FLUSHING_CACHED_CHARGE, &stock->flags)) + if (test_bit(FLUSHING_CACHED_CHARGE, &stock->flags)) flush_work(&stock->work); } out: @@ -2213,14 +2213,22 @@ out: */ static void drain_all_stock_async(struct mem_cgroup *root_mem) { + /* + * If someone calls draining, avoid adding more kworker runs. + */ + if (!mutex_trylock(&percpu_charge_mutex)) + return; drain_all_stock(root_mem, false); + mutex_unlock(&percpu_charge_mutex); } /* This is a synchronous drain interface. */ static void drain_all_stock_sync(struct mem_cgroup *root_mem) { /* called when force_empty is called */ + mutex_lock(&percpu_charge_mutex); drain_all_stock(root_mem, true); + mutex_unlock(&percpu_charge_mutex); } /* diff --git a/mm/slab.c b/mm/slab.c index 95947400702b..6d90a091fdca 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -622,6 +622,51 @@ int slab_is_available(void) static struct lock_class_key on_slab_l3_key; static struct lock_class_key on_slab_alc_key; +static struct lock_class_key debugobj_l3_key; +static struct lock_class_key debugobj_alc_key; + +static void slab_set_lock_classes(struct kmem_cache *cachep, + struct lock_class_key *l3_key, struct lock_class_key *alc_key, + int q) +{ + struct array_cache **alc; + struct kmem_list3 *l3; + int r; + + l3 = cachep->nodelists[q]; + if (!l3) + return; + + lockdep_set_class(&l3->list_lock, l3_key); + alc = l3->alien; + /* + * FIXME: This check for BAD_ALIEN_MAGIC + * should go away when common slab code is taught to + * work even without alien caches. + * Currently, non NUMA code returns BAD_ALIEN_MAGIC + * for alloc_alien_cache, + */ + if (!alc || (unsigned long)alc == BAD_ALIEN_MAGIC) + return; + for_each_node(r) { + if (alc[r]) + lockdep_set_class(&alc[r]->lock, alc_key); + } +} + +static void slab_set_debugobj_lock_classes_node(struct kmem_cache *cachep, int node) +{ + slab_set_lock_classes(cachep, &debugobj_l3_key, &debugobj_alc_key, node); +} + +static void slab_set_debugobj_lock_classes(struct kmem_cache *cachep) +{ + int node; + + for_each_online_node(node) + slab_set_debugobj_lock_classes_node(cachep, node); +} + static void init_node_lock_keys(int q) { struct cache_sizes *s = malloc_sizes; @@ -630,29 +675,14 @@ static void init_node_lock_keys(int q) return; for (s = malloc_sizes; s->cs_size != ULONG_MAX; s++) { - struct array_cache **alc; struct kmem_list3 *l3; - int r; l3 = s->cs_cachep->nodelists[q]; if (!l3 || OFF_SLAB(s->cs_cachep)) continue; - lockdep_set_class(&l3->list_lock, &on_slab_l3_key); - alc = l3->alien; - /* - * FIXME: This check for BAD_ALIEN_MAGIC - * should go away when common slab code is taught to - * work even without alien caches. - * Currently, non NUMA code returns BAD_ALIEN_MAGIC - * for alloc_alien_cache, - */ - if (!alc || (unsigned long)alc == BAD_ALIEN_MAGIC) - continue; - for_each_node(r) { - if (alc[r]) - lockdep_set_class(&alc[r]->lock, - &on_slab_alc_key); - } + + slab_set_lock_classes(s->cs_cachep, &on_slab_l3_key, + &on_slab_alc_key, q); } } @@ -671,6 +701,14 @@ static void init_node_lock_keys(int q) static inline void init_lock_keys(void) { } + +static void slab_set_debugobj_lock_classes_node(struct kmem_cache *cachep, int node) +{ +} + +static void slab_set_debugobj_lock_classes(struct kmem_cache *cachep) +{ +} #endif /* @@ -1264,6 +1302,8 @@ static int __cpuinit cpuup_prepare(long cpu) spin_unlock_irq(&l3->list_lock); kfree(shared); free_alien_cache(alien); + if (cachep->flags & SLAB_DEBUG_OBJECTS) + slab_set_debugobj_lock_classes_node(cachep, node); } init_node_lock_keys(node); @@ -1626,6 +1666,9 @@ void __init kmem_cache_init_late(void) { struct kmem_cache *cachep; + /* Annotate slab for lockdep -- annotate the malloc caches */ + init_lock_keys(); + /* 6) resize the head arrays to their final sizes */ mutex_lock(&cache_chain_mutex); list_for_each_entry(cachep, &cache_chain, next) @@ -1636,9 +1679,6 @@ void __init kmem_cache_init_late(void) /* Done! */ g_cpucache_up = FULL; - /* Annotate slab for lockdep -- annotate the malloc caches */ - init_lock_keys(); - /* * Register a cpu startup notifier callback that initializes * cpu_cache_get for all new cpus @@ -2426,6 +2466,16 @@ kmem_cache_create (const char *name, size_t size, size_t align, goto oops; } + if (flags & SLAB_DEBUG_OBJECTS) { + /* + * Would deadlock through slab_destroy()->call_rcu()-> + * debug_object_activate()->kmem_cache_alloc(). + */ + WARN_ON_ONCE(flags & SLAB_DESTROY_BY_RCU); + + slab_set_debugobj_lock_classes(cachep); + } + /* cache setup completed, link it into the list */ list_add(&cachep->next, &cache_chain); oops: diff --git a/mm/slub.c b/mm/slub.c index eb5a8f93338a..9f662d70eb47 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -701,7 +701,7 @@ static u8 *check_bytes(u8 *start, u8 value, unsigned int bytes) return check_bytes8(start, value, bytes); value64 = value | value << 8 | value << 16 | value << 24; - value64 = value64 | value64 << 32; + value64 = (value64 & 0xffffffff) | value64 << 32; prefix = 8 - ((unsigned long)start) % 8; if (prefix) { @@ -1854,7 +1854,7 @@ redo: new.frozen = 0; - if (!new.inuse && n->nr_partial < s->min_partial) + if (!new.inuse && n->nr_partial > s->min_partial) m = M_FREE; else if (new.freelist) { m = M_PARTIAL; @@ -2387,11 +2387,13 @@ static void __slab_free(struct kmem_cache *s, struct page *page, slab_empty: if (prior) { /* - * Slab still on the partial list. + * Slab on the partial list. */ remove_partial(n, page); stat(s, FREE_REMOVE_PARTIAL); - } + } else + /* Slab must be on the full list */ + remove_full(s, page); spin_unlock_irqrestore(&n->list_lock, flags); stat(s, FREE_SLAB); diff --git a/net/atm/br2684.c b/net/atm/br2684.c index 2252c2085dac..52cfd0c3ea71 100644 --- a/net/atm/br2684.c +++ b/net/atm/br2684.c @@ -242,8 +242,6 @@ static int br2684_xmit_vcc(struct sk_buff *skb, struct net_device *dev, if (brdev->payload == p_bridged) { skb_push(skb, 2); memset(skb->data, 0, 2); - } else { /* p_routed */ - skb_pull(skb, ETH_HLEN); } } skb_debug(skb); diff --git a/net/core/Makefile b/net/core/Makefile index 8a04dd22cf77..0d357b1c4e57 100644 --- a/net/core/Makefile +++ b/net/core/Makefile @@ -3,7 +3,7 @@ # obj-y := sock.o request_sock.o skbuff.o iovec.o datagram.o stream.o scm.o \ - gen_stats.o gen_estimator.o net_namespace.o + gen_stats.o gen_estimator.o net_namespace.o secure_seq.o obj-$(CONFIG_SYSCTL) += sysctl_net_core.o diff --git a/net/core/secure_seq.c b/net/core/secure_seq.c new file mode 100644 index 000000000000..45329d7c9dd9 --- /dev/null +++ b/net/core/secure_seq.c @@ -0,0 +1,184 @@ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/cryptohash.h> +#include <linux/module.h> +#include <linux/cache.h> +#include <linux/random.h> +#include <linux/hrtimer.h> +#include <linux/ktime.h> +#include <linux/string.h> + +#include <net/secure_seq.h> + +static u32 net_secret[MD5_MESSAGE_BYTES / 4] ____cacheline_aligned; + +static int __init net_secret_init(void) +{ + get_random_bytes(net_secret, sizeof(net_secret)); + return 0; +} +late_initcall(net_secret_init); + +static u32 seq_scale(u32 seq) +{ + /* + * As close as possible to RFC 793, which + * suggests using a 250 kHz clock. + * Further reading shows this assumes 2 Mb/s networks. + * For 10 Mb/s Ethernet, a 1 MHz clock is appropriate. + * For 10 Gb/s Ethernet, a 1 GHz clock should be ok, but + * we also need to limit the resolution so that the u32 seq + * overlaps less than one time per MSL (2 minutes). + * Choosing a clock of 64 ns period is OK. (period of 274 s) + */ + return seq + (ktime_to_ns(ktime_get_real()) >> 6); +} + +#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) +__u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr, + __be16 sport, __be16 dport) +{ + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u32 i; + + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) + secret[i] = net_secret[i] + daddr[i]; + secret[4] = net_secret[4] + + (((__force u16)sport << 16) + (__force u16)dport); + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) + secret[i] = net_secret[i]; + + md5_transform(hash, secret); + + return seq_scale(hash[0]); +} +EXPORT_SYMBOL(secure_tcpv6_sequence_number); + +u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, + __be16 dport) +{ + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u32 i; + + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) + secret[i] = net_secret[i] + (__force u32) daddr[i]; + secret[4] = net_secret[4] + (__force u32)dport; + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) + secret[i] = net_secret[i]; + + md5_transform(hash, secret); + + return hash[0]; +} +#endif + +#ifdef CONFIG_INET +__u32 secure_ip_id(__be32 daddr) +{ + u32 hash[MD5_DIGEST_WORDS]; + + hash[0] = (__force __u32) daddr; + hash[1] = net_secret[13]; + hash[2] = net_secret[14]; + hash[3] = net_secret[15]; + + md5_transform(hash, net_secret); + + return hash[0]; +} + +__u32 secure_ipv6_id(const __be32 daddr[4]) +{ + __u32 hash[4]; + + memcpy(hash, daddr, 16); + md5_transform(hash, net_secret); + + return hash[0]; +} + +__u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr, + __be16 sport, __be16 dport) +{ + u32 hash[MD5_DIGEST_WORDS]; + + hash[0] = (__force u32)saddr; + hash[1] = (__force u32)daddr; + hash[2] = ((__force u16)sport << 16) + (__force u16)dport; + hash[3] = net_secret[15]; + + md5_transform(hash, net_secret); + + return seq_scale(hash[0]); +} + +u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport) +{ + u32 hash[MD5_DIGEST_WORDS]; + + hash[0] = (__force u32)saddr; + hash[1] = (__force u32)daddr; + hash[2] = (__force u32)dport ^ net_secret[14]; + hash[3] = net_secret[15]; + + md5_transform(hash, net_secret); + + return hash[0]; +} +EXPORT_SYMBOL_GPL(secure_ipv4_port_ephemeral); +#endif + +#if defined(CONFIG_IP_DCCP) || defined(CONFIG_IP_DCCP_MODULE) +u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr, + __be16 sport, __be16 dport) +{ + u32 hash[MD5_DIGEST_WORDS]; + u64 seq; + + hash[0] = (__force u32)saddr; + hash[1] = (__force u32)daddr; + hash[2] = ((__force u16)sport << 16) + (__force u16)dport; + hash[3] = net_secret[15]; + + md5_transform(hash, net_secret); + + seq = hash[0] | (((u64)hash[1]) << 32); + seq += ktime_to_ns(ktime_get_real()); + seq &= (1ull << 48) - 1; + + return seq; +} +EXPORT_SYMBOL(secure_dccp_sequence_number); + +#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) +u64 secure_dccpv6_sequence_number(__be32 *saddr, __be32 *daddr, + __be16 sport, __be16 dport) +{ + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u64 seq; + u32 i; + + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) + secret[i] = net_secret[i] + daddr[i]; + secret[4] = net_secret[4] + + (((__force u16)sport << 16) + (__force u16)dport); + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) + secret[i] = net_secret[i]; + + md5_transform(hash, secret); + + seq = hash[0] | (((u64)hash[1]) << 32); + seq += ktime_to_ns(ktime_get_real()); + seq &= (1ull << 48) - 1; + + return seq; +} +EXPORT_SYMBOL(secure_dccpv6_sequence_number); +#endif +#endif diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 2beda824636e..27002dffe7ed 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -1369,8 +1369,21 @@ pull_pages: } EXPORT_SYMBOL(__pskb_pull_tail); -/* Copy some data bits from skb to kernel buffer. */ - +/** + * skb_copy_bits - copy bits from skb to kernel buffer + * @skb: source skb + * @offset: offset in source + * @to: destination buffer + * @len: number of bytes to copy + * + * Copy the specified number of bytes from the source skb to the + * destination buffer. + * + * CAUTION ! : + * If its prototype is ever changed, + * check arch/{*}/net/{*}.S files, + * since it is called from BPF assembly code. + */ int skb_copy_bits(const struct sk_buff *skb, int offset, void *to, int len) { int start = skb_headlen(skb); diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c index 8c36adfd1919..332639b56f4d 100644 --- a/net/dccp/ipv4.c +++ b/net/dccp/ipv4.c @@ -26,6 +26,7 @@ #include <net/timewait_sock.h> #include <net/tcp_states.h> #include <net/xfrm.h> +#include <net/secure_seq.h> #include "ackvec.h" #include "ccid.h" diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c index 8dc4348774a5..b74f76117dcf 100644 --- a/net/dccp/ipv6.c +++ b/net/dccp/ipv6.c @@ -29,6 +29,7 @@ #include <net/transp_v6.h> #include <net/ip6_checksum.h> #include <net/xfrm.h> +#include <net/secure_seq.h> #include "dccp.h" #include "ipv6.h" @@ -69,13 +70,7 @@ static inline void dccp_v6_send_check(struct sock *sk, struct sk_buff *skb) dh->dccph_checksum = dccp_v6_csum_finish(skb, &np->saddr, &np->daddr); } -static inline __u32 secure_dccpv6_sequence_number(__be32 *saddr, __be32 *daddr, - __be16 sport, __be16 dport ) -{ - return secure_tcpv6_sequence_number(saddr, daddr, sport, dport); -} - -static inline __u32 dccp_v6_init_sequence(struct sk_buff *skb) +static inline __u64 dccp_v6_init_sequence(struct sk_buff *skb) { return secure_dccpv6_sequence_number(ipv6_hdr(skb)->daddr.s6_addr32, ipv6_hdr(skb)->saddr.s6_addr32, diff --git a/net/ipv4/igmp.c b/net/ipv4/igmp.c index f1d27f6c9351..283c0a26e03f 100644 --- a/net/ipv4/igmp.c +++ b/net/ipv4/igmp.c @@ -1718,7 +1718,7 @@ static int ip_mc_add_src(struct in_device *in_dev, __be32 *pmca, int sfmode, pmc->sfcount[sfmode]--; for (j=0; j<i; j++) - (void) ip_mc_del1_src(pmc, sfmode, &psfsrc[i]); + (void) ip_mc_del1_src(pmc, sfmode, &psfsrc[j]); } else if (isexclude != (pmc->sfcount[MCAST_EXCLUDE] != 0)) { #ifdef CONFIG_IP_MULTICAST struct ip_sf_list *psf; diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c index 3c0369a3a663..984ec656b03b 100644 --- a/net/ipv4/inet_hashtables.c +++ b/net/ipv4/inet_hashtables.c @@ -21,6 +21,7 @@ #include <net/inet_connection_sock.h> #include <net/inet_hashtables.h> +#include <net/secure_seq.h> #include <net/ip.h> /* diff --git a/net/ipv4/inetpeer.c b/net/ipv4/inetpeer.c index e38213817d0a..86f13c67ea85 100644 --- a/net/ipv4/inetpeer.c +++ b/net/ipv4/inetpeer.c @@ -19,6 +19,7 @@ #include <linux/net.h> #include <net/ip.h> #include <net/inetpeer.h> +#include <net/secure_seq.h> /* * Theory of operations. diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c index ccaaa851ab42..77d3eded665a 100644 --- a/net/ipv4/ip_output.c +++ b/net/ipv4/ip_output.c @@ -204,9 +204,15 @@ static inline int ip_finish_output2(struct sk_buff *skb) skb = skb2; } + rcu_read_lock(); neigh = dst_get_neighbour(dst); - if (neigh) - return neigh_output(neigh, skb); + if (neigh) { + int res = neigh_output(neigh, skb); + + rcu_read_unlock(); + return res; + } + rcu_read_unlock(); if (net_ratelimit()) printk(KERN_DEBUG "ip_finish_output2: No header cache and no neighbour!\n"); diff --git a/net/ipv4/netfilter/nf_nat_proto_common.c b/net/ipv4/netfilter/nf_nat_proto_common.c index 3e61faf23a9a..f52d41ea0690 100644 --- a/net/ipv4/netfilter/nf_nat_proto_common.c +++ b/net/ipv4/netfilter/nf_nat_proto_common.c @@ -12,6 +12,7 @@ #include <linux/ip.h> #include <linux/netfilter.h> +#include <net/secure_seq.h> #include <net/netfilter/nf_nat.h> #include <net/netfilter/nf_nat_core.h> #include <net/netfilter/nf_nat_rule.h> diff --git a/net/ipv4/route.c b/net/ipv4/route.c index 1730689f560e..e3dec1c9f09d 100644 --- a/net/ipv4/route.c +++ b/net/ipv4/route.c @@ -109,6 +109,7 @@ #include <linux/sysctl.h> #endif #include <net/atmclip.h> +#include <net/secure_seq.h> #define RT_FL_TOS(oldflp4) \ ((u32)(oldflp4->flowi4_tos & (IPTOS_RT_MASK | RTO_ONLINK))) @@ -1628,16 +1629,18 @@ static int check_peer_redir(struct dst_entry *dst, struct inet_peer *peer) { struct rtable *rt = (struct rtable *) dst; __be32 orig_gw = rt->rt_gateway; - struct neighbour *n; + struct neighbour *n, *old_n; dst_confirm(&rt->dst); - neigh_release(dst_get_neighbour(&rt->dst)); - dst_set_neighbour(&rt->dst, NULL); - rt->rt_gateway = peer->redirect_learned.a4; - rt_bind_neighbour(rt); - n = dst_get_neighbour(&rt->dst); + + n = ipv4_neigh_lookup(&rt->dst, &rt->rt_gateway); + if (IS_ERR(n)) + return PTR_ERR(n); + old_n = xchg(&rt->dst._neighbour, n); + if (old_n) + neigh_release(old_n); if (!n || !(n->nud_state & NUD_VALID)) { if (n) neigh_event_send(n, NULL); diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 955b8e65b69e..1c12b8ec849d 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -72,6 +72,7 @@ #include <net/timewait_sock.h> #include <net/xfrm.h> #include <net/netdma.h> +#include <net/secure_seq.h> #include <linux/inet.h> #include <linux/ipv6.h> diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index a55500cc0b29..f012ebd87b43 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -656,7 +656,7 @@ ipv6_add_addr(struct inet6_dev *idev, const struct in6_addr *addr, int pfxlen, * layer address of our nexhop router */ - if (dst_get_neighbour(&rt->dst) == NULL) + if (dst_get_neighbour_raw(&rt->dst) == NULL) ifa->flags &= ~IFA_F_OPTIMISTIC; ifa->idev = idev; diff --git a/net/ipv6/datagram.c b/net/ipv6/datagram.c index 16560336eb72..9ef1831746ef 100644 --- a/net/ipv6/datagram.c +++ b/net/ipv6/datagram.c @@ -33,6 +33,11 @@ #include <linux/errqueue.h> #include <asm/uaccess.h> +static inline int ipv6_mapped_addr_any(const struct in6_addr *a) +{ + return (ipv6_addr_v4mapped(a) && (a->s6_addr32[3] == 0)); +} + int ip6_datagram_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len) { struct sockaddr_in6 *usin = (struct sockaddr_in6 *) uaddr; @@ -102,10 +107,12 @@ ipv4_connected: ipv6_addr_set_v4mapped(inet->inet_daddr, &np->daddr); - if (ipv6_addr_any(&np->saddr)) + if (ipv6_addr_any(&np->saddr) || + ipv6_mapped_addr_any(&np->saddr)) ipv6_addr_set_v4mapped(inet->inet_saddr, &np->saddr); - if (ipv6_addr_any(&np->rcv_saddr)) { + if (ipv6_addr_any(&np->rcv_saddr) || + ipv6_mapped_addr_any(&np->rcv_saddr)) { ipv6_addr_set_v4mapped(inet->inet_rcv_saddr, &np->rcv_saddr); if (sk->sk_prot->rehash) diff --git a/net/ipv6/inet6_hashtables.c b/net/ipv6/inet6_hashtables.c index b53197233709..73f1a00a96af 100644 --- a/net/ipv6/inet6_hashtables.c +++ b/net/ipv6/inet6_hashtables.c @@ -20,6 +20,7 @@ #include <net/inet_connection_sock.h> #include <net/inet_hashtables.h> #include <net/inet6_hashtables.h> +#include <net/secure_seq.h> #include <net/ip.h> int __inet6_hash(struct sock *sk, struct inet_timewait_sock *tw) diff --git a/net/ipv6/ip6_fib.c b/net/ipv6/ip6_fib.c index 54a4678955bf..320d91d20ad7 100644 --- a/net/ipv6/ip6_fib.c +++ b/net/ipv6/ip6_fib.c @@ -1455,7 +1455,7 @@ static int fib6_age(struct rt6_info *rt, void *arg) RT6_TRACE("aging clone %p\n", rt); return -1; } else if ((rt->rt6i_flags & RTF_GATEWAY) && - (!(dst_get_neighbour(&rt->dst)->flags & NTF_ROUTER))) { + (!(dst_get_neighbour_raw(&rt->dst)->flags & NTF_ROUTER))) { RT6_TRACE("purging route %p via non-router but gateway\n", rt); return -1; diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 32e5339db0c8..4c882cf4e8a1 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -135,10 +135,15 @@ static int ip6_finish_output2(struct sk_buff *skb) skb->len); } + rcu_read_lock(); neigh = dst_get_neighbour(dst); - if (neigh) - return neigh_output(neigh, skb); + if (neigh) { + int res = neigh_output(neigh, skb); + rcu_read_unlock(); + return res; + } + rcu_read_unlock(); IP6_INC_STATS_BH(dev_net(dst->dev), ip6_dst_idev(dst), IPSTATS_MIB_OUTNOROUTES); kfree_skb(skb); @@ -975,12 +980,14 @@ static int ip6_dst_lookup_tail(struct sock *sk, * dst entry and replace it instead with the * dst entry of the nexthop router */ + rcu_read_lock(); n = dst_get_neighbour(*dst); if (n && !(n->nud_state & NUD_VALID)) { struct inet6_ifaddr *ifp; struct flowi6 fl_gw6; int redirect; + rcu_read_unlock(); ifp = ipv6_get_ifaddr(net, &fl6->saddr, (*dst)->dev, 1); @@ -1000,6 +1007,8 @@ static int ip6_dst_lookup_tail(struct sock *sk, if ((err = (*dst)->error)) goto out_err_release; } + } else { + rcu_read_unlock(); } #endif diff --git a/net/ipv6/route.c b/net/ipv6/route.c index e8987da06667..9e69eb0ec6dd 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -364,7 +364,7 @@ out: #ifdef CONFIG_IPV6_ROUTER_PREF static void rt6_probe(struct rt6_info *rt) { - struct neighbour *neigh = rt ? dst_get_neighbour(&rt->dst) : NULL; + struct neighbour *neigh; /* * Okay, this does not seem to be appropriate * for now, however, we need to check if it @@ -373,8 +373,10 @@ static void rt6_probe(struct rt6_info *rt) * Router Reachability Probe MUST be rate-limited * to no more than one per minute. */ + rcu_read_lock(); + neigh = rt ? dst_get_neighbour(&rt->dst) : NULL; if (!neigh || (neigh->nud_state & NUD_VALID)) - return; + goto out; read_lock_bh(&neigh->lock); if (!(neigh->nud_state & NUD_VALID) && time_after(jiffies, neigh->updated + rt->rt6i_idev->cnf.rtr_probe_interval)) { @@ -387,8 +389,11 @@ static void rt6_probe(struct rt6_info *rt) target = (struct in6_addr *)&neigh->primary_key; addrconf_addr_solict_mult(target, &mcaddr); ndisc_send_ns(rt->rt6i_dev, NULL, target, &mcaddr, NULL); - } else + } else { read_unlock_bh(&neigh->lock); + } +out: + rcu_read_unlock(); } #else static inline void rt6_probe(struct rt6_info *rt) @@ -412,8 +417,11 @@ static inline int rt6_check_dev(struct rt6_info *rt, int oif) static inline int rt6_check_neigh(struct rt6_info *rt) { - struct neighbour *neigh = dst_get_neighbour(&rt->dst); + struct neighbour *neigh; int m; + + rcu_read_lock(); + neigh = dst_get_neighbour(&rt->dst); if (rt->rt6i_flags & RTF_NONEXTHOP || !(rt->rt6i_flags & RTF_GATEWAY)) m = 1; @@ -430,6 +438,7 @@ static inline int rt6_check_neigh(struct rt6_info *rt) read_unlock_bh(&neigh->lock); } else m = 0; + rcu_read_unlock(); return m; } @@ -769,7 +778,7 @@ static struct rt6_info *rt6_alloc_clone(struct rt6_info *ort, rt->rt6i_dst.plen = 128; rt->rt6i_flags |= RTF_CACHE; rt->dst.flags |= DST_HOST; - dst_set_neighbour(&rt->dst, neigh_clone(dst_get_neighbour(&ort->dst))); + dst_set_neighbour(&rt->dst, neigh_clone(dst_get_neighbour_raw(&ort->dst))); } return rt; } @@ -803,7 +812,7 @@ restart: dst_hold(&rt->dst); read_unlock_bh(&table->tb6_lock); - if (!dst_get_neighbour(&rt->dst) && !(rt->rt6i_flags & RTF_NONEXTHOP)) + if (!dst_get_neighbour_raw(&rt->dst) && !(rt->rt6i_flags & RTF_NONEXTHOP)) nrt = rt6_alloc_cow(rt, &fl6->daddr, &fl6->saddr); else if (!(rt->dst.flags & DST_HOST)) nrt = rt6_alloc_clone(rt, &fl6->daddr); @@ -1587,7 +1596,7 @@ void rt6_redirect(const struct in6_addr *dest, const struct in6_addr *src, dst_confirm(&rt->dst); /* Duplicate redirect: silently ignore. */ - if (neigh == dst_get_neighbour(&rt->dst)) + if (neigh == dst_get_neighbour_raw(&rt->dst)) goto out; nrt = ip6_rt_copy(rt, dest); @@ -1682,7 +1691,7 @@ again: 1. It is connected route. Action: COW 2. It is gatewayed route or NONEXTHOP route. Action: clone it. */ - if (!dst_get_neighbour(&rt->dst) && !(rt->rt6i_flags & RTF_NONEXTHOP)) + if (!dst_get_neighbour_raw(&rt->dst) && !(rt->rt6i_flags & RTF_NONEXTHOP)) nrt = rt6_alloc_cow(rt, daddr, saddr); else nrt = rt6_alloc_clone(rt, daddr); @@ -2326,6 +2335,7 @@ static int rt6_fill_node(struct net *net, struct nlmsghdr *nlh; long expires; u32 table; + struct neighbour *n; if (prefix) { /* user wants prefix routes only */ if (!(rt->rt6i_flags & RTF_PREFIX_RT)) { @@ -2414,8 +2424,11 @@ static int rt6_fill_node(struct net *net, if (rtnetlink_put_metrics(skb, dst_metrics_ptr(&rt->dst)) < 0) goto nla_put_failure; - if (dst_get_neighbour(&rt->dst)) - NLA_PUT(skb, RTA_GATEWAY, 16, &dst_get_neighbour(&rt->dst)->primary_key); + rcu_read_lock(); + n = dst_get_neighbour(&rt->dst); + if (n) + NLA_PUT(skb, RTA_GATEWAY, 16, &n->primary_key); + rcu_read_unlock(); if (rt->dst.dev) NLA_PUT_U32(skb, RTA_OIF, rt->rt6i_dev->ifindex); @@ -2608,12 +2621,14 @@ static int rt6_info_route(struct rt6_info *rt, void *p_arg) #else seq_puts(m, "00000000000000000000000000000000 00 "); #endif + rcu_read_lock(); n = dst_get_neighbour(&rt->dst); if (n) { seq_printf(m, "%pi6", n->primary_key); } else { seq_puts(m, "00000000000000000000000000000000"); } + rcu_read_unlock(); seq_printf(m, " %08x %08x %08x %08x %8s\n", rt->rt6i_metric, atomic_read(&rt->dst.__refcnt), rt->dst.__use, rt->rt6i_flags, diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index 78aa53492b3e..d1fb63f4aeb7 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -61,6 +61,7 @@ #include <net/timewait_sock.h> #include <net/netdma.h> #include <net/inet_common.h> +#include <net/secure_seq.h> #include <asm/uaccess.h> diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c index be43fd805bd0..2b771dc708a3 100644 --- a/net/netfilter/ipvs/ip_vs_ctl.c +++ b/net/netfilter/ipvs/ip_vs_ctl.c @@ -3771,6 +3771,7 @@ err_sock: void ip_vs_control_cleanup(void) { EnterFunction(2); + unregister_netdevice_notifier(&ip_vs_dst_notifier); ip_vs_genl_unregister(); nf_unregister_sockopt(&ip_vs_sockopts); LeaveFunction(2); diff --git a/net/netlabel/Makefile b/net/netlabel/Makefile index ea750e9df65f..d2732fc952e2 100644 --- a/net/netlabel/Makefile +++ b/net/netlabel/Makefile @@ -1,8 +1,6 @@ # # Makefile for the NetLabel subsystem. # -# Feb 9, 2006, Paul Moore <paul.moore@hp.com> -# # base objects obj-y := netlabel_user.o netlabel_kapi.o diff --git a/net/netlabel/netlabel_addrlist.c b/net/netlabel/netlabel_addrlist.c index c0519139679e..96b749dacc34 100644 --- a/net/netlabel/netlabel_addrlist.c +++ b/net/netlabel/netlabel_addrlist.c @@ -6,7 +6,7 @@ * system manages static and dynamic label mappings for network protocols such * as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_addrlist.h b/net/netlabel/netlabel_addrlist.h index 2b9644e19de0..fdbc1d2c7352 100644 --- a/net/netlabel/netlabel_addrlist.h +++ b/net/netlabel/netlabel_addrlist.h @@ -6,7 +6,7 @@ * system manages static and dynamic label mappings for network protocols such * as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_cipso_v4.c b/net/netlabel/netlabel_cipso_v4.c index dd53a36d89af..6bf878335d94 100644 --- a/net/netlabel/netlabel_cipso_v4.c +++ b/net/netlabel/netlabel_cipso_v4.c @@ -5,7 +5,7 @@ * NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_cipso_v4.h b/net/netlabel/netlabel_cipso_v4.h index af7f3355103e..d24d774bfd62 100644 --- a/net/netlabel/netlabel_cipso_v4.h +++ b/net/netlabel/netlabel_cipso_v4.h @@ -5,7 +5,7 @@ * NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_domainhash.c b/net/netlabel/netlabel_domainhash.c index 2aa975e5452d..7d8083cde34f 100644 --- a/net/netlabel/netlabel_domainhash.c +++ b/net/netlabel/netlabel_domainhash.c @@ -6,7 +6,7 @@ * system manages static and dynamic label mappings for network protocols such * as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_domainhash.h b/net/netlabel/netlabel_domainhash.h index 0261dda3f2d2..bfcc0f7024c5 100644 --- a/net/netlabel/netlabel_domainhash.h +++ b/net/netlabel/netlabel_domainhash.h @@ -6,7 +6,7 @@ * system manages static and dynamic label mappings for network protocols such * as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_kapi.c b/net/netlabel/netlabel_kapi.c index b528dd928d3c..58107d060846 100644 --- a/net/netlabel/netlabel_kapi.c +++ b/net/netlabel/netlabel_kapi.c @@ -5,7 +5,7 @@ * system manages static and dynamic label mappings for network protocols such * as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_mgmt.c b/net/netlabel/netlabel_mgmt.c index dff8a0809245..bfa555869775 100644 --- a/net/netlabel/netlabel_mgmt.c +++ b/net/netlabel/netlabel_mgmt.c @@ -5,7 +5,7 @@ * NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_mgmt.h b/net/netlabel/netlabel_mgmt.h index 8db37f4c10f7..5a9f31ce5799 100644 --- a/net/netlabel/netlabel_mgmt.h +++ b/net/netlabel/netlabel_mgmt.h @@ -5,7 +5,7 @@ * NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_unlabeled.c b/net/netlabel/netlabel_unlabeled.c index f1ecf848e3ac..e6e823656f9d 100644 --- a/net/netlabel/netlabel_unlabeled.c +++ b/net/netlabel/netlabel_unlabeled.c @@ -5,7 +5,7 @@ * NetLabel system. The NetLabel system manages static and dynamic label * mappings for network protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_unlabeled.h b/net/netlabel/netlabel_unlabeled.h index 0bc8dc3f9e3c..700af49022a0 100644 --- a/net/netlabel/netlabel_unlabeled.h +++ b/net/netlabel/netlabel_unlabeled.h @@ -5,7 +5,7 @@ * NetLabel system. The NetLabel system manages static and dynamic label * mappings for network protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_user.c b/net/netlabel/netlabel_user.c index a3fd75ac3fa5..9fae63f10298 100644 --- a/net/netlabel/netlabel_user.c +++ b/net/netlabel/netlabel_user.c @@ -5,7 +5,7 @@ * NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/netlabel/netlabel_user.h b/net/netlabel/netlabel_user.h index f4fc4c9ad567..81969785e279 100644 --- a/net/netlabel/netlabel_user.h +++ b/net/netlabel/netlabel_user.h @@ -5,7 +5,7 @@ * NetLabel system manages static and dynamic label mappings for network * protocols such as CIPSO and RIPSO. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/net/sched/sch_sfq.c b/net/sched/sch_sfq.c index 4536ee64383e..4f5510e2bd6f 100644 --- a/net/sched/sch_sfq.c +++ b/net/sched/sch_sfq.c @@ -410,7 +410,12 @@ sfq_enqueue(struct sk_buff *skb, struct Qdisc *sch) /* Return Congestion Notification only if we dropped a packet * from this flow. */ - return (qlen != slot->qlen) ? NET_XMIT_CN : NET_XMIT_SUCCESS; + if (qlen != slot->qlen) + return NET_XMIT_CN; + + /* As we dropped a packet, better let upper stack know this */ + qdisc_tree_decrease_qlen(sch, 1); + return NET_XMIT_SUCCESS; } static struct sk_buff * diff --git a/net/socket.c b/net/socket.c index b1cbbcd92558..24a77400b65e 100644 --- a/net/socket.c +++ b/net/socket.c @@ -1871,8 +1871,14 @@ SYSCALL_DEFINE2(shutdown, int, fd, int, how) #define COMPAT_NAMELEN(msg) COMPAT_MSG(msg, msg_namelen) #define COMPAT_FLAGS(msg) COMPAT_MSG(msg, msg_flags) +struct used_address { + struct sockaddr_storage name; + unsigned int name_len; +}; + static int __sys_sendmsg(struct socket *sock, struct msghdr __user *msg, - struct msghdr *msg_sys, unsigned flags, int nosec) + struct msghdr *msg_sys, unsigned flags, + struct used_address *used_address) { struct compat_msghdr __user *msg_compat = (struct compat_msghdr __user *)msg; @@ -1953,8 +1959,28 @@ static int __sys_sendmsg(struct socket *sock, struct msghdr __user *msg, if (sock->file->f_flags & O_NONBLOCK) msg_sys->msg_flags |= MSG_DONTWAIT; - err = (nosec ? sock_sendmsg_nosec : sock_sendmsg)(sock, msg_sys, - total_len); + /* + * If this is sendmmsg() and current destination address is same as + * previously succeeded address, omit asking LSM's decision. + * used_address->name_len is initialized to UINT_MAX so that the first + * destination address never matches. + */ + if (used_address && used_address->name_len == msg_sys->msg_namelen && + !memcmp(&used_address->name, msg->msg_name, + used_address->name_len)) { + err = sock_sendmsg_nosec(sock, msg_sys, total_len); + goto out_freectl; + } + err = sock_sendmsg(sock, msg_sys, total_len); + /* + * If this is sendmmsg() and sending to current destination address was + * successful, remember it. + */ + if (used_address && err >= 0) { + used_address->name_len = msg_sys->msg_namelen; + memcpy(&used_address->name, msg->msg_name, + used_address->name_len); + } out_freectl: if (ctl_buf != ctl) @@ -1979,7 +2005,7 @@ SYSCALL_DEFINE3(sendmsg, int, fd, struct msghdr __user *, msg, unsigned, flags) if (!sock) goto out; - err = __sys_sendmsg(sock, msg, &msg_sys, flags, 0); + err = __sys_sendmsg(sock, msg, &msg_sys, flags, NULL); fput_light(sock->file, fput_needed); out: @@ -1998,6 +2024,10 @@ int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen, struct mmsghdr __user *entry; struct compat_mmsghdr __user *compat_entry; struct msghdr msg_sys; + struct used_address used_address; + + if (vlen > UIO_MAXIOV) + vlen = UIO_MAXIOV; datagrams = 0; @@ -2005,27 +2035,22 @@ int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen, if (!sock) return err; - err = sock_error(sock->sk); - if (err) - goto out_put; - + used_address.name_len = UINT_MAX; entry = mmsg; compat_entry = (struct compat_mmsghdr __user *)mmsg; + err = 0; while (datagrams < vlen) { - /* - * No need to ask LSM for more than the first datagram. - */ if (MSG_CMSG_COMPAT & flags) { err = __sys_sendmsg(sock, (struct msghdr __user *)compat_entry, - &msg_sys, flags, datagrams); + &msg_sys, flags, &used_address); if (err < 0) break; err = __put_user(err, &compat_entry->msg_len); ++compat_entry; } else { err = __sys_sendmsg(sock, (struct msghdr __user *)entry, - &msg_sys, flags, datagrams); + &msg_sys, flags, &used_address); if (err < 0) break; err = put_user(err, &entry->msg_len); @@ -2037,29 +2062,11 @@ int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen, ++datagrams; } -out_put: fput_light(sock->file, fput_needed); - if (err == 0) - return datagrams; - - if (datagrams != 0) { - /* - * We may send less entries than requested (vlen) if the - * sock is non blocking... - */ - if (err != -EAGAIN) { - /* - * ... or if sendmsg returns an error after we - * send some datagrams, where we record the - * error to return on the next call or if the - * app asks about it using getsockopt(SO_ERROR). - */ - sock->sk->sk_err = -err; - } - + /* We only return an error if no datagrams were able to be sent */ + if (datagrams != 0) return datagrams; - } return err; } diff --git a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c index 9b6a4d1ea8f8..f4385e45a5fc 100644 --- a/net/sunrpc/xprt.c +++ b/net/sunrpc/xprt.c @@ -187,6 +187,7 @@ EXPORT_SYMBOL_GPL(xprt_load_transport); /** * xprt_reserve_xprt - serialize write access to transports * @task: task that is requesting access to the transport + * @xprt: pointer to the target transport * * This prevents mixing the payload of separate requests, and prevents * transport connects from colliding with writes. No congestion control diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index 28d2aa109bee..e83e7fee3bc0 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c @@ -3464,7 +3464,7 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info) tmp) { enum ieee80211_band band = nla_type(attr); - if (band < 0 || band > IEEE80211_NUM_BANDS) { + if (band < 0 || band >= IEEE80211_NUM_BANDS) { err = -EINVAL; goto out_free; } diff --git a/net/xfrm/xfrm_algo.c b/net/xfrm/xfrm_algo.c index 58064d9e565d..791ab2e77f3f 100644 --- a/net/xfrm/xfrm_algo.c +++ b/net/xfrm/xfrm_algo.c @@ -462,8 +462,8 @@ static struct xfrm_algo_desc ealg_list[] = { .desc = { .sadb_alg_id = SADB_X_EALG_AESCTR, .sadb_alg_ivlen = 8, - .sadb_alg_minbits = 128, - .sadb_alg_maxbits = 256 + .sadb_alg_minbits = 160, + .sadb_alg_maxbits = 288 } }, }; diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index a38316b2e3f6..266a2292451d 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -14,7 +14,7 @@ * Copyright (C) 2004-2005 Trusted Computer Solutions, Inc. * <dgoeddel@trustedcs.com> * Copyright (C) 2006, 2007, 2009 Hewlett-Packard Development Company, L.P. - * Paul Moore <paul.moore@hp.com> + * Paul Moore <paul@paul-moore.com> * Copyright (C) 2007 Hitachi Software Engineering Co., Ltd. * Yuichi Nakamura <ynakam@hitachisoft.jp> * diff --git a/security/selinux/include/netif.h b/security/selinux/include/netif.h index ce23edd128b3..43d507242b42 100644 --- a/security/selinux/include/netif.h +++ b/security/selinux/include/netif.h @@ -8,7 +8,7 @@ * * Copyright (C) 2003 Red Hat, Inc., James Morris <jmorris@redhat.com> * Copyright (C) 2007 Hewlett-Packard Development Company, L.P. - * Paul Moore, <paul.moore@hp.com> + * Paul Moore <paul@paul-moore.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2, diff --git a/security/selinux/include/netlabel.h b/security/selinux/include/netlabel.h index cf2f628e6e28..8c59b8f150e8 100644 --- a/security/selinux/include/netlabel.h +++ b/security/selinux/include/netlabel.h @@ -1,7 +1,7 @@ /* * SELinux interface to the NetLabel subsystem * - * Author : Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/security/selinux/include/netnode.h b/security/selinux/include/netnode.h index 1b94450d11d2..df7a5ed6c694 100644 --- a/security/selinux/include/netnode.h +++ b/security/selinux/include/netnode.h @@ -6,7 +6,7 @@ * needed to reduce the lookup overhead since most of these queries happen on * a per-packet basis. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/security/selinux/include/netport.h b/security/selinux/include/netport.h index 8991752eaf93..4d965b83d735 100644 --- a/security/selinux/include/netport.h +++ b/security/selinux/include/netport.h @@ -5,7 +5,7 @@ * mapping is maintained as part of the normal policy but a fast cache is * needed to reduce the lookup overhead. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/security/selinux/netif.c b/security/selinux/netif.c index 58cc481c93d5..326f22cbe405 100644 --- a/security/selinux/netif.c +++ b/security/selinux/netif.c @@ -8,7 +8,7 @@ * * Copyright (C) 2003 Red Hat, Inc., James Morris <jmorris@redhat.com> * Copyright (C) 2007 Hewlett-Packard Development Company, L.P. - * Paul Moore <paul.moore@hp.com> + * Paul Moore <paul@paul-moore.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2, diff --git a/security/selinux/netlabel.c b/security/selinux/netlabel.c index c3bf3ed07b06..da4b8b233280 100644 --- a/security/selinux/netlabel.c +++ b/security/selinux/netlabel.c @@ -4,7 +4,7 @@ * This file provides the necessary glue to tie NetLabel into the SELinux * subsystem. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * */ diff --git a/security/selinux/netnode.c b/security/selinux/netnode.c index 8b691a863186..3bf46abaa688 100644 --- a/security/selinux/netnode.c +++ b/security/selinux/netnode.c @@ -6,7 +6,7 @@ * needed to reduce the lookup overhead since most of these queries happen on * a per-packet basis. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * * This code is heavily based on the "netif" concept originally developed by * James Morris <jmorris@redhat.com> diff --git a/security/selinux/netport.c b/security/selinux/netport.c index ae76e298de7d..0b62bd112461 100644 --- a/security/selinux/netport.c +++ b/security/selinux/netport.c @@ -5,7 +5,7 @@ * mapping is maintained as part of the normal policy but a fast cache is * needed to reduce the lookup overhead. * - * Author: Paul Moore <paul.moore@hp.com> + * Author: Paul Moore <paul@paul-moore.com> * * This code is heavily based on the "netif" concept originally developed by * James Morris <jmorris@redhat.com> diff --git a/security/selinux/selinuxfs.c b/security/selinux/selinuxfs.c index de7900ef53da..55d92cbb177a 100644 --- a/security/selinux/selinuxfs.c +++ b/security/selinux/selinuxfs.c @@ -2,7 +2,7 @@ * * Added conditional policy language extensions * - * Updated: Hewlett-Packard <paul.moore@hp.com> + * Updated: Hewlett-Packard <paul@paul-moore.com> * * Added support for the policy capability bitmap * diff --git a/security/selinux/ss/ebitmap.c b/security/selinux/ss/ebitmap.c index d42951fcbe87..30f119b1d1ec 100644 --- a/security/selinux/ss/ebitmap.c +++ b/security/selinux/ss/ebitmap.c @@ -4,7 +4,7 @@ * Author : Stephen Smalley, <sds@epoch.ncsc.mil> */ /* - * Updated: Hewlett-Packard <paul.moore@hp.com> + * Updated: Hewlett-Packard <paul@paul-moore.com> * * Added support to import/export the NetLabel category bitmap * diff --git a/security/selinux/ss/mls.c b/security/selinux/ss/mls.c index e96174216bc9..fbf9c5816c71 100644 --- a/security/selinux/ss/mls.c +++ b/security/selinux/ss/mls.c @@ -11,7 +11,7 @@ * Copyright (C) 2004-2006 Trusted Computer Solutions, Inc. */ /* - * Updated: Hewlett-Packard <paul.moore@hp.com> + * Updated: Hewlett-Packard <paul@paul-moore.com> * * Added support to import/export the MLS label from NetLabel * diff --git a/security/selinux/ss/mls.h b/security/selinux/ss/mls.h index 037bf9d82d41..e4369e3e6366 100644 --- a/security/selinux/ss/mls.h +++ b/security/selinux/ss/mls.h @@ -11,7 +11,7 @@ * Copyright (C) 2004-2006 Trusted Computer Solutions, Inc. */ /* - * Updated: Hewlett-Packard <paul.moore@hp.com> + * Updated: Hewlett-Packard <paul@paul-moore.com> * * Added support to import/export the MLS label from NetLabel * diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c index d246aca3f4fb..2381d0ded228 100644 --- a/security/selinux/ss/policydb.c +++ b/security/selinux/ss/policydb.c @@ -13,7 +13,7 @@ * * Added conditional policy language extensions * - * Updated: Hewlett-Packard <paul.moore@hp.com> + * Updated: Hewlett-Packard <paul@paul-moore.com> * * Added support for the policy capability bitmap * diff --git a/security/selinux/ss/services.c b/security/selinux/ss/services.c index 973e00e34fa9..f6917bc0aa05 100644 --- a/security/selinux/ss/services.c +++ b/security/selinux/ss/services.c @@ -13,7 +13,7 @@ * * Added conditional policy language extensions * - * Updated: Hewlett-Packard <paul.moore@hp.com> + * Updated: Hewlett-Packard <paul@paul-moore.com> * * Added support for NetLabel * Added support for the policy capability bitmap diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index f375eb2e1957..b9c5e149903b 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -9,7 +9,7 @@ * * Copyright (C) 2007 Casey Schaufler <casey@schaufler-ca.com> * Copyright (C) 2009 Hewlett-Packard Development Company, L.P. - * Paul Moore <paul.moore@hp.com> + * Paul Moore <paul@paul-moore.com> * Copyright (C) 2010 Nokia Corporation * * This program is free software; you can redistribute it and/or modify diff --git a/security/tomoyo/common.c b/security/tomoyo/common.c index c8439cf2a448..2e43aec1c36b 100644 --- a/security/tomoyo/common.c +++ b/security/tomoyo/common.c @@ -710,8 +710,10 @@ static void tomoyo_read_profile(struct tomoyo_io_buffer *head) head->r.index++) if (ns->profile_ptr[head->r.index]) break; - if (head->r.index == TOMOYO_MAX_PROFILES) + if (head->r.index == TOMOYO_MAX_PROFILES) { + head->r.eof = true; return; + } head->r.step++; break; case 2: @@ -723,6 +725,7 @@ static void tomoyo_read_profile(struct tomoyo_io_buffer *head) tomoyo_io_printf(head, "%u-COMMENT=", index); tomoyo_set_string(head, comment ? comment->name : ""); tomoyo_set_lf(head); + tomoyo_print_namespace(head); tomoyo_io_printf(head, "%u-PREFERENCE={ ", index); for (i = 0; i < TOMOYO_MAX_PREF; i++) tomoyo_io_printf(head, "%s=%u ", diff --git a/sound/core/timer.c b/sound/core/timer.c index 7c1cbf0a0dc4..67ebf1c21c04 100644 --- a/sound/core/timer.c +++ b/sound/core/timer.c @@ -328,6 +328,8 @@ int snd_timer_close(struct snd_timer_instance *timeri) mutex_unlock(®ister_mutex); } else { timer = timeri->timer; + if (snd_BUG_ON(!timer)) + goto out; /* wait, until the active callback is finished */ spin_lock_irq(&timer->lock); while (timeri->flags & SNDRV_TIMER_IFLG_CALLBACK) { @@ -353,6 +355,7 @@ int snd_timer_close(struct snd_timer_instance *timeri) } mutex_unlock(®ister_mutex); } + out: if (timeri->private_free) timeri->private_free(timeri); kfree(timeri->owner); @@ -531,6 +534,8 @@ int snd_timer_stop(struct snd_timer_instance *timeri) if (err < 0) return err; timer = timeri->timer; + if (!timer) + return -EINVAL; spin_lock_irqsave(&timer->lock, flags); timeri->cticks = timeri->ticks; timeri->pticks = 0; diff --git a/sound/oss/pas2_pcm.c b/sound/oss/pas2_pcm.c index 8f7d175767a2..6f13ab4afc6b 100644 --- a/sound/oss/pas2_pcm.c +++ b/sound/oss/pas2_pcm.c @@ -63,13 +63,13 @@ static int pcm_set_speed(int arg) if (pcm_channels & 2) { - foo = ((CLOCK_TICK_RATE / 2) + (arg / 2)) / arg; - arg = ((CLOCK_TICK_RATE / 2) + (foo / 2)) / foo; + foo = ((PIT_TICK_RATE / 2) + (arg / 2)) / arg; + arg = ((PIT_TICK_RATE / 2) + (foo / 2)) / foo; } else { - foo = (CLOCK_TICK_RATE + (arg / 2)) / arg; - arg = (CLOCK_TICK_RATE + (foo / 2)) / foo; + foo = (PIT_TICK_RATE + (arg / 2)) / arg; + arg = (PIT_TICK_RATE + (foo / 2)) / foo; } pcm_speed = arg; diff --git a/sound/oss/pss.c b/sound/oss/pss.c index 9b800ce5100e..2fc0624024b5 100644 --- a/sound/oss/pss.c +++ b/sound/oss/pss.c @@ -673,7 +673,8 @@ static void configure_nonsound_components(void) if (pss_cdrom_port == -1) { /* If cdrom port enablation wasn't requested */ printk(KERN_INFO "PSS: CDROM port not enabled.\n"); - } else if (check_region(pss_cdrom_port, 2)) { + } else if (!request_region(pss_cdrom_port, 2, "PSS CDROM")) { + pss_cdrom_port = -1; printk(KERN_ERR "PSS: CDROM I/O port conflict.\n"); } else { set_io_base(devc, CONF_CDROM, pss_cdrom_port); @@ -1232,7 +1233,8 @@ static void __exit cleanup_pss(void) if(pssmpu) unload_pss_mpu(&cfg_mpu); unload_pss(&cfg); - } + } else if (pss_cdrom_port != -1) + release_region(pss_cdrom_port, 2); if(!pss_keep_settings) /* Keep hardware settings if asked */ { diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig index 50abf5bf8e09..88168044375f 100644 --- a/sound/pci/Kconfig +++ b/sound/pci/Kconfig @@ -1,5 +1,10 @@ # ALSA PCI drivers +config SND_TEA575X + tristate + depends on SND_FM801_TEA575X_BOOL || SND_ES1968_RADIO || RADIO_SF16FMR2 + default SND_FM801 || SND_ES1968 || RADIO_SF16FMR2 + menuconfig SND_PCI bool "PCI sound devices" depends on PCI @@ -563,11 +568,6 @@ config SND_FM801_TEA575X_BOOL FM801 chip with a TEA5757 tuner (MediaForte SF256-PCS, SF256-PCP and SF64-PCR) into the snd-fm801 driver. -config SND_TEA575X - tristate - depends on SND_FM801_TEA575X_BOOL || SND_ES1968_RADIO || RADIO_SF16FMR2 - default SND_FM801 || SND_ES1968 || RADIO_SF16FMR2 - source "sound/pci/hda/Kconfig" config SND_HDSP diff --git a/sound/pci/asihpi/hpicmn.c b/sound/pci/asihpi/hpicmn.c index 65b7ca13115b..bd47521b24ec 100644 --- a/sound/pci/asihpi/hpicmn.c +++ b/sound/pci/asihpi/hpicmn.c @@ -631,13 +631,12 @@ struct hpi_control_cache *hpi_alloc_control_cache(const u32 control_count, if (!p_cache) return NULL; - p_cache->p_info = - kmalloc(sizeof(*p_cache->p_info) * control_count, GFP_KERNEL); + p_cache->p_info = kzalloc(sizeof(*p_cache->p_info) * control_count, + GFP_KERNEL); if (!p_cache->p_info) { kfree(p_cache); return NULL; } - memset(p_cache->p_info, 0, sizeof(*p_cache->p_info) * control_count); p_cache->cache_size_in_bytes = size_in_bytes; p_cache->control_count = control_count; p_cache->p_cache = p_dsp_control_buffer; diff --git a/sound/pci/hda/alc269_quirks.c b/sound/pci/hda/alc269_quirks.c index 14fdcf29b154..5ac0e2162a46 100644 --- a/sound/pci/hda/alc269_quirks.c +++ b/sound/pci/hda/alc269_quirks.c @@ -531,17 +531,10 @@ static const struct snd_pci_quirk alc269_cfg_tbl[] = { SND_PCI_QUIRK(0x1043, 0x1653, "ASUS U50", ALC269_AMIC), SND_PCI_QUIRK(0x1043, 0x1693, "ASUS F50N", ALC269_AMIC), SND_PCI_QUIRK(0x1043, 0x16a3, "ASUS F5Q", ALC269_AMIC), - SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_DMIC), SND_PCI_QUIRK(0x1043, 0x1723, "ASUS P80", ALC269_AMIC), SND_PCI_QUIRK(0x1043, 0x1743, "ASUS U80", ALC269_AMIC), SND_PCI_QUIRK(0x1043, 0x1773, "ASUS U20A", ALC269_AMIC), SND_PCI_QUIRK(0x1043, 0x1883, "ASUS F81Se", ALC269_AMIC), - SND_PCI_QUIRK(0x1043, 0x831a, "ASUS Eeepc P901", - ALC269_DMIC), - SND_PCI_QUIRK(0x1043, 0x834a, "ASUS Eeepc S101", - ALC269_DMIC), - SND_PCI_QUIRK(0x1043, 0x8398, "ASUS P1005HA", ALC269_DMIC), - SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS P1005HA", ALC269_DMIC), SND_PCI_QUIRK(0x104d, 0x9071, "Sony VAIO", ALC269_AUTO), SND_PCI_QUIRK(0x10cf, 0x1475, "Lifebook ICH9M-based", ALC269_LIFEBOOK), SND_PCI_QUIRK(0x152d, 0x1778, "Quanta ON1", ALC269_DMIC), diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index e125c60fe352..9a1aa09f47fe 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -4484,6 +4484,22 @@ static void alc269_fixup_pcm_44k(struct hda_codec *codec, spec->stream_analog_capture = &alc269_44k_pcm_analog_capture; } +static void alc269_fixup_stereo_dmic(struct hda_codec *codec, + const struct alc_fixup *fix, int action) +{ + int coef; + + if (action != ALC_FIXUP_ACT_INIT) + return; + /* The digital-mic unit sends PDM (differential signal) instead of + * the standard PCM, thus you can't record a valid mono stream as is. + * Below is a workaround specific to ALC269 to control the dmic + * signal source as mono. + */ + coef = alc_read_coef_idx(codec, 0x07); + alc_write_coef_idx(codec, 0x07, coef | 0x80); +} + enum { ALC269_FIXUP_SONY_VAIO, ALC275_FIXUP_SONY_VAIO_GPIO2, @@ -4494,6 +4510,7 @@ enum { ALC275_FIXUP_SONY_HWEQ, ALC271_FIXUP_DMIC, ALC269_FIXUP_PCM_44K, + ALC269_FIXUP_STEREO_DMIC, }; static const struct alc_fixup alc269_fixups[] = { @@ -4556,10 +4573,19 @@ static const struct alc_fixup alc269_fixups[] = { .type = ALC_FIXUP_FUNC, .v.func = alc269_fixup_pcm_44k, }, + [ALC269_FIXUP_STEREO_DMIC] = { + .type = ALC_FIXUP_FUNC, + .v.func = alc269_fixup_stereo_dmic, + }, }; static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW), + SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC), + SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC), + SND_PCI_QUIRK(0x1043, 0x834a, "ASUS S101", ALC269_FIXUP_STEREO_DMIC), + SND_PCI_QUIRK(0x1043, 0x8398, "ASUS P1005", ALC269_FIXUP_STEREO_DMIC), + SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS P1005", ALC269_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x104d, 0x9073, "Sony VAIO", ALC275_FIXUP_SONY_VAIO_GPIO2), SND_PCI_QUIRK(0x104d, 0x907b, "Sony VAIO", ALC275_FIXUP_SONY_HWEQ), SND_PCI_QUIRK(0x104d, 0x9084, "Sony VAIO", ALC275_FIXUP_SONY_HWEQ), diff --git a/sound/pci/hda/patch_via.c b/sound/pci/hda/patch_via.c index 84d8798bf33a..4ebfbd874c9a 100644 --- a/sound/pci/hda/patch_via.c +++ b/sound/pci/hda/patch_via.c @@ -2084,7 +2084,7 @@ static int via_auto_create_speaker_ctls(struct hda_codec *codec) struct via_spec *spec = codec->spec; struct nid_path *path; bool check_dac; - hda_nid_t pin, dac; + hda_nid_t pin, dac = 0; int err; pin = spec->autocfg.speaker_pins[0]; diff --git a/sound/pci/rme9652/hdspm.c b/sound/pci/rme9652/hdspm.c index 6edc67ced905..493e3946756f 100644 --- a/sound/pci/rme9652/hdspm.c +++ b/sound/pci/rme9652/hdspm.c @@ -1339,6 +1339,10 @@ static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) break; case MADIface: freq_const = 131072000000000ULL; + break; + default: + snd_BUG(); + return 0; } return div_u64(freq_const, period); @@ -1356,16 +1360,19 @@ static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) switch (hdspm->io_type) { case MADIface: - n = 131072000000000ULL; /* 125 MHz */ - break; + n = 131072000000000ULL; /* 125 MHz */ + break; case MADI: case AES32: - n = 110069313433624ULL; /* 105 MHz */ - break; + n = 110069313433624ULL; /* 105 MHz */ + break; case RayDAT: case AIO: - n = 104857600000000ULL; /* 100 MHz */ - break; + n = 104857600000000ULL; /* 100 MHz */ + break; + default: + snd_BUG(); + return; } n = div_u64(n, rate); diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 379b2e3afd98..665d9240c4ae 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -78,7 +78,6 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8900 if I2C select SND_SOC_WM8903 if I2C select SND_SOC_WM8904 if I2C - select SND_SOC_WM8915 if I2C select SND_SOC_WM8940 if I2C select SND_SOC_WM8955 if I2C select SND_SOC_WM8960 if I2C @@ -95,6 +94,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8993 if I2C select SND_SOC_WM8994 if MFD_WM8994 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI + select SND_SOC_WM8996 if I2C select SND_SOC_WM9081 if I2C select SND_SOC_WM9090 if I2C select SND_SOC_WM9705 if SND_SOC_AC97_BUS @@ -329,9 +329,6 @@ config SND_SOC_WM8903 config SND_SOC_WM8904 tristate -config SND_SOC_WM8915 - tristate - config SND_SOC_WM8940 tristate @@ -380,6 +377,9 @@ config SND_SOC_WM8994 config SND_SOC_WM8995 tristate +config SND_SOC_WM8996 + tristate + config SND_SOC_WM9081 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index da9990fb8569..5119a7e2c1a8 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -63,7 +63,7 @@ snd-soc-wm8804-objs := wm8804.o snd-soc-wm8900-objs := wm8900.o snd-soc-wm8903-objs := wm8903.o snd-soc-wm8904-objs := wm8904.o -snd-soc-wm8915-objs := wm8915.o +snd-soc-wm8996-objs := wm8996.o snd-soc-wm8940-objs := wm8940.o snd-soc-wm8955-objs := wm8955.o snd-soc-wm8960-objs := wm8960.o @@ -160,7 +160,7 @@ obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o obj-$(CONFIG_SND_SOC_WM8904) += snd-soc-wm8904.o -obj-$(CONFIG_SND_SOC_WM8915) += snd-soc-wm8915.o +obj-$(CONFIG_SND_SOC_WM8996) += snd-soc-wm8996.o obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o obj-$(CONFIG_SND_SOC_WM8955) += snd-soc-wm8955.o obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index 76258f2a2ffb..7e4066e131e6 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -33,73 +33,31 @@ #define SGTL5000_DAP_REG_OFFSET 0x0100 #define SGTL5000_MAX_REG_OFFSET 0x013A -/* default value of sgtl5000 registers except DAP */ -static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = { - 0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */ - 0x0000, /* 0x0002, CHIP_DIG_POWER. */ - 0x0008, /* 0x0004, CHIP_CKL_CTRL */ - 0x0010, /* 0x0006, CHIP_I2S_CTRL */ - 0x0000, /* 0x0008, reserved */ - 0x0008, /* 0x000A, CHIP_SSS_CTRL */ - 0x0000, /* 0x000C, reserved */ - 0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */ - 0x3c3c, /* 0x0010, CHIP_DAC_VOL */ - 0x0000, /* 0x0012, reserved */ - 0x015f, /* 0x0014, CHIP_PAD_STRENGTH */ - 0x0000, /* 0x0016, reserved */ - 0x0000, /* 0x0018, reserved */ - 0x0000, /* 0x001A, reserved */ - 0x0000, /* 0x001E, reserved */ - 0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */ - 0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */ - 0x0111, /* 0x0024, CHIP_ANN_CTRL */ - 0x0000, /* 0x0026, CHIP_LINREG_CTRL */ - 0x0000, /* 0x0028, CHIP_REF_CTRL */ - 0x0000, /* 0x002A, CHIP_MIC_CTRL */ - 0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */ - 0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */ - 0x7060, /* 0x0030, CHIP_ANA_POWER */ - 0x5000, /* 0x0032, CHIP_PLL_CTRL */ - 0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */ - 0x0000, /* 0x0036, CHIP_ANA_STATUS */ - 0x0000, /* 0x0038, reserved */ - 0x0000, /* 0x003A, CHIP_ANA_TEST2 */ - 0x0000, /* 0x003C, CHIP_SHORT_CTRL */ - 0x0000, /* reserved */ -}; - -/* default value of dap registers */ -static const u16 sgtl5000_dap_regs[] = { - 0x0000, /* 0x0100, DAP_CONTROL */ - 0x0000, /* 0x0102, DAP_PEQ */ - 0x0040, /* 0x0104, DAP_BASS_ENHANCE */ - 0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */ - 0x0000, /* 0x0108, DAP_AUDIO_EQ */ - 0x0040, /* 0x010A, DAP_SGTL_SURROUND */ - 0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */ - 0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */ - 0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */ - 0x0000, /* 0x0112, reserved */ - 0x0000, /* 0x0114, reserved */ - 0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */ - 0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */ - 0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */ - 0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */ - 0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */ - 0x8000, /* 0x0120, DAP_MAIN_CHAN */ - 0x0000, /* 0x0122, DAP_MIX_CHAN */ - 0x0510, /* 0x0124, DAP_AVC_CTRL */ - 0x1473, /* 0x0126, DAP_AVC_THRESHOLD */ - 0x0028, /* 0x0128, DAP_AVC_ATTACK */ - 0x0050, /* 0x012A, DAP_AVC_DECAY */ - 0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */ - 0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */ - 0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */ - 0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */ - 0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */ - 0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */ - 0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */ - 0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */ +/* default value of sgtl5000 registers */ +static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = { + [SGTL5000_CHIP_CLK_CTRL] = 0x0008, + [SGTL5000_CHIP_I2S_CTRL] = 0x0010, + [SGTL5000_CHIP_SSS_CTRL] = 0x0008, + [SGTL5000_CHIP_DAC_VOL] = 0x3c3c, + [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f, + [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818, + [SGTL5000_CHIP_ANA_CTRL] = 0x0111, + [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404, + [SGTL5000_CHIP_ANA_POWER] = 0x7060, + [SGTL5000_CHIP_PLL_CTRL] = 0x5000, + [SGTL5000_DAP_BASS_ENHANCE] = 0x0040, + [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f, + [SGTL5000_DAP_SURROUND] = 0x0040, + [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f, + [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f, + [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f, + [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f, + [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f, + [SGTL5000_DAP_MAIN_CHAN] = 0x8000, + [SGTL5000_DAP_AVC_CTRL] = 0x0510, + [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473, + [SGTL5000_DAP_AVC_ATTACK] = 0x0028, + [SGTL5000_DAP_AVC_DECAY] = 0x0050, }; /* regulator supplies for sgtl5000, VDDD is an optional external supply */ @@ -1023,12 +981,10 @@ static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state) static int sgtl5000_restore_regs(struct snd_soc_codec *codec) { u16 *cache = codec->reg_cache; - int i; - int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1; + u16 reg; /* restore regular registers */ - for (i = 0; i < regular_regs; i++) { - int reg = i << 1; + for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { /* this regs depends on the others */ if (reg == SGTL5000_CHIP_ANA_POWER || @@ -1038,35 +994,31 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec) reg == SGTL5000_CHIP_CLK_CTRL) continue; - snd_soc_write(codec, reg, cache[i]); + snd_soc_write(codec, reg, cache[reg]); } /* restore dap registers */ - for (i = SGTL5000_DAP_REG_OFFSET >> 1; - i < SGTL5000_MAX_REG_OFFSET >> 1; i++) { - int reg = i << 1; - - snd_soc_write(codec, reg, cache[i]); - } + for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) + snd_soc_write(codec, reg, cache[reg]); /* * restore power and other regs according * to set_power() and set_clock() */ snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, - cache[SGTL5000_CHIP_LINREG_CTRL >> 1]); + cache[SGTL5000_CHIP_LINREG_CTRL]); snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, - cache[SGTL5000_CHIP_ANA_POWER >> 1]); + cache[SGTL5000_CHIP_ANA_POWER]); snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, - cache[SGTL5000_CHIP_CLK_CTRL >> 1]); + cache[SGTL5000_CHIP_CLK_CTRL]); snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, - cache[SGTL5000_CHIP_REF_CTRL >> 1]); + cache[SGTL5000_CHIP_REF_CTRL]); snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, - cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]); + cache[SGTL5000_CHIP_LINE_OUT_CTRL]); return 0; } @@ -1454,16 +1406,6 @@ static __devinit int sgtl5000_i2c_probe(struct i2c_client *client, if (!sgtl5000) return -ENOMEM; - /* - * copy DAP default values to default value array. - * sgtl5000 register space has a big hole, merge it - * at init phase makes life easy. - * FIXME: should we drop 'const' of sgtl5000_regs? - */ - memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)), - sgtl5000_dap_regs, - SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET); - i2c_set_clientdata(client, sgtl5000); ret = snd_soc_register_codec(&client->dev, diff --git a/sound/soc/codecs/wm8915.c b/sound/soc/codecs/wm8915.c deleted file mode 100644 index 423baa9be241..000000000000 --- a/sound/soc/codecs/wm8915.c +++ /dev/null @@ -1,2995 +0,0 @@ -/* - * wm8915.c - WM8915 audio codec interface - * - * Copyright 2011 Wolfson Microelectronics PLC. - * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/init.h> -#include <linux/completion.h> -#include <linux/delay.h> -#include <linux/pm.h> -#include <linux/gcd.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/regulator/consumer.h> -#include <linux/slab.h> -#include <linux/workqueue.h> -#include <sound/core.h> -#include <sound/jack.h> -#include <sound/pcm.h> -#include <sound/pcm_params.h> -#include <sound/soc.h> -#include <sound/initval.h> -#include <sound/tlv.h> -#include <trace/events/asoc.h> - -#include <sound/wm8915.h> -#include "wm8915.h" - -#define WM8915_AIFS 2 - -#define HPOUT1L 1 -#define HPOUT1R 2 -#define HPOUT2L 4 -#define HPOUT2R 8 - -#define WM8915_NUM_SUPPLIES 4 -static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = { - "DBVDD", - "AVDD1", - "AVDD2", - "CPVDD", -}; - -struct wm8915_priv { - struct snd_soc_codec *codec; - - int ldo1ena; - - int sysclk; - int sysclk_src; - - int fll_src; - int fll_fref; - int fll_fout; - - struct completion fll_lock; - - u16 dcs_pending; - struct completion dcs_done; - - u16 hpout_ena; - u16 hpout_pending; - - struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES]; - struct notifier_block disable_nb[WM8915_NUM_SUPPLIES]; - - struct wm8915_pdata pdata; - - int rx_rate[WM8915_AIFS]; - int bclk_rate[WM8915_AIFS]; - - /* Platform dependant ReTune mobile configuration */ - int num_retune_mobile_texts; - const char **retune_mobile_texts; - int retune_mobile_cfg[2]; - struct soc_enum retune_mobile_enum; - - struct snd_soc_jack *jack; - bool detecting; - bool jack_mic; - wm8915_polarity_fn polarity_cb; - -#ifdef CONFIG_GPIOLIB - struct gpio_chip gpio_chip; -#endif -}; - -/* We can't use the same notifier block for more than one supply and - * there's no way I can see to get from a callback to the caller - * except container_of(). - */ -#define WM8915_REGULATOR_EVENT(n) \ -static int wm8915_regulator_event_##n(struct notifier_block *nb, \ - unsigned long event, void *data) \ -{ \ - struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \ - disable_nb[n]); \ - if (event & REGULATOR_EVENT_DISABLE) { \ - wm8915->codec->cache_sync = 1; \ - } \ - return 0; \ -} - -WM8915_REGULATOR_EVENT(0) -WM8915_REGULATOR_EVENT(1) -WM8915_REGULATOR_EVENT(2) -WM8915_REGULATOR_EVENT(3) - -static const u16 wm8915_reg[WM8915_MAX_REGISTER] = { - [WM8915_SOFTWARE_RESET] = 0x8915, - [WM8915_POWER_MANAGEMENT_7] = 0x10, - [WM8915_DAC1_HPOUT1_VOLUME] = 0x88, - [WM8915_DAC2_HPOUT2_VOLUME] = 0x88, - [WM8915_DAC1_LEFT_VOLUME] = 0x2c0, - [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0, - [WM8915_DAC2_LEFT_VOLUME] = 0x2c0, - [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0, - [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80, - [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80, - [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80, - [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80, - [WM8915_MICBIAS_1] = 0x39, - [WM8915_MICBIAS_2] = 0x39, - [WM8915_LDO_1] = 0x3, - [WM8915_LDO_2] = 0x13, - [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4, - [WM8915_HEADPHONE_DETECT_1] = 0x20, - [WM8915_MIC_DETECT_1] = 0x7600, - [WM8915_MIC_DETECT_2] = 0xbf, - [WM8915_CHARGE_PUMP_1] = 0x1f25, - [WM8915_CHARGE_PUMP_2] = 0xab19, - [WM8915_DC_SERVO_5] = 0x2a2a, - [WM8915_CONTROL_INTERFACE_1] = 0x8004, - [WM8915_CLOCKING_1] = 0x10, - [WM8915_AIF_RATE] = 0x83, - [WM8915_FLL_CONTROL_4] = 0x5dc0, - [WM8915_FLL_CONTROL_5] = 0xc84, - [WM8915_FLL_EFS_2] = 0x2, - [WM8915_AIF1_TX_LRCLK_1] = 0x80, - [WM8915_AIF1_TX_LRCLK_2] = 0x8, - [WM8915_AIF1_RX_LRCLK_1] = 0x80, - [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818, - [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818, - [WM8915_AIF1TX_TEST] = 0x7, - [WM8915_AIF2_TX_LRCLK_1] = 0x80, - [WM8915_AIF2_TX_LRCLK_2] = 0x8, - [WM8915_AIF2_RX_LRCLK_1] = 0x80, - [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818, - [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818, - [WM8915_AIF2TX_TEST] = 0x1, - [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0, - [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0, - [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0, - [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0, - [WM8915_DSP1_TX_FILTERS] = 0x2000, - [WM8915_DSP1_RX_FILTERS_1] = 0x200, - [WM8915_DSP1_RX_FILTERS_2] = 0x10, - [WM8915_DSP1_DRC_1] = 0x98, - [WM8915_DSP1_DRC_2] = 0x845, - [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318, - [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300, - [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca, - [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400, - [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8, - [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5, - [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145, - [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75, - [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5, - [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58, - [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373, - [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54, - [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558, - [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e, - [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829, - [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad, - [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103, - [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564, - [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559, - [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000, - [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0, - [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0, - [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0, - [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0, - [WM8915_DSP2_TX_FILTERS] = 0x2000, - [WM8915_DSP2_RX_FILTERS_1] = 0x200, - [WM8915_DSP2_RX_FILTERS_2] = 0x10, - [WM8915_DSP2_DRC_1] = 0x98, - [WM8915_DSP2_DRC_2] = 0x845, - [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318, - [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300, - [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca, - [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400, - [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8, - [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5, - [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145, - [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75, - [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5, - [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58, - [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373, - [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54, - [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558, - [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e, - [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829, - [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad, - [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103, - [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564, - [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559, - [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000, - [WM8915_OVERSAMPLING] = 0xd, - [WM8915_SIDETONE] = 0x1040, - [WM8915_GPIO_1] = 0xa101, - [WM8915_GPIO_2] = 0xa101, - [WM8915_GPIO_3] = 0xa101, - [WM8915_GPIO_4] = 0xa101, - [WM8915_GPIO_5] = 0xa101, - [WM8915_PULL_CONTROL_2] = 0x140, - [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f, - [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf, - [WM8915_RIGHT_PDM_SPEAKER] = 0x1, - [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69, - [WM8915_PDM_SPEAKER_VOLUME] = 0x66, - [WM8915_WRITE_SEQUENCER_0] = 0x1, - [WM8915_WRITE_SEQUENCER_1] = 0x1, - [WM8915_WRITE_SEQUENCER_3] = 0x6, - [WM8915_WRITE_SEQUENCER_4] = 0x40, - [WM8915_WRITE_SEQUENCER_5] = 0x1, - [WM8915_WRITE_SEQUENCER_6] = 0xf, - [WM8915_WRITE_SEQUENCER_7] = 0x6, - [WM8915_WRITE_SEQUENCER_8] = 0x1, - [WM8915_WRITE_SEQUENCER_9] = 0x3, - [WM8915_WRITE_SEQUENCER_10] = 0x104, - [WM8915_WRITE_SEQUENCER_12] = 0x60, - [WM8915_WRITE_SEQUENCER_13] = 0x11, - [WM8915_WRITE_SEQUENCER_14] = 0x401, - [WM8915_WRITE_SEQUENCER_16] = 0x50, - [WM8915_WRITE_SEQUENCER_17] = 0x3, - [WM8915_WRITE_SEQUENCER_18] = 0x100, - [WM8915_WRITE_SEQUENCER_20] = 0x51, - [WM8915_WRITE_SEQUENCER_21] = 0x3, - [WM8915_WRITE_SEQUENCER_22] = 0x104, - [WM8915_WRITE_SEQUENCER_23] = 0xa, - [WM8915_WRITE_SEQUENCER_24] = 0x60, - [WM8915_WRITE_SEQUENCER_25] = 0x3b, - [WM8915_WRITE_SEQUENCER_26] = 0x502, - [WM8915_WRITE_SEQUENCER_27] = 0x100, - [WM8915_WRITE_SEQUENCER_28] = 0x2fff, - [WM8915_WRITE_SEQUENCER_32] = 0x2fff, - [WM8915_WRITE_SEQUENCER_36] = 0x2fff, - [WM8915_WRITE_SEQUENCER_40] = 0x2fff, - [WM8915_WRITE_SEQUENCER_44] = 0x2fff, - [WM8915_WRITE_SEQUENCER_48] = 0x2fff, - [WM8915_WRITE_SEQUENCER_52] = 0x2fff, - [WM8915_WRITE_SEQUENCER_56] = 0x2fff, - [WM8915_WRITE_SEQUENCER_60] = 0x2fff, - [WM8915_WRITE_SEQUENCER_64] = 0x1, - [WM8915_WRITE_SEQUENCER_65] = 0x1, - [WM8915_WRITE_SEQUENCER_67] = 0x6, - [WM8915_WRITE_SEQUENCER_68] = 0x40, - [WM8915_WRITE_SEQUENCER_69] = 0x1, - [WM8915_WRITE_SEQUENCER_70] = 0xf, - [WM8915_WRITE_SEQUENCER_71] = 0x6, - [WM8915_WRITE_SEQUENCER_72] = 0x1, - [WM8915_WRITE_SEQUENCER_73] = 0x3, - [WM8915_WRITE_SEQUENCER_74] = 0x104, - [WM8915_WRITE_SEQUENCER_76] = 0x60, - [WM8915_WRITE_SEQUENCER_77] = 0x11, - [WM8915_WRITE_SEQUENCER_78] = 0x401, - [WM8915_WRITE_SEQUENCER_80] = 0x50, - [WM8915_WRITE_SEQUENCER_81] = 0x3, - [WM8915_WRITE_SEQUENCER_82] = 0x100, - [WM8915_WRITE_SEQUENCER_84] = 0x60, - [WM8915_WRITE_SEQUENCER_85] = 0x3b, - [WM8915_WRITE_SEQUENCER_86] = 0x502, - [WM8915_WRITE_SEQUENCER_87] = 0x100, - [WM8915_WRITE_SEQUENCER_88] = 0x2fff, - [WM8915_WRITE_SEQUENCER_92] = 0x2fff, - [WM8915_WRITE_SEQUENCER_96] = 0x2fff, - [WM8915_WRITE_SEQUENCER_100] = 0x2fff, - [WM8915_WRITE_SEQUENCER_104] = 0x2fff, - [WM8915_WRITE_SEQUENCER_108] = 0x2fff, - [WM8915_WRITE_SEQUENCER_112] = 0x2fff, - [WM8915_WRITE_SEQUENCER_116] = 0x2fff, - [WM8915_WRITE_SEQUENCER_120] = 0x2fff, - [WM8915_WRITE_SEQUENCER_124] = 0x2fff, - [WM8915_WRITE_SEQUENCER_128] = 0x1, - [WM8915_WRITE_SEQUENCER_129] = 0x1, - [WM8915_WRITE_SEQUENCER_131] = 0x6, - [WM8915_WRITE_SEQUENCER_132] = 0x40, - [WM8915_WRITE_SEQUENCER_133] = 0x1, - [WM8915_WRITE_SEQUENCER_134] = 0xf, - [WM8915_WRITE_SEQUENCER_135] = 0x6, - [WM8915_WRITE_SEQUENCER_136] = 0x1, - [WM8915_WRITE_SEQUENCER_137] = 0x3, - [WM8915_WRITE_SEQUENCER_138] = 0x106, - [WM8915_WRITE_SEQUENCER_140] = 0x61, - [WM8915_WRITE_SEQUENCER_141] = 0x11, - [WM8915_WRITE_SEQUENCER_142] = 0x401, - [WM8915_WRITE_SEQUENCER_144] = 0x50, - [WM8915_WRITE_SEQUENCER_145] = 0x3, - [WM8915_WRITE_SEQUENCER_146] = 0x102, - [WM8915_WRITE_SEQUENCER_148] = 0x51, - [WM8915_WRITE_SEQUENCER_149] = 0x3, - [WM8915_WRITE_SEQUENCER_150] = 0x106, - [WM8915_WRITE_SEQUENCER_151] = 0xa, - [WM8915_WRITE_SEQUENCER_152] = 0x61, - [WM8915_WRITE_SEQUENCER_153] = 0x3b, - [WM8915_WRITE_SEQUENCER_154] = 0x502, - [WM8915_WRITE_SEQUENCER_155] = 0x100, - [WM8915_WRITE_SEQUENCER_156] = 0x2fff, - [WM8915_WRITE_SEQUENCER_160] = 0x2fff, - [WM8915_WRITE_SEQUENCER_164] = 0x2fff, - [WM8915_WRITE_SEQUENCER_168] = 0x2fff, - [WM8915_WRITE_SEQUENCER_172] = 0x2fff, - [WM8915_WRITE_SEQUENCER_176] = 0x2fff, - [WM8915_WRITE_SEQUENCER_180] = 0x2fff, - [WM8915_WRITE_SEQUENCER_184] = 0x2fff, - [WM8915_WRITE_SEQUENCER_188] = 0x2fff, - [WM8915_WRITE_SEQUENCER_192] = 0x1, - [WM8915_WRITE_SEQUENCER_193] = 0x1, - [WM8915_WRITE_SEQUENCER_195] = 0x6, - [WM8915_WRITE_SEQUENCER_196] = 0x40, - [WM8915_WRITE_SEQUENCER_197] = 0x1, - [WM8915_WRITE_SEQUENCER_198] = 0xf, - [WM8915_WRITE_SEQUENCER_199] = 0x6, - [WM8915_WRITE_SEQUENCER_200] = 0x1, - [WM8915_WRITE_SEQUENCER_201] = 0x3, - [WM8915_WRITE_SEQUENCER_202] = 0x106, - [WM8915_WRITE_SEQUENCER_204] = 0x61, - [WM8915_WRITE_SEQUENCER_205] = 0x11, - [WM8915_WRITE_SEQUENCER_206] = 0x401, - [WM8915_WRITE_SEQUENCER_208] = 0x50, - [WM8915_WRITE_SEQUENCER_209] = 0x3, - [WM8915_WRITE_SEQUENCER_210] = 0x102, - [WM8915_WRITE_SEQUENCER_212] = 0x61, - [WM8915_WRITE_SEQUENCER_213] = 0x3b, - [WM8915_WRITE_SEQUENCER_214] = 0x502, - [WM8915_WRITE_SEQUENCER_215] = 0x100, - [WM8915_WRITE_SEQUENCER_216] = 0x2fff, - [WM8915_WRITE_SEQUENCER_220] = 0x2fff, - [WM8915_WRITE_SEQUENCER_224] = 0x2fff, - [WM8915_WRITE_SEQUENCER_228] = 0x2fff, - [WM8915_WRITE_SEQUENCER_232] = 0x2fff, - [WM8915_WRITE_SEQUENCER_236] = 0x2fff, - [WM8915_WRITE_SEQUENCER_240] = 0x2fff, - [WM8915_WRITE_SEQUENCER_244] = 0x2fff, - [WM8915_WRITE_SEQUENCER_248] = 0x2fff, - [WM8915_WRITE_SEQUENCER_252] = 0x2fff, - [WM8915_WRITE_SEQUENCER_256] = 0x60, - [WM8915_WRITE_SEQUENCER_258] = 0x601, - [WM8915_WRITE_SEQUENCER_260] = 0x50, - [WM8915_WRITE_SEQUENCER_262] = 0x100, - [WM8915_WRITE_SEQUENCER_264] = 0x1, - [WM8915_WRITE_SEQUENCER_266] = 0x104, - [WM8915_WRITE_SEQUENCER_267] = 0x100, - [WM8915_WRITE_SEQUENCER_268] = 0x2fff, - [WM8915_WRITE_SEQUENCER_272] = 0x2fff, - [WM8915_WRITE_SEQUENCER_276] = 0x2fff, - [WM8915_WRITE_SEQUENCER_280] = 0x2fff, - [WM8915_WRITE_SEQUENCER_284] = 0x2fff, - [WM8915_WRITE_SEQUENCER_288] = 0x2fff, - [WM8915_WRITE_SEQUENCER_292] = 0x2fff, - [WM8915_WRITE_SEQUENCER_296] = 0x2fff, - [WM8915_WRITE_SEQUENCER_300] = 0x2fff, - [WM8915_WRITE_SEQUENCER_304] = 0x2fff, - [WM8915_WRITE_SEQUENCER_308] = 0x2fff, - [WM8915_WRITE_SEQUENCER_312] = 0x2fff, - [WM8915_WRITE_SEQUENCER_316] = 0x2fff, - [WM8915_WRITE_SEQUENCER_320] = 0x61, - [WM8915_WRITE_SEQUENCER_322] = 0x601, - [WM8915_WRITE_SEQUENCER_324] = 0x50, - [WM8915_WRITE_SEQUENCER_326] = 0x102, - [WM8915_WRITE_SEQUENCER_328] = 0x1, - [WM8915_WRITE_SEQUENCER_330] = 0x106, - [WM8915_WRITE_SEQUENCER_331] = 0x100, - [WM8915_WRITE_SEQUENCER_332] = 0x2fff, - [WM8915_WRITE_SEQUENCER_336] = 0x2fff, - [WM8915_WRITE_SEQUENCER_340] = 0x2fff, - [WM8915_WRITE_SEQUENCER_344] = 0x2fff, - [WM8915_WRITE_SEQUENCER_348] = 0x2fff, - [WM8915_WRITE_SEQUENCER_352] = 0x2fff, - [WM8915_WRITE_SEQUENCER_356] = 0x2fff, - [WM8915_WRITE_SEQUENCER_360] = 0x2fff, - [WM8915_WRITE_SEQUENCER_364] = 0x2fff, - [WM8915_WRITE_SEQUENCER_368] = 0x2fff, - [WM8915_WRITE_SEQUENCER_372] = 0x2fff, - [WM8915_WRITE_SEQUENCER_376] = 0x2fff, - [WM8915_WRITE_SEQUENCER_380] = 0x2fff, - [WM8915_WRITE_SEQUENCER_384] = 0x60, - [WM8915_WRITE_SEQUENCER_386] = 0x601, - [WM8915_WRITE_SEQUENCER_388] = 0x61, - [WM8915_WRITE_SEQUENCER_390] = 0x601, - [WM8915_WRITE_SEQUENCER_392] = 0x50, - [WM8915_WRITE_SEQUENCER_394] = 0x300, - [WM8915_WRITE_SEQUENCER_396] = 0x1, - [WM8915_WRITE_SEQUENCER_398] = 0x304, - [WM8915_WRITE_SEQUENCER_400] = 0x40, - [WM8915_WRITE_SEQUENCER_402] = 0xf, - [WM8915_WRITE_SEQUENCER_404] = 0x1, - [WM8915_WRITE_SEQUENCER_407] = 0x100, -}; - -static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); -static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); -static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); -static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); -static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); -static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); -static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); - -static const char *sidetone_hpf_text[] = { - "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" -}; - -static const struct soc_enum sidetone_hpf = - SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text); - -static const char *hpf_mode_text[] = { - "HiFi", "Custom", "Voice" -}; - -static const struct soc_enum dsp1tx_hpf_mode = - SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text); - -static const struct soc_enum dsp2tx_hpf_mode = - SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text); - -static const char *hpf_cutoff_text[] = { - "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" -}; - -static const struct soc_enum dsp1tx_hpf_cutoff = - SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text); - -static const struct soc_enum dsp2tx_hpf_cutoff = - SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text); - -static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - struct wm8915_pdata *pdata = &wm8915->pdata; - int base, best, best_val, save, i, cfg, iface; - - if (!wm8915->num_retune_mobile_texts) - return; - - switch (block) { - case 0: - base = WM8915_DSP1_RX_EQ_GAINS_1; - if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) & - WM8915_DSP1RX_SRC) - iface = 1; - else - iface = 0; - break; - case 1: - base = WM8915_DSP1_RX_EQ_GAINS_2; - if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) & - WM8915_DSP2RX_SRC) - iface = 1; - else - iface = 0; - break; - default: - return; - } - - /* Find the version of the currently selected configuration - * with the nearest sample rate. */ - cfg = wm8915->retune_mobile_cfg[block]; - best = 0; - best_val = INT_MAX; - for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { - if (strcmp(pdata->retune_mobile_cfgs[i].name, - wm8915->retune_mobile_texts[cfg]) == 0 && - abs(pdata->retune_mobile_cfgs[i].rate - - wm8915->rx_rate[iface]) < best_val) { - best = i; - best_val = abs(pdata->retune_mobile_cfgs[i].rate - - wm8915->rx_rate[iface]); - } - } - - dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", - block, - pdata->retune_mobile_cfgs[best].name, - pdata->retune_mobile_cfgs[best].rate, - wm8915->rx_rate[iface]); - - /* The EQ will be disabled while reconfiguring it, remember the - * current configuration. - */ - save = snd_soc_read(codec, base); - save &= WM8915_DSP1RX_EQ_ENA; - - for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) - snd_soc_update_bits(codec, base + i, 0xffff, - pdata->retune_mobile_cfgs[best].regs[i]); - - snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save); -} - -/* Icky as hell but saves code duplication */ -static int wm8915_get_retune_mobile_block(const char *name) -{ - if (strcmp(name, "DSP1 EQ Mode") == 0) - return 0; - if (strcmp(name, "DSP2 EQ Mode") == 0) - return 1; - return -EINVAL; -} - -static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - struct wm8915_pdata *pdata = &wm8915->pdata; - int block = wm8915_get_retune_mobile_block(kcontrol->id.name); - int value = ucontrol->value.integer.value[0]; - - if (block < 0) - return block; - - if (value >= pdata->num_retune_mobile_cfgs) - return -EINVAL; - - wm8915->retune_mobile_cfg[block] = value; - - wm8915_set_retune_mobile(codec, block); - - return 0; -} - -static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int block = wm8915_get_retune_mobile_block(kcontrol->id.name); - - ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block]; - - return 0; -} - -static const struct snd_kcontrol_new wm8915_snd_controls[] = { -SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME, - WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), -SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME, - WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), - -SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES, - 0, 5, 24, 0, sidetone_tlv), -SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES, - 0, 5, 24, 0, sidetone_tlv), -SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0), -SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), -SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0), - -SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME, - WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), -SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME, - WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), - -SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS, - 13, 1, 0), -SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0), -SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), -SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), - -SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS, - 13, 1, 0), -SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0), -SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), -SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), - -SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME, - WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), -SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1), - -SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME, - WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), -SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1), - -SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME, - WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), -SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME, - WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1), - -SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME, - WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), -SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME, - WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1), - -SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0), -SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0), -SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0), -SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0), - -SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0), -SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0), - -SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4, - 8, 0, out_digital_tlv), -SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4, - 8, 0, out_digital_tlv), - -SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME, - WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), -SOC_DOUBLE_R("Output 1 ZC Switch", WM8915_OUTPUT1_LEFT_VOLUME, - WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), - -SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME, - WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), -SOC_DOUBLE_R("Output 2 ZC Switch", WM8915_OUTPUT2_LEFT_VOLUME, - WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), - -SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, - spk_tlv), -SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER, - WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1), -SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER, - WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0), - -SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0), -SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0), -}; - -static const struct snd_kcontrol_new wm8915_eq_controls[] = { -SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0, - eq_tlv), - -SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0, - eq_tlv), -SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0, - eq_tlv), -}; - -static int cp_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - switch (event) { - case SND_SOC_DAPM_POST_PMU: - msleep(5); - break; - default: - BUG(); - return -EINVAL; - } - - return 0; -} - -static int rmv_short_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec); - - /* Record which outputs we enabled */ - switch (event) { - case SND_SOC_DAPM_PRE_PMD: - wm8915->hpout_pending &= ~w->shift; - break; - case SND_SOC_DAPM_PRE_PMU: - wm8915->hpout_pending |= w->shift; - break; - default: - BUG(); - return -EINVAL; - } - - return 0; -} - -static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) -{ - struct i2c_client *i2c = to_i2c_client(codec->dev); - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int i, ret; - unsigned long timeout = 200; - - snd_soc_write(codec, WM8915_DC_SERVO_2, mask); - - /* Use the interrupt if possible */ - do { - if (i2c->irq) { - timeout = wait_for_completion_timeout(&wm8915->dcs_done, - msecs_to_jiffies(200)); - if (timeout == 0) - dev_err(codec->dev, "DC servo timed out\n"); - - } else { - msleep(1); - if (--i) { - timeout = 0; - break; - } - } - - ret = snd_soc_read(codec, WM8915_DC_SERVO_2); - dev_dbg(codec->dev, "DC servo state: %x\n", ret); - } while (ret & mask); - - if (timeout == 0) - dev_err(codec->dev, "DC servo timed out for %x\n", mask); - else - dev_dbg(codec->dev, "DC servo complete for %x\n", mask); -} - -static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm, - enum snd_soc_dapm_type event, int subseq) -{ - struct snd_soc_codec *codec = container_of(dapm, - struct snd_soc_codec, dapm); - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - u16 val, mask; - - /* Complete any pending DC servo starts */ - if (wm8915->dcs_pending) { - dev_dbg(codec->dev, "Starting DC servo for %x\n", - wm8915->dcs_pending); - - /* Trigger a startup sequence */ - wait_for_dc_servo(codec, wm8915->dcs_pending - << WM8915_DCS_TRIG_STARTUP_0_SHIFT); - - wm8915->dcs_pending = 0; - } - - if (wm8915->hpout_pending != wm8915->hpout_ena) { - dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", - wm8915->hpout_ena, wm8915->hpout_pending); - - val = 0; - mask = 0; - if (wm8915->hpout_pending & HPOUT1L) { - val |= WM8915_HPOUT1L_RMV_SHORT; - mask |= WM8915_HPOUT1L_RMV_SHORT; - } else { - mask |= WM8915_HPOUT1L_RMV_SHORT | - WM8915_HPOUT1L_OUTP | - WM8915_HPOUT1L_DLY; - } - - if (wm8915->hpout_pending & HPOUT1R) { - val |= WM8915_HPOUT1R_RMV_SHORT; - mask |= WM8915_HPOUT1R_RMV_SHORT; - } else { - mask |= WM8915_HPOUT1R_RMV_SHORT | - WM8915_HPOUT1R_OUTP | - WM8915_HPOUT1R_DLY; - } - - snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val); - - val = 0; - mask = 0; - if (wm8915->hpout_pending & HPOUT2L) { - val |= WM8915_HPOUT2L_RMV_SHORT; - mask |= WM8915_HPOUT2L_RMV_SHORT; - } else { - mask |= WM8915_HPOUT2L_RMV_SHORT | - WM8915_HPOUT2L_OUTP | - WM8915_HPOUT2L_DLY; - } - - if (wm8915->hpout_pending & HPOUT2R) { - val |= WM8915_HPOUT2R_RMV_SHORT; - mask |= WM8915_HPOUT2R_RMV_SHORT; - } else { - mask |= WM8915_HPOUT2R_RMV_SHORT | - WM8915_HPOUT2R_OUTP | - WM8915_HPOUT2R_DLY; - } - - snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val); - - wm8915->hpout_ena = wm8915->hpout_pending; - } -} - -static int dcs_start(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec); - - switch (event) { - case SND_SOC_DAPM_POST_PMU: - wm8915->dcs_pending |= 1 << w->shift; - break; - default: - BUG(); - return -EINVAL; - } - - return 0; -} - -static const char *sidetone_text[] = { - "IN1", "IN2", -}; - -static const struct soc_enum left_sidetone_enum = - SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text); - -static const struct snd_kcontrol_new left_sidetone = - SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); - -static const struct soc_enum right_sidetone_enum = - SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text); - -static const struct snd_kcontrol_new right_sidetone = - SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); - -static const char *spk_text[] = { - "DAC1L", "DAC1R", "DAC2L", "DAC2R" -}; - -static const struct soc_enum spkl_enum = - SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text); - -static const struct snd_kcontrol_new spkl_mux = - SOC_DAPM_ENUM("SPKL", spkl_enum); - -static const struct soc_enum spkr_enum = - SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text); - -static const struct snd_kcontrol_new spkr_mux = - SOC_DAPM_ENUM("SPKR", spkr_enum); - -static const char *dsp1rx_text[] = { - "AIF1", "AIF2" -}; - -static const struct soc_enum dsp1rx_enum = - SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text); - -static const struct snd_kcontrol_new dsp1rx = - SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); - -static const char *dsp2rx_text[] = { - "AIF2", "AIF1" -}; - -static const struct soc_enum dsp2rx_enum = - SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text); - -static const struct snd_kcontrol_new dsp2rx = - SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); - -static const char *aif2tx_text[] = { - "DSP2", "DSP1", "AIF1" -}; - -static const struct soc_enum aif2tx_enum = - SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text); - -static const struct snd_kcontrol_new aif2tx = - SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); - -static const char *inmux_text[] = { - "ADC", "DMIC1", "DMIC2" -}; - -static const struct soc_enum in1_enum = - SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text); - -static const struct snd_kcontrol_new in1_mux = - SOC_DAPM_ENUM("IN1 Mux", in1_enum); - -static const struct soc_enum in2_enum = - SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text); - -static const struct snd_kcontrol_new in2_mux = - SOC_DAPM_ENUM("IN2 Mux", in2_enum); - -static const struct snd_kcontrol_new dac2r_mix[] = { -SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, - 5, 1, 0), -SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, - 4, 1, 0), -SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), -SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), -}; - -static const struct snd_kcontrol_new dac2l_mix[] = { -SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, - 5, 1, 0), -SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, - 4, 1, 0), -SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), -SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), -}; - -static const struct snd_kcontrol_new dac1r_mix[] = { -SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, - 5, 1, 0), -SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, - 4, 1, 0), -SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), -SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), -}; - -static const struct snd_kcontrol_new dac1l_mix[] = { -SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, - 5, 1, 0), -SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, - 4, 1, 0), -SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), -SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), -}; - -static const struct snd_kcontrol_new dsp1txl[] = { -SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING, - 1, 1, 0), -SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new dsp1txr[] = { -SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING, - 1, 1, 0), -SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new dsp2txl[] = { -SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING, - 1, 1, 0), -SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new dsp2txr[] = { -SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING, - 1, 1, 0), -SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING, - 0, 1, 0), -}; - - -static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = { -SND_SOC_DAPM_INPUT("IN1LN"), -SND_SOC_DAPM_INPUT("IN1LP"), -SND_SOC_DAPM_INPUT("IN1RN"), -SND_SOC_DAPM_INPUT("IN1RP"), - -SND_SOC_DAPM_INPUT("IN2LN"), -SND_SOC_DAPM_INPUT("IN2LP"), -SND_SOC_DAPM_INPUT("IN2RN"), -SND_SOC_DAPM_INPUT("IN2RP"), - -SND_SOC_DAPM_INPUT("DMIC1DAT"), -SND_SOC_DAPM_INPUT("DMIC2DAT"), - -SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0), -SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0), -SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0), -SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event, - SND_SOC_DAPM_POST_PMU), - -SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0), -SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0), -SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0), - -SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0), -SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0), - -SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux), -SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux), -SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux), -SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux), - -SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0), -SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0), -SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0), -SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0), - -SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0), -SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0), - -SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0), -SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0), -SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0), -SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0), - -SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0), -SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0), - -SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), -SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), - -SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0), -SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0), -SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0), -SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0), - -SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0, - dsp2txl, ARRAY_SIZE(dsp2txl)), -SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0, - dsp2txr, ARRAY_SIZE(dsp2txr)), -SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0, - dsp1txl, ARRAY_SIZE(dsp1txl)), -SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0, - dsp1txr, ARRAY_SIZE(dsp1txr)), - -SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, - dac2l_mix, ARRAY_SIZE(dac2l_mix)), -SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, - dac2r_mix, ARRAY_SIZE(dac2r_mix)), -SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, - dac1l_mix, ARRAY_SIZE(dac1l_mix)), -SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, - dac1r_mix, ARRAY_SIZE(dac1r_mix)), - -SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0), -SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0), -SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0), -SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0), - -SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1, - WM8915_POWER_MANAGEMENT_4, 9, 0), -SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2, - WM8915_POWER_MANAGEMENT_4, 8, 0), - -SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1, - WM8915_POWER_MANAGEMENT_6, 9, 0), -SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2, - WM8915_POWER_MANAGEMENT_6, 8, 0), - -SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5, - WM8915_POWER_MANAGEMENT_4, 5, 0), -SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4, - WM8915_POWER_MANAGEMENT_4, 4, 0), -SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3, - WM8915_POWER_MANAGEMENT_4, 3, 0), -SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2, - WM8915_POWER_MANAGEMENT_4, 2, 0), -SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1, - WM8915_POWER_MANAGEMENT_4, 1, 0), -SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0, - WM8915_POWER_MANAGEMENT_4, 0, 0), - -SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5, - WM8915_POWER_MANAGEMENT_6, 5, 0), -SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4, - WM8915_POWER_MANAGEMENT_6, 4, 0), -SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3, - WM8915_POWER_MANAGEMENT_6, 3, 0), -SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2, - WM8915_POWER_MANAGEMENT_6, 2, 0), -SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1, - WM8915_POWER_MANAGEMENT_6, 1, 0), -SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0, - WM8915_POWER_MANAGEMENT_6, 0, 0), - -/* We route as stereo pairs so define some dummy widgets to squash - * things down for now. RXA = 0,1, RXB = 2,3 and so on */ -SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), -SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), -SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), -SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), -SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), - -SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), -SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), -SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), - -SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), -SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), -SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), -SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), - -SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start, - SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, - rmv_short_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), - -SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start, - SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, - rmv_short_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), - -SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start, - SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, - rmv_short_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), - -SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start, - SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0), -SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, - rmv_short_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), - -SND_SOC_DAPM_OUTPUT("HPOUT1L"), -SND_SOC_DAPM_OUTPUT("HPOUT1R"), -SND_SOC_DAPM_OUTPUT("HPOUT2L"), -SND_SOC_DAPM_OUTPUT("HPOUT2R"), -SND_SOC_DAPM_OUTPUT("SPKDAT"), -}; - -static const struct snd_soc_dapm_route wm8915_dapm_routes[] = { - { "AIFCLK", NULL, "SYSCLK" }, - { "SYSDSPCLK", NULL, "SYSCLK" }, - { "Charge Pump", NULL, "SYSCLK" }, - - { "MICB1", NULL, "LDO2" }, - { "MICB2", NULL, "LDO2" }, - - { "IN1L PGA", NULL, "IN2LN" }, - { "IN1L PGA", NULL, "IN2LP" }, - { "IN1L PGA", NULL, "IN1LN" }, - { "IN1L PGA", NULL, "IN1LP" }, - - { "IN1R PGA", NULL, "IN2RN" }, - { "IN1R PGA", NULL, "IN2RP" }, - { "IN1R PGA", NULL, "IN1RN" }, - { "IN1R PGA", NULL, "IN1RP" }, - - { "ADCL", NULL, "IN1L PGA" }, - - { "ADCR", NULL, "IN1R PGA" }, - - { "DMIC1L", NULL, "DMIC1DAT" }, - { "DMIC1R", NULL, "DMIC1DAT" }, - { "DMIC2L", NULL, "DMIC2DAT" }, - { "DMIC2R", NULL, "DMIC2DAT" }, - - { "DMIC2L", NULL, "DMIC2" }, - { "DMIC2R", NULL, "DMIC2" }, - { "DMIC1L", NULL, "DMIC1" }, - { "DMIC1R", NULL, "DMIC1" }, - - { "IN1L Mux", "ADC", "ADCL" }, - { "IN1L Mux", "DMIC1", "DMIC1L" }, - { "IN1L Mux", "DMIC2", "DMIC2L" }, - - { "IN1R Mux", "ADC", "ADCR" }, - { "IN1R Mux", "DMIC1", "DMIC1R" }, - { "IN1R Mux", "DMIC2", "DMIC2R" }, - - { "IN2L Mux", "ADC", "ADCL" }, - { "IN2L Mux", "DMIC1", "DMIC1L" }, - { "IN2L Mux", "DMIC2", "DMIC2L" }, - - { "IN2R Mux", "ADC", "ADCR" }, - { "IN2R Mux", "DMIC1", "DMIC1R" }, - { "IN2R Mux", "DMIC2", "DMIC2R" }, - - { "Left Sidetone", "IN1", "IN1L Mux" }, - { "Left Sidetone", "IN2", "IN2L Mux" }, - - { "Right Sidetone", "IN1", "IN1R Mux" }, - { "Right Sidetone", "IN2", "IN2R Mux" }, - - { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, - { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, - - { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, - { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, - - { "AIF1TX0", NULL, "DSP1TXL" }, - { "AIF1TX1", NULL, "DSP1TXR" }, - { "AIF1TX2", NULL, "DSP2TXL" }, - { "AIF1TX3", NULL, "DSP2TXR" }, - { "AIF1TX4", NULL, "AIF2RX0" }, - { "AIF1TX5", NULL, "AIF2RX1" }, - - { "AIF1RX0", NULL, "AIFCLK" }, - { "AIF1RX1", NULL, "AIFCLK" }, - { "AIF1RX2", NULL, "AIFCLK" }, - { "AIF1RX3", NULL, "AIFCLK" }, - { "AIF1RX4", NULL, "AIFCLK" }, - { "AIF1RX5", NULL, "AIFCLK" }, - - { "AIF2RX0", NULL, "AIFCLK" }, - { "AIF2RX1", NULL, "AIFCLK" }, - - { "DSP1RXL", NULL, "SYSDSPCLK" }, - { "DSP1RXR", NULL, "SYSDSPCLK" }, - { "DSP2RXL", NULL, "SYSDSPCLK" }, - { "DSP2RXR", NULL, "SYSDSPCLK" }, - { "DSP1TXL", NULL, "SYSDSPCLK" }, - { "DSP1TXR", NULL, "SYSDSPCLK" }, - { "DSP2TXL", NULL, "SYSDSPCLK" }, - { "DSP2TXR", NULL, "SYSDSPCLK" }, - - { "AIF1RXA", NULL, "AIF1RX0" }, - { "AIF1RXA", NULL, "AIF1RX1" }, - { "AIF1RXB", NULL, "AIF1RX2" }, - { "AIF1RXB", NULL, "AIF1RX3" }, - { "AIF1RXC", NULL, "AIF1RX4" }, - { "AIF1RXC", NULL, "AIF1RX5" }, - - { "AIF2RX", NULL, "AIF2RX0" }, - { "AIF2RX", NULL, "AIF2RX1" }, - - { "AIF2TX", "DSP2", "DSP2TX" }, - { "AIF2TX", "DSP1", "DSP1RX" }, - { "AIF2TX", "AIF1", "AIF1RXC" }, - - { "DSP1RXL", NULL, "DSP1RX" }, - { "DSP1RXR", NULL, "DSP1RX" }, - { "DSP2RXL", NULL, "DSP2RX" }, - { "DSP2RXR", NULL, "DSP2RX" }, - - { "DSP2TX", NULL, "DSP2TXL" }, - { "DSP2TX", NULL, "DSP2TXR" }, - - { "DSP1RX", "AIF1", "AIF1RXA" }, - { "DSP1RX", "AIF2", "AIF2RX" }, - - { "DSP2RX", "AIF1", "AIF1RXB" }, - { "DSP2RX", "AIF2", "AIF2RX" }, - - { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, - { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, - { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, - { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, - - { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, - { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, - { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, - { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, - - { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, - { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, - { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, - { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, - - { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, - { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, - { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, - { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, - - { "DAC1L", NULL, "DAC1L Mixer" }, - { "DAC1R", NULL, "DAC1R Mixer" }, - { "DAC2L", NULL, "DAC2L Mixer" }, - { "DAC2R", NULL, "DAC2R Mixer" }, - - { "HPOUT2L PGA", NULL, "Charge Pump" }, - { "HPOUT2L PGA", NULL, "DAC2L" }, - { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, - { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, - { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" }, - { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" }, - - { "HPOUT2R PGA", NULL, "Charge Pump" }, - { "HPOUT2R PGA", NULL, "DAC2R" }, - { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, - { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, - { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" }, - { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" }, - - { "HPOUT1L PGA", NULL, "Charge Pump" }, - { "HPOUT1L PGA", NULL, "DAC1L" }, - { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, - { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, - { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" }, - { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" }, - - { "HPOUT1R PGA", NULL, "Charge Pump" }, - { "HPOUT1R PGA", NULL, "DAC1R" }, - { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, - { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, - { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" }, - { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" }, - - { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, - { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, - { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, - { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, - - { "SPKL", "DAC1L", "DAC1L" }, - { "SPKL", "DAC1R", "DAC1R" }, - { "SPKL", "DAC2L", "DAC2L" }, - { "SPKL", "DAC2R", "DAC2R" }, - - { "SPKR", "DAC1L", "DAC1L" }, - { "SPKR", "DAC1R", "DAC1R" }, - { "SPKR", "DAC2L", "DAC2L" }, - { "SPKR", "DAC2R", "DAC2R" }, - - { "SPKL PGA", NULL, "SPKL" }, - { "SPKR PGA", NULL, "SPKR" }, - - { "SPKDAT", NULL, "SPKL PGA" }, - { "SPKDAT", NULL, "SPKR PGA" }, -}; - -static int wm8915_readable_register(struct snd_soc_codec *codec, - unsigned int reg) -{ - /* Due to the sparseness of the register map the compiler - * output from an explicit switch statement ends up being much - * more efficient than a table. - */ - switch (reg) { - case WM8915_SOFTWARE_RESET: - case WM8915_POWER_MANAGEMENT_1: - case WM8915_POWER_MANAGEMENT_2: - case WM8915_POWER_MANAGEMENT_3: - case WM8915_POWER_MANAGEMENT_4: - case WM8915_POWER_MANAGEMENT_5: - case WM8915_POWER_MANAGEMENT_6: - case WM8915_POWER_MANAGEMENT_7: - case WM8915_POWER_MANAGEMENT_8: - case WM8915_LEFT_LINE_INPUT_VOLUME: - case WM8915_RIGHT_LINE_INPUT_VOLUME: - case WM8915_LINE_INPUT_CONTROL: - case WM8915_DAC1_HPOUT1_VOLUME: - case WM8915_DAC2_HPOUT2_VOLUME: - case WM8915_DAC1_LEFT_VOLUME: - case WM8915_DAC1_RIGHT_VOLUME: - case WM8915_DAC2_LEFT_VOLUME: - case WM8915_DAC2_RIGHT_VOLUME: - case WM8915_OUTPUT1_LEFT_VOLUME: - case WM8915_OUTPUT1_RIGHT_VOLUME: - case WM8915_OUTPUT2_LEFT_VOLUME: - case WM8915_OUTPUT2_RIGHT_VOLUME: - case WM8915_MICBIAS_1: - case WM8915_MICBIAS_2: - case WM8915_LDO_1: - case WM8915_LDO_2: - case WM8915_ACCESSORY_DETECT_MODE_1: - case WM8915_ACCESSORY_DETECT_MODE_2: - case WM8915_HEADPHONE_DETECT_1: - case WM8915_HEADPHONE_DETECT_2: - case WM8915_MIC_DETECT_1: - case WM8915_MIC_DETECT_2: - case WM8915_MIC_DETECT_3: - case WM8915_CHARGE_PUMP_1: - case WM8915_CHARGE_PUMP_2: - case WM8915_DC_SERVO_1: - case WM8915_DC_SERVO_2: - case WM8915_DC_SERVO_3: - case WM8915_DC_SERVO_5: - case WM8915_DC_SERVO_6: - case WM8915_DC_SERVO_7: - case WM8915_DC_SERVO_READBACK_0: - case WM8915_ANALOGUE_HP_1: - case WM8915_ANALOGUE_HP_2: - case WM8915_CHIP_REVISION: - case WM8915_CONTROL_INTERFACE_1: - case WM8915_WRITE_SEQUENCER_CTRL_1: - case WM8915_WRITE_SEQUENCER_CTRL_2: - case WM8915_AIF_CLOCKING_1: - case WM8915_AIF_CLOCKING_2: - case WM8915_CLOCKING_1: - case WM8915_CLOCKING_2: - case WM8915_AIF_RATE: - case WM8915_FLL_CONTROL_1: - case WM8915_FLL_CONTROL_2: - case WM8915_FLL_CONTROL_3: - case WM8915_FLL_CONTROL_4: - case WM8915_FLL_CONTROL_5: - case WM8915_FLL_CONTROL_6: - case WM8915_FLL_EFS_1: - case WM8915_FLL_EFS_2: - case WM8915_AIF1_CONTROL: - case WM8915_AIF1_BCLK: - case WM8915_AIF1_TX_LRCLK_1: - case WM8915_AIF1_TX_LRCLK_2: - case WM8915_AIF1_RX_LRCLK_1: - case WM8915_AIF1_RX_LRCLK_2: - case WM8915_AIF1TX_DATA_CONFIGURATION_1: - case WM8915_AIF1TX_DATA_CONFIGURATION_2: - case WM8915_AIF1RX_DATA_CONFIGURATION: - case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION: - case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION: - case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION: - case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION: - case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION: - case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION: - case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION: - case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION: - case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION: - case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION: - case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION: - case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION: - case WM8915_AIF1RX_MONO_CONFIGURATION: - case WM8915_AIF1TX_TEST: - case WM8915_AIF2_CONTROL: - case WM8915_AIF2_BCLK: - case WM8915_AIF2_TX_LRCLK_1: - case WM8915_AIF2_TX_LRCLK_2: - case WM8915_AIF2_RX_LRCLK_1: - case WM8915_AIF2_RX_LRCLK_2: - case WM8915_AIF2TX_DATA_CONFIGURATION_1: - case WM8915_AIF2TX_DATA_CONFIGURATION_2: - case WM8915_AIF2RX_DATA_CONFIGURATION: - case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION: - case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION: - case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION: - case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION: - case WM8915_AIF2RX_MONO_CONFIGURATION: - case WM8915_AIF2TX_TEST: - case WM8915_DSP1_TX_LEFT_VOLUME: - case WM8915_DSP1_TX_RIGHT_VOLUME: - case WM8915_DSP1_RX_LEFT_VOLUME: - case WM8915_DSP1_RX_RIGHT_VOLUME: - case WM8915_DSP1_TX_FILTERS: - case WM8915_DSP1_RX_FILTERS_1: - case WM8915_DSP1_RX_FILTERS_2: - case WM8915_DSP1_DRC_1: - case WM8915_DSP1_DRC_2: - case WM8915_DSP1_DRC_3: - case WM8915_DSP1_DRC_4: - case WM8915_DSP1_DRC_5: - case WM8915_DSP1_RX_EQ_GAINS_1: - case WM8915_DSP1_RX_EQ_GAINS_2: - case WM8915_DSP1_RX_EQ_BAND_1_A: - case WM8915_DSP1_RX_EQ_BAND_1_B: - case WM8915_DSP1_RX_EQ_BAND_1_PG: - case WM8915_DSP1_RX_EQ_BAND_2_A: - case WM8915_DSP1_RX_EQ_BAND_2_B: - case WM8915_DSP1_RX_EQ_BAND_2_C: - case WM8915_DSP1_RX_EQ_BAND_2_PG: - case WM8915_DSP1_RX_EQ_BAND_3_A: - case WM8915_DSP1_RX_EQ_BAND_3_B: - case WM8915_DSP1_RX_EQ_BAND_3_C: - case WM8915_DSP1_RX_EQ_BAND_3_PG: - case WM8915_DSP1_RX_EQ_BAND_4_A: - case WM8915_DSP1_RX_EQ_BAND_4_B: - case WM8915_DSP1_RX_EQ_BAND_4_C: - case WM8915_DSP1_RX_EQ_BAND_4_PG: - case WM8915_DSP1_RX_EQ_BAND_5_A: - case WM8915_DSP1_RX_EQ_BAND_5_B: - case WM8915_DSP1_RX_EQ_BAND_5_PG: - case WM8915_DSP2_TX_LEFT_VOLUME: - case WM8915_DSP2_TX_RIGHT_VOLUME: - case WM8915_DSP2_RX_LEFT_VOLUME: - case WM8915_DSP2_RX_RIGHT_VOLUME: - case WM8915_DSP2_TX_FILTERS: - case WM8915_DSP2_RX_FILTERS_1: - case WM8915_DSP2_RX_FILTERS_2: - case WM8915_DSP2_DRC_1: - case WM8915_DSP2_DRC_2: - case WM8915_DSP2_DRC_3: - case WM8915_DSP2_DRC_4: - case WM8915_DSP2_DRC_5: - case WM8915_DSP2_RX_EQ_GAINS_1: - case WM8915_DSP2_RX_EQ_GAINS_2: - case WM8915_DSP2_RX_EQ_BAND_1_A: - case WM8915_DSP2_RX_EQ_BAND_1_B: - case WM8915_DSP2_RX_EQ_BAND_1_PG: - case WM8915_DSP2_RX_EQ_BAND_2_A: - case WM8915_DSP2_RX_EQ_BAND_2_B: - case WM8915_DSP2_RX_EQ_BAND_2_C: - case WM8915_DSP2_RX_EQ_BAND_2_PG: - case WM8915_DSP2_RX_EQ_BAND_3_A: - case WM8915_DSP2_RX_EQ_BAND_3_B: - case WM8915_DSP2_RX_EQ_BAND_3_C: - case WM8915_DSP2_RX_EQ_BAND_3_PG: - case WM8915_DSP2_RX_EQ_BAND_4_A: - case WM8915_DSP2_RX_EQ_BAND_4_B: - case WM8915_DSP2_RX_EQ_BAND_4_C: - case WM8915_DSP2_RX_EQ_BAND_4_PG: - case WM8915_DSP2_RX_EQ_BAND_5_A: - case WM8915_DSP2_RX_EQ_BAND_5_B: - case WM8915_DSP2_RX_EQ_BAND_5_PG: - case WM8915_DAC1_MIXER_VOLUMES: - case WM8915_DAC1_LEFT_MIXER_ROUTING: - case WM8915_DAC1_RIGHT_MIXER_ROUTING: - case WM8915_DAC2_MIXER_VOLUMES: - case WM8915_DAC2_LEFT_MIXER_ROUTING: - case WM8915_DAC2_RIGHT_MIXER_ROUTING: - case WM8915_DSP1_TX_LEFT_MIXER_ROUTING: - case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING: - case WM8915_DSP2_TX_LEFT_MIXER_ROUTING: - case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING: - case WM8915_DSP_TX_MIXER_SELECT: - case WM8915_DAC_SOFTMUTE: - case WM8915_OVERSAMPLING: - case WM8915_SIDETONE: - case WM8915_GPIO_1: - case WM8915_GPIO_2: - case WM8915_GPIO_3: - case WM8915_GPIO_4: - case WM8915_GPIO_5: - case WM8915_PULL_CONTROL_1: - case WM8915_PULL_CONTROL_2: - case WM8915_INTERRUPT_STATUS_1: - case WM8915_INTERRUPT_STATUS_2: - case WM8915_INTERRUPT_RAW_STATUS_2: - case WM8915_INTERRUPT_STATUS_1_MASK: - case WM8915_INTERRUPT_STATUS_2_MASK: - case WM8915_INTERRUPT_CONTROL: - case WM8915_LEFT_PDM_SPEAKER: - case WM8915_RIGHT_PDM_SPEAKER: - case WM8915_PDM_SPEAKER_MUTE_SEQUENCE: - case WM8915_PDM_SPEAKER_VOLUME: - return 1; - default: - return 0; - } -} - -static int wm8915_volatile_register(struct snd_soc_codec *codec, - unsigned int reg) -{ - switch (reg) { - case WM8915_SOFTWARE_RESET: - case WM8915_CHIP_REVISION: - case WM8915_LDO_1: - case WM8915_LDO_2: - case WM8915_INTERRUPT_STATUS_1: - case WM8915_INTERRUPT_STATUS_2: - case WM8915_INTERRUPT_RAW_STATUS_2: - case WM8915_DC_SERVO_READBACK_0: - case WM8915_DC_SERVO_2: - case WM8915_DC_SERVO_6: - case WM8915_DC_SERVO_7: - case WM8915_FLL_CONTROL_6: - case WM8915_MIC_DETECT_3: - case WM8915_HEADPHONE_DETECT_1: - case WM8915_HEADPHONE_DETECT_2: - return 1; - default: - return 0; - } -} - -static int wm8915_reset(struct snd_soc_codec *codec) -{ - return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915); -} - -static const int bclk_divs[] = { - 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 -}; - -static void wm8915_update_bclk(struct snd_soc_codec *codec) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int aif, best, cur_val, bclk_rate, bclk_reg, i; - - /* Don't bother if we're in a low frequency idle mode that - * can't support audio. - */ - if (wm8915->sysclk < 64000) - return; - - for (aif = 0; aif < WM8915_AIFS; aif++) { - switch (aif) { - case 0: - bclk_reg = WM8915_AIF1_BCLK; - break; - case 1: - bclk_reg = WM8915_AIF2_BCLK; - break; - } - - bclk_rate = wm8915->bclk_rate[aif]; - - /* Pick a divisor for BCLK as close as we can get to ideal */ - best = 0; - for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { - cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate; - if (cur_val < 0) /* BCLK table is sorted */ - break; - best = i; - } - bclk_rate = wm8915->sysclk / bclk_divs[best]; - dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", - bclk_divs[best], bclk_rate); - - snd_soc_update_bits(codec, bclk_reg, - WM8915_AIF1_BCLK_DIV_MASK, best); - } -} - -static int wm8915_set_bias_level(struct snd_soc_codec *codec, - enum snd_soc_bias_level level) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int ret; - - switch (level) { - case SND_SOC_BIAS_ON: - break; - - case SND_SOC_BIAS_PREPARE: - if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { - snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1, - WM8915_BG_ENA, WM8915_BG_ENA); - msleep(2); - } - break; - - case SND_SOC_BIAS_STANDBY: - if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { - ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies), - wm8915->supplies); - if (ret != 0) { - dev_err(codec->dev, - "Failed to enable supplies: %d\n", - ret); - return ret; - } - - if (wm8915->pdata.ldo_ena >= 0) { - gpio_set_value_cansleep(wm8915->pdata.ldo_ena, - 1); - msleep(5); - } - - codec->cache_only = false; - snd_soc_cache_sync(codec); - } - - snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1, - WM8915_BG_ENA, 0); - break; - - case SND_SOC_BIAS_OFF: - codec->cache_only = true; - if (wm8915->pdata.ldo_ena >= 0) - gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0); - regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), - wm8915->supplies); - break; - } - - codec->dapm.bias_level = level; - - return 0; -} - -static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -{ - struct snd_soc_codec *codec = dai->codec; - int aifctrl = 0; - int bclk = 0; - int lrclk_tx = 0; - int lrclk_rx = 0; - int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; - - switch (dai->id) { - case 0: - aifctrl_reg = WM8915_AIF1_CONTROL; - bclk_reg = WM8915_AIF1_BCLK; - lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2; - lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2; - break; - case 1: - aifctrl_reg = WM8915_AIF2_CONTROL; - bclk_reg = WM8915_AIF2_BCLK; - lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2; - lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2; - break; - default: - BUG(); - return -EINVAL; - } - - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { - case SND_SOC_DAIFMT_NB_NF: - break; - case SND_SOC_DAIFMT_IB_NF: - bclk |= WM8915_AIF1_BCLK_INV; - break; - case SND_SOC_DAIFMT_NB_IF: - lrclk_tx |= WM8915_AIF1TX_LRCLK_INV; - lrclk_rx |= WM8915_AIF1RX_LRCLK_INV; - break; - case SND_SOC_DAIFMT_IB_IF: - bclk |= WM8915_AIF1_BCLK_INV; - lrclk_tx |= WM8915_AIF1TX_LRCLK_INV; - lrclk_rx |= WM8915_AIF1RX_LRCLK_INV; - break; - } - - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBS_CFS: - break; - case SND_SOC_DAIFMT_CBS_CFM: - lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR; - lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR; - break; - case SND_SOC_DAIFMT_CBM_CFS: - bclk |= WM8915_AIF1_BCLK_MSTR; - break; - case SND_SOC_DAIFMT_CBM_CFM: - bclk |= WM8915_AIF1_BCLK_MSTR; - lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR; - lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR; - break; - default: - return -EINVAL; - } - - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_DSP_A: - break; - case SND_SOC_DAIFMT_DSP_B: - aifctrl |= 1; - break; - case SND_SOC_DAIFMT_I2S: - aifctrl |= 2; - break; - case SND_SOC_DAIFMT_LEFT_J: - aifctrl |= 3; - break; - default: - return -EINVAL; - } - - snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl); - snd_soc_update_bits(codec, bclk_reg, - WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR, - bclk); - snd_soc_update_bits(codec, lrclk_tx_reg, - WM8915_AIF1TX_LRCLK_INV | - WM8915_AIF1TX_LRCLK_MSTR, - lrclk_tx); - snd_soc_update_bits(codec, lrclk_rx_reg, - WM8915_AIF1RX_LRCLK_INV | - WM8915_AIF1RX_LRCLK_MSTR, - lrclk_rx); - - return 0; -} - -static const int dsp_divs[] = { - 48000, 32000, 16000, 8000 -}; - -static int wm8915_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) -{ - struct snd_soc_codec *codec = dai->codec; - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int bits, i, bclk_rate; - int aifdata = 0; - int lrclk = 0; - int dsp = 0; - int aifdata_reg, lrclk_reg, dsp_shift; - - switch (dai->id) { - case 0: - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || - (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) { - aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION; - lrclk_reg = WM8915_AIF1_RX_LRCLK_1; - } else { - aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1; - lrclk_reg = WM8915_AIF1_TX_LRCLK_1; - } - dsp_shift = 0; - break; - case 1: - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || - (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) { - aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION; - lrclk_reg = WM8915_AIF2_RX_LRCLK_1; - } else { - aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1; - lrclk_reg = WM8915_AIF2_TX_LRCLK_1; - } - dsp_shift = WM8915_DSP2_DIV_SHIFT; - break; - default: - BUG(); - return -EINVAL; - } - - bclk_rate = snd_soc_params_to_bclk(params); - if (bclk_rate < 0) { - dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); - return bclk_rate; - } - - wm8915->bclk_rate[dai->id] = bclk_rate; - wm8915->rx_rate[dai->id] = params_rate(params); - - /* Needs looking at for TDM */ - bits = snd_pcm_format_width(params_format(params)); - if (bits < 0) - return bits; - aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits; - - for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { - if (dsp_divs[i] == params_rate(params)) - break; - } - if (i == ARRAY_SIZE(dsp_divs)) { - dev_err(codec->dev, "Unsupported sample rate %dHz\n", - params_rate(params)); - return -EINVAL; - } - dsp |= i << dsp_shift; - - wm8915_update_bclk(codec); - - lrclk = bclk_rate / params_rate(params); - dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", - lrclk, bclk_rate / lrclk); - - snd_soc_update_bits(codec, aifdata_reg, - WM8915_AIF1TX_WL_MASK | - WM8915_AIF1TX_SLOT_LEN_MASK, - aifdata); - snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK, - lrclk); - snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2, - WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp); - - return 0; -} - -static int wm8915_set_sysclk(struct snd_soc_dai *dai, - int clk_id, unsigned int freq, int dir) -{ - struct snd_soc_codec *codec = dai->codec; - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int lfclk = 0; - int ratediv = 0; - int src; - int old; - - if (freq == wm8915->sysclk && clk_id == wm8915->sysclk_src) - return 0; - - /* Disable SYSCLK while we reconfigure */ - old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1) & WM8915_SYSCLK_ENA; - snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1, - WM8915_SYSCLK_ENA, 0); - - switch (clk_id) { - case WM8915_SYSCLK_MCLK1: - wm8915->sysclk = freq; - src = 0; - break; - case WM8915_SYSCLK_MCLK2: - wm8915->sysclk = freq; - src = 1; - break; - case WM8915_SYSCLK_FLL: - wm8915->sysclk = freq; - src = 2; - break; - default: - dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); - return -EINVAL; - } - - switch (wm8915->sysclk) { - case 6144000: - snd_soc_update_bits(codec, WM8915_AIF_RATE, - WM8915_SYSCLK_RATE, 0); - break; - case 24576000: - ratediv = WM8915_SYSCLK_DIV; - case 12288000: - snd_soc_update_bits(codec, WM8915_AIF_RATE, - WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE); - break; - case 32000: - case 32768: - lfclk = WM8915_LFCLK_ENA; - break; - default: - dev_warn(codec->dev, "Unsupported clock rate %dHz\n", - wm8915->sysclk); - return -EINVAL; - } - - wm8915_update_bclk(codec); - - snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1, - WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK, - src << WM8915_SYSCLK_SRC_SHIFT | ratediv); - snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk); - snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1, - WM8915_SYSCLK_ENA, old); - - wm8915->sysclk_src = clk_id; - - return 0; -} - -struct _fll_div { - u16 fll_fratio; - u16 fll_outdiv; - u16 fll_refclk_div; - u16 fll_loop_gain; - u16 fll_ref_freq; - u16 n; - u16 theta; - u16 lambda; -}; - -static struct { - unsigned int min; - unsigned int max; - u16 fll_fratio; - int ratio; -} fll_fratios[] = { - { 0, 64000, 4, 16 }, - { 64000, 128000, 3, 8 }, - { 128000, 256000, 2, 4 }, - { 256000, 1000000, 1, 2 }, - { 1000000, 13500000, 0, 1 }, -}; - -static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, - unsigned int Fout) -{ - unsigned int target; - unsigned int div; - unsigned int fratio, gcd_fll; - int i; - - /* Fref must be <=13.5MHz */ - div = 1; - fll_div->fll_refclk_div = 0; - while ((Fref / div) > 13500000) { - div *= 2; - fll_div->fll_refclk_div++; - - if (div > 8) { - pr_err("Can't scale %dMHz input down to <=13.5MHz\n", - Fref); - return -EINVAL; - } - } - - pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); - - /* Apply the division for our remaining calculations */ - Fref /= div; - - if (Fref >= 3000000) - fll_div->fll_loop_gain = 5; - else - fll_div->fll_loop_gain = 0; - - if (Fref >= 48000) - fll_div->fll_ref_freq = 0; - else - fll_div->fll_ref_freq = 1; - - /* Fvco should be 90-100MHz; don't check the upper bound */ - div = 2; - while (Fout * div < 90000000) { - div++; - if (div > 64) { - pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", - Fout); - return -EINVAL; - } - } - target = Fout * div; - fll_div->fll_outdiv = div - 1; - - pr_debug("FLL Fvco=%dHz\n", target); - - /* Find an appropraite FLL_FRATIO and factor it out of the target */ - for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { - if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { - fll_div->fll_fratio = fll_fratios[i].fll_fratio; - fratio = fll_fratios[i].ratio; - break; - } - } - if (i == ARRAY_SIZE(fll_fratios)) { - pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); - return -EINVAL; - } - - fll_div->n = target / (fratio * Fref); - - if (target % Fref == 0) { - fll_div->theta = 0; - fll_div->lambda = 0; - } else { - gcd_fll = gcd(target, fratio * Fref); - - fll_div->theta = (target - (fll_div->n * fratio * Fref)) - / gcd_fll; - fll_div->lambda = (fratio * Fref) / gcd_fll; - } - - pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", - fll_div->n, fll_div->theta, fll_div->lambda); - pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", - fll_div->fll_fratio, fll_div->fll_outdiv, - fll_div->fll_refclk_div); - - return 0; -} - -static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source, - unsigned int Fref, unsigned int Fout) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - struct i2c_client *i2c = to_i2c_client(codec->dev); - struct _fll_div fll_div; - unsigned long timeout; - int ret, reg; - - /* Any change? */ - if (source == wm8915->fll_src && Fref == wm8915->fll_fref && - Fout == wm8915->fll_fout) - return 0; - - if (Fout == 0) { - dev_dbg(codec->dev, "FLL disabled\n"); - - wm8915->fll_fref = 0; - wm8915->fll_fout = 0; - - snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1, - WM8915_FLL_ENA, 0); - - return 0; - } - - ret = fll_factors(&fll_div, Fref, Fout); - if (ret != 0) - return ret; - - switch (source) { - case WM8915_FLL_MCLK1: - reg = 0; - break; - case WM8915_FLL_MCLK2: - reg = 1; - break; - case WM8915_FLL_DACLRCLK1: - reg = 2; - break; - case WM8915_FLL_BCLK1: - reg = 3; - break; - default: - dev_err(codec->dev, "Unknown FLL source %d\n", ret); - return -EINVAL; - } - - reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT; - reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT; - - snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5, - WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ | - WM8915_FLL_REFCLK_SRC_MASK, reg); - - reg = 0; - if (fll_div.theta || fll_div.lambda) - reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT); - else - reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT; - snd_soc_write(codec, WM8915_FLL_EFS_2, reg); - - snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2, - WM8915_FLL_OUTDIV_MASK | - WM8915_FLL_FRATIO_MASK, - (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) | - (fll_div.fll_fratio)); - - snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta); - - snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4, - WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK, - (fll_div.n << WM8915_FLL_N_SHIFT) | - fll_div.fll_loop_gain); - - snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda); - - snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1, - WM8915_FLL_ENA, WM8915_FLL_ENA); - - /* The FLL supports live reconfiguration - kick that in case we were - * already enabled. - */ - snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK); - - /* Wait for the FLL to lock, using the interrupt if possible */ - if (Fref > 1000000) - timeout = usecs_to_jiffies(300); - else - timeout = msecs_to_jiffies(2); - - /* Allow substantially longer if we've actually got the IRQ */ - if (i2c->irq) - timeout *= 1000; - - ret = wait_for_completion_timeout(&wm8915->fll_lock, timeout); - - if (ret == 0 && i2c->irq) { - dev_err(codec->dev, "Timed out waiting for FLL\n"); - ret = -ETIMEDOUT; - } else { - ret = 0; - } - - dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); - - wm8915->fll_fref = Fref; - wm8915->fll_fout = Fout; - wm8915->fll_src = source; - - return ret; -} - -#ifdef CONFIG_GPIOLIB -static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip) -{ - return container_of(chip, struct wm8915_priv, gpio_chip); -} - -static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); - struct snd_soc_codec *codec = wm8915->codec; - - snd_soc_update_bits(codec, WM8915_GPIO_1 + offset, - WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT); -} - -static int wm8915_gpio_direction_out(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); - struct snd_soc_codec *codec = wm8915->codec; - int val; - - val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT); - - return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset, - WM8915_GP1_FN_MASK | WM8915_GP1_DIR | - WM8915_GP1_LVL, val); -} - -static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); - struct snd_soc_codec *codec = wm8915->codec; - int ret; - - ret = snd_soc_read(codec, WM8915_GPIO_1 + offset); - if (ret < 0) - return ret; - - return (ret & WM8915_GP1_LVL) != 0; -} - -static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset) -{ - struct wm8915_priv *wm8915 = gpio_to_wm8915(chip); - struct snd_soc_codec *codec = wm8915->codec; - - return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset, - WM8915_GP1_FN_MASK | WM8915_GP1_DIR, - (1 << WM8915_GP1_FN_SHIFT) | - (1 << WM8915_GP1_DIR_SHIFT)); -} - -static struct gpio_chip wm8915_template_chip = { - .label = "wm8915", - .owner = THIS_MODULE, - .direction_output = wm8915_gpio_direction_out, - .set = wm8915_gpio_set, - .direction_input = wm8915_gpio_direction_in, - .get = wm8915_gpio_get, - .can_sleep = 1, -}; - -static void wm8915_init_gpio(struct snd_soc_codec *codec) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int ret; - - wm8915->gpio_chip = wm8915_template_chip; - wm8915->gpio_chip.ngpio = 5; - wm8915->gpio_chip.dev = codec->dev; - - if (wm8915->pdata.gpio_base) - wm8915->gpio_chip.base = wm8915->pdata.gpio_base; - else - wm8915->gpio_chip.base = -1; - - ret = gpiochip_add(&wm8915->gpio_chip); - if (ret != 0) - dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); -} - -static void wm8915_free_gpio(struct snd_soc_codec *codec) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int ret; - - ret = gpiochip_remove(&wm8915->gpio_chip); - if (ret != 0) - dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); -} -#else -static void wm8915_init_gpio(struct snd_soc_codec *codec) -{ -} - -static void wm8915_free_gpio(struct snd_soc_codec *codec) -{ -} -#endif - -/** - * wm8915_detect - Enable default WM8915 jack detection - * - * The WM8915 has advanced accessory detection support for headsets. - * This function provides a default implementation which integrates - * the majority of this functionality with minimal user configuration. - * - * This will detect headset, headphone and short circuit button and - * will also detect inverted microphone ground connections and update - * the polarity of the connections. - */ -int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, - wm8915_polarity_fn polarity_cb) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - - wm8915->jack = jack; - wm8915->detecting = true; - wm8915->polarity_cb = polarity_cb; - - if (wm8915->polarity_cb) - wm8915->polarity_cb(codec, 0); - - /* Clear discarge to avoid noise during detection */ - snd_soc_update_bits(codec, WM8915_MICBIAS_1, - WM8915_MICB1_DISCH, 0); - snd_soc_update_bits(codec, WM8915_MICBIAS_2, - WM8915_MICB2_DISCH, 0); - - /* LDO2 powers the microphones, SYSCLK clocks detection */ - snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); - snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); - - /* We start off just enabling microphone detection - even a - * plain headphone will trigger detection. - */ - snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, - WM8915_MICD_ENA, WM8915_MICD_ENA); - - /* Slowest detection rate, gives debounce for initial detection */ - snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, - WM8915_MICD_RATE_MASK, - WM8915_MICD_RATE_MASK); - - /* Enable interrupts and we're off */ - snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK, - WM8915_IM_MICD_EINT, 0); - - return 0; -} -EXPORT_SYMBOL_GPL(wm8915_detect); - -static void wm8915_micd(struct snd_soc_codec *codec) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int val, reg; - - val = snd_soc_read(codec, WM8915_MIC_DETECT_3); - - dev_dbg(codec->dev, "Microphone event: %x\n", val); - - if (!(val & WM8915_MICD_VALID)) { - dev_warn(codec->dev, "Microphone detection state invalid\n"); - return; - } - - /* No accessory, reset everything and report removal */ - if (!(val & WM8915_MICD_STS)) { - dev_dbg(codec->dev, "Jack removal detected\n"); - wm8915->jack_mic = false; - wm8915->detecting = true; - snd_soc_jack_report(wm8915->jack, 0, - SND_JACK_HEADSET | SND_JACK_BTN_0); - snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, - WM8915_MICD_RATE_MASK, - WM8915_MICD_RATE_MASK); - return; - } - - /* If the measurement is very high we've got a microphone but - * do a little debounce to account for mechanical issues. - */ - if (val & 0x400) { - dev_dbg(codec->dev, "Microphone detected\n"); - snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET, - SND_JACK_HEADSET | SND_JACK_BTN_0); - wm8915->jack_mic = true; - wm8915->detecting = false; - - /* Increase poll rate to give better responsiveness - * for buttons */ - snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, - WM8915_MICD_RATE_MASK, - 5 << WM8915_MICD_RATE_SHIFT); - } - - /* If we detected a lower impedence during initial startup - * then we probably have the wrong polarity, flip it. Don't - * do this for the lowest impedences to speed up detection of - * plain headphones. - */ - if (wm8915->detecting && (val & 0x3f0)) { - reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2); - reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC | - WM8915_MICD_BIAS_SRC; - snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2, - WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC | - WM8915_MICD_BIAS_SRC, reg); - - if (wm8915->polarity_cb) - wm8915->polarity_cb(codec, - (reg & WM8915_MICD_SRC) != 0); - - dev_dbg(codec->dev, "Set microphone polarity to %d\n", - (reg & WM8915_MICD_SRC) != 0); - - return; - } - - /* Don't distinguish between buttons, just report any low - * impedence as BTN_0. - */ - if (val & 0x3fc) { - if (wm8915->jack_mic) { - dev_dbg(codec->dev, "Mic button detected\n"); - snd_soc_jack_report(wm8915->jack, - SND_JACK_HEADSET | SND_JACK_BTN_0, - SND_JACK_HEADSET | SND_JACK_BTN_0); - } else { - dev_dbg(codec->dev, "Headphone detected\n"); - snd_soc_jack_report(wm8915->jack, - SND_JACK_HEADPHONE, - SND_JACK_HEADSET | - SND_JACK_BTN_0); - - /* Increase the detection rate a bit for - * responsiveness. - */ - snd_soc_update_bits(codec, WM8915_MIC_DETECT_1, - WM8915_MICD_RATE_MASK, - 7 << WM8915_MICD_RATE_SHIFT); - - wm8915->detecting = false; - } - } -} - -static irqreturn_t wm8915_irq(int irq, void *data) -{ - struct snd_soc_codec *codec = data; - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - int irq_val; - - irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2); - if (irq_val < 0) { - dev_err(codec->dev, "Failed to read IRQ status: %d\n", - irq_val); - return IRQ_NONE; - } - irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK); - - if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) { - dev_dbg(codec->dev, "DC servo IRQ\n"); - complete(&wm8915->dcs_done); - } - - if (irq_val & WM8915_FIFOS_ERR_EINT) - dev_err(codec->dev, "Digital core FIFO error\n"); - - if (irq_val & WM8915_FLL_LOCK_EINT) { - dev_dbg(codec->dev, "FLL locked\n"); - complete(&wm8915->fll_lock); - } - - if (irq_val & WM8915_MICD_EINT) - wm8915_micd(codec); - - if (irq_val) { - snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val); - - return IRQ_HANDLED; - } else { - return IRQ_NONE; - } -} - -static irqreturn_t wm8915_edge_irq(int irq, void *data) -{ - irqreturn_t ret = IRQ_NONE; - irqreturn_t val; - - do { - val = wm8915_irq(irq, data); - if (val != IRQ_NONE) - ret = val; - } while (val != IRQ_NONE); - - return ret; -} - -static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - struct wm8915_pdata *pdata = &wm8915->pdata; - - struct snd_kcontrol_new controls[] = { - SOC_ENUM_EXT("DSP1 EQ Mode", - wm8915->retune_mobile_enum, - wm8915_get_retune_mobile_enum, - wm8915_put_retune_mobile_enum), - SOC_ENUM_EXT("DSP2 EQ Mode", - wm8915->retune_mobile_enum, - wm8915_get_retune_mobile_enum, - wm8915_put_retune_mobile_enum), - }; - int ret, i, j; - const char **t; - - /* We need an array of texts for the enum API but the number - * of texts is likely to be less than the number of - * configurations due to the sample rate dependency of the - * configurations. */ - wm8915->num_retune_mobile_texts = 0; - wm8915->retune_mobile_texts = NULL; - for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { - for (j = 0; j < wm8915->num_retune_mobile_texts; j++) { - if (strcmp(pdata->retune_mobile_cfgs[i].name, - wm8915->retune_mobile_texts[j]) == 0) - break; - } - - if (j != wm8915->num_retune_mobile_texts) - continue; - - /* Expand the array... */ - t = krealloc(wm8915->retune_mobile_texts, - sizeof(char *) * - (wm8915->num_retune_mobile_texts + 1), - GFP_KERNEL); - if (t == NULL) - continue; - - /* ...store the new entry... */ - t[wm8915->num_retune_mobile_texts] = - pdata->retune_mobile_cfgs[i].name; - - /* ...and remember the new version. */ - wm8915->num_retune_mobile_texts++; - wm8915->retune_mobile_texts = t; - } - - dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", - wm8915->num_retune_mobile_texts); - - wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts; - wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts; - - ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); - if (ret != 0) - dev_err(codec->dev, - "Failed to add ReTune Mobile controls: %d\n", ret); -} - -static int wm8915_probe(struct snd_soc_codec *codec) -{ - int ret; - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - struct i2c_client *i2c = to_i2c_client(codec->dev); - struct snd_soc_dapm_context *dapm = &codec->dapm; - int i, irq_flags; - - wm8915->codec = codec; - - init_completion(&wm8915->dcs_done); - init_completion(&wm8915->fll_lock); - - dapm->idle_bias_off = true; - dapm->bias_level = SND_SOC_BIAS_OFF; - - ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); - if (ret != 0) { - dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); - goto err; - } - - for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) - wm8915->supplies[i].supply = wm8915_supply_names[i]; - - ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies), - wm8915->supplies); - if (ret != 0) { - dev_err(codec->dev, "Failed to request supplies: %d\n", ret); - goto err; - } - - wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0; - wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1; - wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2; - wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3; - - /* This should really be moved into the regulator core */ - for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) { - ret = regulator_register_notifier(wm8915->supplies[i].consumer, - &wm8915->disable_nb[i]); - if (ret != 0) { - dev_err(codec->dev, - "Failed to register regulator notifier: %d\n", - ret); - } - } - - ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies), - wm8915->supplies); - if (ret != 0) { - dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); - goto err_get; - } - - if (wm8915->pdata.ldo_ena >= 0) { - gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1); - msleep(5); - } - - ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET); - if (ret < 0) { - dev_err(codec->dev, "Failed to read ID register: %d\n", ret); - goto err_enable; - } - if (ret != 0x8915) { - dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret); - ret = -EINVAL; - goto err_enable; - } - - ret = snd_soc_read(codec, WM8915_CHIP_REVISION); - if (ret < 0) { - dev_err(codec->dev, "Failed to read device revision: %d\n", - ret); - goto err_enable; - } - - dev_info(codec->dev, "revision %c\n", - (ret & WM8915_CHIP_REV_MASK) + 'A'); - - if (wm8915->pdata.ldo_ena >= 0) { - gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0); - } else { - ret = wm8915_reset(codec); - if (ret < 0) { - dev_err(codec->dev, "Failed to issue reset\n"); - goto err_enable; - } - } - - codec->cache_only = true; - - /* Apply platform data settings */ - snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL, - WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK, - wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT | - wm8915->pdata.inr_mode); - - for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) { - if (!wm8915->pdata.gpio_default[i]) - continue; - - snd_soc_write(codec, WM8915_GPIO_1 + i, - wm8915->pdata.gpio_default[i] & 0xffff); - } - - if (wm8915->pdata.spkmute_seq) - snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE, - WM8915_SPK_MUTE_ENDIAN | - WM8915_SPK_MUTE_SEQ1_MASK, - wm8915->pdata.spkmute_seq); - - snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2, - WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC | - WM8915_MICD_SRC, wm8915->pdata.micdet_def); - - /* Latch volume update bits */ - snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME, - WM8915_IN1_VU, WM8915_IN1_VU); - snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME, - WM8915_IN1_VU, WM8915_IN1_VU); - - snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME, - WM8915_DAC1_VU, WM8915_DAC1_VU); - snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME, - WM8915_DAC1_VU, WM8915_DAC1_VU); - snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME, - WM8915_DAC2_VU, WM8915_DAC2_VU); - snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME, - WM8915_DAC2_VU, WM8915_DAC2_VU); - - snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME, - WM8915_DAC1_VU, WM8915_DAC1_VU); - snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME, - WM8915_DAC1_VU, WM8915_DAC1_VU); - snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME, - WM8915_DAC2_VU, WM8915_DAC2_VU); - snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME, - WM8915_DAC2_VU, WM8915_DAC2_VU); - - snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME, - WM8915_DSP1TX_VU, WM8915_DSP1TX_VU); - snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME, - WM8915_DSP1TX_VU, WM8915_DSP1TX_VU); - snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME, - WM8915_DSP2TX_VU, WM8915_DSP2TX_VU); - snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME, - WM8915_DSP2TX_VU, WM8915_DSP2TX_VU); - - snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME, - WM8915_DSP1RX_VU, WM8915_DSP1RX_VU); - snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME, - WM8915_DSP1RX_VU, WM8915_DSP1RX_VU); - snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME, - WM8915_DSP2RX_VU, WM8915_DSP2RX_VU); - snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME, - WM8915_DSP2RX_VU, WM8915_DSP2RX_VU); - - /* No support currently for the underclocked TDM modes and - * pick a default TDM layout with each channel pair working with - * slots 0 and 1. */ - snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION, - WM8915_AIF1RX_CHAN0_SLOTS_MASK | - WM8915_AIF1RX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION, - WM8915_AIF1RX_CHAN1_SLOTS_MASK | - WM8915_AIF1RX_CHAN1_START_SLOT_MASK, - 1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1); - snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION, - WM8915_AIF1RX_CHAN2_SLOTS_MASK | - WM8915_AIF1RX_CHAN2_START_SLOT_MASK, - 1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION, - WM8915_AIF1RX_CHAN3_SLOTS_MASK | - WM8915_AIF1RX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1); - snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION, - WM8915_AIF1RX_CHAN4_SLOTS_MASK | - WM8915_AIF1RX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION, - WM8915_AIF1RX_CHAN5_SLOTS_MASK | - WM8915_AIF1RX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1); - - snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION, - WM8915_AIF2RX_CHAN0_SLOTS_MASK | - WM8915_AIF2RX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION, - WM8915_AIF2RX_CHAN1_SLOTS_MASK | - WM8915_AIF2RX_CHAN1_START_SLOT_MASK, - 1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1); - - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION, - WM8915_AIF1TX_CHAN0_SLOTS_MASK | - WM8915_AIF1TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION, - WM8915_AIF1TX_CHAN1_SLOTS_MASK | - WM8915_AIF1TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1); - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION, - WM8915_AIF1TX_CHAN2_SLOTS_MASK | - WM8915_AIF1TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION, - WM8915_AIF1TX_CHAN3_SLOTS_MASK | - WM8915_AIF1TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1); - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION, - WM8915_AIF1TX_CHAN4_SLOTS_MASK | - WM8915_AIF1TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION, - WM8915_AIF1TX_CHAN5_SLOTS_MASK | - WM8915_AIF1TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1); - - snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION, - WM8915_AIF2TX_CHAN0_SLOTS_MASK | - WM8915_AIF2TX_CHAN0_START_SLOT_MASK, - 1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0); - snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION, - WM8915_AIF2TX_CHAN1_SLOTS_MASK | - WM8915_AIF2TX_CHAN1_START_SLOT_MASK, - 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1); - - if (wm8915->pdata.num_retune_mobile_cfgs) - wm8915_retune_mobile_pdata(codec); - else - snd_soc_add_controls(codec, wm8915_eq_controls, - ARRAY_SIZE(wm8915_eq_controls)); - - /* If the TX LRCLK pins are not in LRCLK mode configure the - * AIFs to source their clocks from the RX LRCLKs. - */ - if ((snd_soc_read(codec, WM8915_GPIO_1))) - snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2, - WM8915_AIF1TX_LRCLK_MODE, - WM8915_AIF1TX_LRCLK_MODE); - - if ((snd_soc_read(codec, WM8915_GPIO_2))) - snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2, - WM8915_AIF2TX_LRCLK_MODE, - WM8915_AIF2TX_LRCLK_MODE); - - regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); - - wm8915_init_gpio(codec); - - if (i2c->irq) { - if (wm8915->pdata.irq_flags) - irq_flags = wm8915->pdata.irq_flags; - else - irq_flags = IRQF_TRIGGER_LOW; - - irq_flags |= IRQF_ONESHOT; - - if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) - ret = request_threaded_irq(i2c->irq, NULL, - wm8915_edge_irq, - irq_flags, "wm8915", codec); - else - ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq, - irq_flags, "wm8915", codec); - - if (ret == 0) { - /* Unmask the interrupt */ - snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL, - WM8915_IM_IRQ, 0); - - /* Enable error reporting and DC servo status */ - snd_soc_update_bits(codec, - WM8915_INTERRUPT_STATUS_2_MASK, - WM8915_IM_DCS_DONE_23_EINT | - WM8915_IM_DCS_DONE_01_EINT | - WM8915_IM_FLL_LOCK_EINT | - WM8915_IM_FIFOS_ERR_EINT, - 0); - } else { - dev_err(codec->dev, "Failed to request IRQ: %d\n", - ret); - } - } - - return 0; - -err_enable: - if (wm8915->pdata.ldo_ena >= 0) - gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0); - - regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); -err_get: - regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); -err: - return ret; -} - -static int wm8915_remove(struct snd_soc_codec *codec) -{ - struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec); - struct i2c_client *i2c = to_i2c_client(codec->dev); - int i; - - snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL, - WM8915_IM_IRQ, WM8915_IM_IRQ); - - if (i2c->irq) - free_irq(i2c->irq, codec); - - wm8915_free_gpio(codec); - - for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) - regulator_unregister_notifier(wm8915->supplies[i].consumer, - &wm8915->disable_nb[i]); - regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies); - - return 0; -} - -static struct snd_soc_codec_driver soc_codec_dev_wm8915 = { - .probe = wm8915_probe, - .remove = wm8915_remove, - .set_bias_level = wm8915_set_bias_level, - .seq_notifier = wm8915_seq_notifier, - .reg_cache_size = WM8915_MAX_REGISTER + 1, - .reg_word_size = sizeof(u16), - .reg_cache_default = wm8915_reg, - .volatile_register = wm8915_volatile_register, - .readable_register = wm8915_readable_register, - .compress_type = SND_SOC_RBTREE_COMPRESSION, - .controls = wm8915_snd_controls, - .num_controls = ARRAY_SIZE(wm8915_snd_controls), - .dapm_widgets = wm8915_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets), - .dapm_routes = wm8915_dapm_routes, - .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes), - .set_pll = wm8915_set_fll, -}; - -#define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) -#define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ - SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ - SNDRV_PCM_FMTBIT_S32_LE) - -static struct snd_soc_dai_ops wm8915_dai_ops = { - .set_fmt = wm8915_set_fmt, - .hw_params = wm8915_hw_params, - .set_sysclk = wm8915_set_sysclk, -}; - -static struct snd_soc_dai_driver wm8915_dai[] = { - { - .name = "wm8915-aif1", - .playback = { - .stream_name = "AIF1 Playback", - .channels_min = 1, - .channels_max = 6, - .rates = WM8915_RATES, - .formats = WM8915_FORMATS, - }, - .capture = { - .stream_name = "AIF1 Capture", - .channels_min = 1, - .channels_max = 6, - .rates = WM8915_RATES, - .formats = WM8915_FORMATS, - }, - .ops = &wm8915_dai_ops, - }, - { - .name = "wm8915-aif2", - .playback = { - .stream_name = "AIF2 Playback", - .channels_min = 1, - .channels_max = 2, - .rates = WM8915_RATES, - .formats = WM8915_FORMATS, - }, - .capture = { - .stream_name = "AIF2 Capture", - .channels_min = 1, - .channels_max = 2, - .rates = WM8915_RATES, - .formats = WM8915_FORMATS, - }, - .ops = &wm8915_dai_ops, - }, -}; - -static __devinit int wm8915_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) -{ - struct wm8915_priv *wm8915; - int ret; - - wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL); - if (wm8915 == NULL) - return -ENOMEM; - - i2c_set_clientdata(i2c, wm8915); - - if (dev_get_platdata(&i2c->dev)) - memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev), - sizeof(wm8915->pdata)); - - if (wm8915->pdata.ldo_ena > 0) { - ret = gpio_request_one(wm8915->pdata.ldo_ena, - GPIOF_OUT_INIT_LOW, "WM8915 ENA"); - if (ret < 0) { - dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", - wm8915->pdata.ldo_ena, ret); - goto err; - } - } - - ret = snd_soc_register_codec(&i2c->dev, - &soc_codec_dev_wm8915, wm8915_dai, - ARRAY_SIZE(wm8915_dai)); - if (ret < 0) - goto err_gpio; - - return ret; - -err_gpio: - if (wm8915->pdata.ldo_ena > 0) - gpio_free(wm8915->pdata.ldo_ena); -err: - kfree(wm8915); - - return ret; -} - -static __devexit int wm8915_i2c_remove(struct i2c_client *client) -{ - struct wm8915_priv *wm8915 = i2c_get_clientdata(client); - - snd_soc_unregister_codec(&client->dev); - if (wm8915->pdata.ldo_ena > 0) - gpio_free(wm8915->pdata.ldo_ena); - kfree(i2c_get_clientdata(client)); - return 0; -} - -static const struct i2c_device_id wm8915_i2c_id[] = { - { "wm8915", 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id); - -static struct i2c_driver wm8915_i2c_driver = { - .driver = { - .name = "wm8915", - .owner = THIS_MODULE, - }, - .probe = wm8915_i2c_probe, - .remove = __devexit_p(wm8915_i2c_remove), - .id_table = wm8915_i2c_id, -}; - -static int __init wm8915_modinit(void) -{ - int ret; - - ret = i2c_add_driver(&wm8915_i2c_driver); - if (ret != 0) { - printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n", - ret); - } - - return ret; -} -module_init(wm8915_modinit); - -static void __exit wm8915_exit(void) -{ - i2c_del_driver(&wm8915_i2c_driver); -} -module_exit(wm8915_exit); - -MODULE_DESCRIPTION("ASoC WM8915 driver"); -MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); -MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8915.h b/sound/soc/codecs/wm8915.h deleted file mode 100644 index 200ffd7bf953..000000000000 --- a/sound/soc/codecs/wm8915.h +++ /dev/null @@ -1,3717 +0,0 @@ -/* - * wm8915.h - WM8915 audio codec interface - * - * Copyright 2011 Wolfson Microelectronics PLC. - * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef _WM8915_H -#define _WM8915_H - -#define WM8915_SYSCLK_MCLK1 1 -#define WM8915_SYSCLK_MCLK2 2 -#define WM8915_SYSCLK_FLL 3 - -#define WM8915_FLL_MCLK1 1 -#define WM8915_FLL_MCLK2 2 -#define WM8915_FLL_DACLRCLK1 3 -#define WM8915_FLL_BCLK1 4 - -typedef void (*wm8915_polarity_fn)(struct snd_soc_codec *codec, int polarity); - -int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, - wm8915_polarity_fn polarity_cb); - -/* - * Register values. - */ -#define WM8915_SOFTWARE_RESET 0x00 -#define WM8915_POWER_MANAGEMENT_1 0x01 -#define WM8915_POWER_MANAGEMENT_2 0x02 -#define WM8915_POWER_MANAGEMENT_3 0x03 -#define WM8915_POWER_MANAGEMENT_4 0x04 -#define WM8915_POWER_MANAGEMENT_5 0x05 -#define WM8915_POWER_MANAGEMENT_6 0x06 -#define WM8915_POWER_MANAGEMENT_7 0x07 -#define WM8915_POWER_MANAGEMENT_8 0x08 -#define WM8915_LEFT_LINE_INPUT_VOLUME 0x10 -#define WM8915_RIGHT_LINE_INPUT_VOLUME 0x11 -#define WM8915_LINE_INPUT_CONTROL 0x12 -#define WM8915_DAC1_HPOUT1_VOLUME 0x15 -#define WM8915_DAC2_HPOUT2_VOLUME 0x16 -#define WM8915_DAC1_LEFT_VOLUME 0x18 -#define WM8915_DAC1_RIGHT_VOLUME 0x19 -#define WM8915_DAC2_LEFT_VOLUME 0x1A -#define WM8915_DAC2_RIGHT_VOLUME 0x1B -#define WM8915_OUTPUT1_LEFT_VOLUME 0x1C -#define WM8915_OUTPUT1_RIGHT_VOLUME 0x1D -#define WM8915_OUTPUT2_LEFT_VOLUME 0x1E -#define WM8915_OUTPUT2_RIGHT_VOLUME 0x1F -#define WM8915_MICBIAS_1 0x20 -#define WM8915_MICBIAS_2 0x21 -#define WM8915_LDO_1 0x28 -#define WM8915_LDO_2 0x29 -#define WM8915_ACCESSORY_DETECT_MODE_1 0x30 -#define WM8915_ACCESSORY_DETECT_MODE_2 0x31 -#define WM8915_HEADPHONE_DETECT_1 0x34 -#define WM8915_HEADPHONE_DETECT_2 0x35 -#define WM8915_MIC_DETECT_1 0x38 -#define WM8915_MIC_DETECT_2 0x39 -#define WM8915_MIC_DETECT_3 0x3A -#define WM8915_CHARGE_PUMP_1 0x40 -#define WM8915_CHARGE_PUMP_2 0x41 -#define WM8915_DC_SERVO_1 0x50 -#define WM8915_DC_SERVO_2 0x51 -#define WM8915_DC_SERVO_3 0x52 -#define WM8915_DC_SERVO_5 0x54 -#define WM8915_DC_SERVO_6 0x55 -#define WM8915_DC_SERVO_7 0x56 -#define WM8915_DC_SERVO_READBACK_0 0x57 -#define WM8915_ANALOGUE_HP_1 0x60 -#define WM8915_ANALOGUE_HP_2 0x61 -#define WM8915_CHIP_REVISION 0x100 -#define WM8915_CONTROL_INTERFACE_1 0x101 -#define WM8915_WRITE_SEQUENCER_CTRL_1 0x110 -#define WM8915_WRITE_SEQUENCER_CTRL_2 0x111 -#define WM8915_AIF_CLOCKING_1 0x200 -#define WM8915_AIF_CLOCKING_2 0x201 -#define WM8915_CLOCKING_1 0x208 -#define WM8915_CLOCKING_2 0x209 -#define WM8915_AIF_RATE 0x210 -#define WM8915_FLL_CONTROL_1 0x220 -#define WM8915_FLL_CONTROL_2 0x221 -#define WM8915_FLL_CONTROL_3 0x222 -#define WM8915_FLL_CONTROL_4 0x223 -#define WM8915_FLL_CONTROL_5 0x224 -#define WM8915_FLL_CONTROL_6 0x225 -#define WM8915_FLL_EFS_1 0x226 -#define WM8915_FLL_EFS_2 0x227 -#define WM8915_AIF1_CONTROL 0x300 -#define WM8915_AIF1_BCLK 0x301 -#define WM8915_AIF1_TX_LRCLK_1 0x302 -#define WM8915_AIF1_TX_LRCLK_2 0x303 -#define WM8915_AIF1_RX_LRCLK_1 0x304 -#define WM8915_AIF1_RX_LRCLK_2 0x305 -#define WM8915_AIF1TX_DATA_CONFIGURATION_1 0x306 -#define WM8915_AIF1TX_DATA_CONFIGURATION_2 0x307 -#define WM8915_AIF1RX_DATA_CONFIGURATION 0x308 -#define WM8915_AIF1TX_CHANNEL_0_CONFIGURATION 0x309 -#define WM8915_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A -#define WM8915_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B -#define WM8915_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C -#define WM8915_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D -#define WM8915_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E -#define WM8915_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F -#define WM8915_AIF1RX_CHANNEL_1_CONFIGURATION 0x310 -#define WM8915_AIF1RX_CHANNEL_2_CONFIGURATION 0x311 -#define WM8915_AIF1RX_CHANNEL_3_CONFIGURATION 0x312 -#define WM8915_AIF1RX_CHANNEL_4_CONFIGURATION 0x313 -#define WM8915_AIF1RX_CHANNEL_5_CONFIGURATION 0x314 -#define WM8915_AIF1RX_MONO_CONFIGURATION 0x315 -#define WM8915_AIF1TX_TEST 0x31A -#define WM8915_AIF2_CONTROL 0x320 -#define WM8915_AIF2_BCLK 0x321 -#define WM8915_AIF2_TX_LRCLK_1 0x322 -#define WM8915_AIF2_TX_LRCLK_2 0x323 -#define WM8915_AIF2_RX_LRCLK_1 0x324 -#define WM8915_AIF2_RX_LRCLK_2 0x325 -#define WM8915_AIF2TX_DATA_CONFIGURATION_1 0x326 -#define WM8915_AIF2TX_DATA_CONFIGURATION_2 0x327 -#define WM8915_AIF2RX_DATA_CONFIGURATION 0x328 -#define WM8915_AIF2TX_CHANNEL_0_CONFIGURATION 0x329 -#define WM8915_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A -#define WM8915_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B -#define WM8915_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C -#define WM8915_AIF2RX_MONO_CONFIGURATION 0x32D -#define WM8915_AIF2TX_TEST 0x32F -#define WM8915_DSP1_TX_LEFT_VOLUME 0x400 -#define WM8915_DSP1_TX_RIGHT_VOLUME 0x401 -#define WM8915_DSP1_RX_LEFT_VOLUME 0x402 -#define WM8915_DSP1_RX_RIGHT_VOLUME 0x403 -#define WM8915_DSP1_TX_FILTERS 0x410 -#define WM8915_DSP1_RX_FILTERS_1 0x420 -#define WM8915_DSP1_RX_FILTERS_2 0x421 -#define WM8915_DSP1_DRC_1 0x440 -#define WM8915_DSP1_DRC_2 0x441 -#define WM8915_DSP1_DRC_3 0x442 -#define WM8915_DSP1_DRC_4 0x443 -#define WM8915_DSP1_DRC_5 0x444 -#define WM8915_DSP1_RX_EQ_GAINS_1 0x480 -#define WM8915_DSP1_RX_EQ_GAINS_2 0x481 -#define WM8915_DSP1_RX_EQ_BAND_1_A 0x482 -#define WM8915_DSP1_RX_EQ_BAND_1_B 0x483 -#define WM8915_DSP1_RX_EQ_BAND_1_PG 0x484 -#define WM8915_DSP1_RX_EQ_BAND_2_A 0x485 -#define WM8915_DSP1_RX_EQ_BAND_2_B 0x486 -#define WM8915_DSP1_RX_EQ_BAND_2_C 0x487 -#define WM8915_DSP1_RX_EQ_BAND_2_PG 0x488 -#define WM8915_DSP1_RX_EQ_BAND_3_A 0x489 -#define WM8915_DSP1_RX_EQ_BAND_3_B 0x48A -#define WM8915_DSP1_RX_EQ_BAND_3_C 0x48B -#define WM8915_DSP1_RX_EQ_BAND_3_PG 0x48C -#define WM8915_DSP1_RX_EQ_BAND_4_A 0x48D -#define WM8915_DSP1_RX_EQ_BAND_4_B 0x48E -#define WM8915_DSP1_RX_EQ_BAND_4_C 0x48F -#define WM8915_DSP1_RX_EQ_BAND_4_PG 0x490 -#define WM8915_DSP1_RX_EQ_BAND_5_A 0x491 -#define WM8915_DSP1_RX_EQ_BAND_5_B 0x492 -#define WM8915_DSP1_RX_EQ_BAND_5_PG 0x493 -#define WM8915_DSP2_TX_LEFT_VOLUME 0x500 -#define WM8915_DSP2_TX_RIGHT_VOLUME 0x501 -#define WM8915_DSP2_RX_LEFT_VOLUME 0x502 -#define WM8915_DSP2_RX_RIGHT_VOLUME 0x503 -#define WM8915_DSP2_TX_FILTERS 0x510 -#define WM8915_DSP2_RX_FILTERS_1 0x520 -#define WM8915_DSP2_RX_FILTERS_2 0x521 -#define WM8915_DSP2_DRC_1 0x540 -#define WM8915_DSP2_DRC_2 0x541 -#define WM8915_DSP2_DRC_3 0x542 -#define WM8915_DSP2_DRC_4 0x543 -#define WM8915_DSP2_DRC_5 0x544 -#define WM8915_DSP2_RX_EQ_GAINS_1 0x580 -#define WM8915_DSP2_RX_EQ_GAINS_2 0x581 -#define WM8915_DSP2_RX_EQ_BAND_1_A 0x582 -#define WM8915_DSP2_RX_EQ_BAND_1_B 0x583 -#define WM8915_DSP2_RX_EQ_BAND_1_PG 0x584 -#define WM8915_DSP2_RX_EQ_BAND_2_A 0x585 -#define WM8915_DSP2_RX_EQ_BAND_2_B 0x586 -#define WM8915_DSP2_RX_EQ_BAND_2_C 0x587 -#define WM8915_DSP2_RX_EQ_BAND_2_PG 0x588 -#define WM8915_DSP2_RX_EQ_BAND_3_A 0x589 -#define WM8915_DSP2_RX_EQ_BAND_3_B 0x58A -#define WM8915_DSP2_RX_EQ_BAND_3_C 0x58B -#define WM8915_DSP2_RX_EQ_BAND_3_PG 0x58C -#define WM8915_DSP2_RX_EQ_BAND_4_A 0x58D -#define WM8915_DSP2_RX_EQ_BAND_4_B 0x58E -#define WM8915_DSP2_RX_EQ_BAND_4_C 0x58F -#define WM8915_DSP2_RX_EQ_BAND_4_PG 0x590 -#define WM8915_DSP2_RX_EQ_BAND_5_A 0x591 -#define WM8915_DSP2_RX_EQ_BAND_5_B 0x592 -#define WM8915_DSP2_RX_EQ_BAND_5_PG 0x593 -#define WM8915_DAC1_MIXER_VOLUMES 0x600 -#define WM8915_DAC1_LEFT_MIXER_ROUTING 0x601 -#define WM8915_DAC1_RIGHT_MIXER_ROUTING 0x602 -#define WM8915_DAC2_MIXER_VOLUMES 0x603 -#define WM8915_DAC2_LEFT_MIXER_ROUTING 0x604 -#define WM8915_DAC2_RIGHT_MIXER_ROUTING 0x605 -#define WM8915_DSP1_TX_LEFT_MIXER_ROUTING 0x606 -#define WM8915_DSP1_TX_RIGHT_MIXER_ROUTING 0x607 -#define WM8915_DSP2_TX_LEFT_MIXER_ROUTING 0x608 -#define WM8915_DSP2_TX_RIGHT_MIXER_ROUTING 0x609 -#define WM8915_DSP_TX_MIXER_SELECT 0x60A -#define WM8915_DAC_SOFTMUTE 0x610 -#define WM8915_OVERSAMPLING 0x620 -#define WM8915_SIDETONE 0x621 -#define WM8915_GPIO_1 0x700 -#define WM8915_GPIO_2 0x701 -#define WM8915_GPIO_3 0x702 -#define WM8915_GPIO_4 0x703 -#define WM8915_GPIO_5 0x704 -#define WM8915_PULL_CONTROL_1 0x720 -#define WM8915_PULL_CONTROL_2 0x721 -#define WM8915_INTERRUPT_STATUS_1 0x730 -#define WM8915_INTERRUPT_STATUS_2 0x731 -#define WM8915_INTERRUPT_RAW_STATUS_2 0x732 -#define WM8915_INTERRUPT_STATUS_1_MASK 0x738 -#define WM8915_INTERRUPT_STATUS_2_MASK 0x739 -#define WM8915_INTERRUPT_CONTROL 0x740 -#define WM8915_LEFT_PDM_SPEAKER 0x800 -#define WM8915_RIGHT_PDM_SPEAKER 0x801 -#define WM8915_PDM_SPEAKER_MUTE_SEQUENCE 0x802 -#define WM8915_PDM_SPEAKER_VOLUME 0x803 -#define WM8915_WRITE_SEQUENCER_0 0x3000 -#define WM8915_WRITE_SEQUENCER_1 0x3001 -#define WM8915_WRITE_SEQUENCER_2 0x3002 -#define WM8915_WRITE_SEQUENCER_3 0x3003 -#define WM8915_WRITE_SEQUENCER_4 0x3004 -#define WM8915_WRITE_SEQUENCER_5 0x3005 -#define WM8915_WRITE_SEQUENCER_6 0x3006 -#define WM8915_WRITE_SEQUENCER_7 0x3007 -#define WM8915_WRITE_SEQUENCER_8 0x3008 -#define WM8915_WRITE_SEQUENCER_9 0x3009 -#define WM8915_WRITE_SEQUENCER_10 0x300A -#define WM8915_WRITE_SEQUENCER_11 0x300B -#define WM8915_WRITE_SEQUENCER_12 0x300C -#define WM8915_WRITE_SEQUENCER_13 0x300D -#define WM8915_WRITE_SEQUENCER_14 0x300E -#define WM8915_WRITE_SEQUENCER_15 0x300F -#define WM8915_WRITE_SEQUENCER_16 0x3010 -#define WM8915_WRITE_SEQUENCER_17 0x3011 -#define WM8915_WRITE_SEQUENCER_18 0x3012 -#define WM8915_WRITE_SEQUENCER_19 0x3013 -#define WM8915_WRITE_SEQUENCER_20 0x3014 -#define WM8915_WRITE_SEQUENCER_21 0x3015 -#define WM8915_WRITE_SEQUENCER_22 0x3016 -#define WM8915_WRITE_SEQUENCER_23 0x3017 -#define WM8915_WRITE_SEQUENCER_24 0x3018 -#define WM8915_WRITE_SEQUENCER_25 0x3019 -#define WM8915_WRITE_SEQUENCER_26 0x301A -#define WM8915_WRITE_SEQUENCER_27 0x301B -#define WM8915_WRITE_SEQUENCER_28 0x301C -#define WM8915_WRITE_SEQUENCER_29 0x301D -#define WM8915_WRITE_SEQUENCER_30 0x301E -#define WM8915_WRITE_SEQUENCER_31 0x301F -#define WM8915_WRITE_SEQUENCER_32 0x3020 -#define WM8915_WRITE_SEQUENCER_33 0x3021 -#define WM8915_WRITE_SEQUENCER_34 0x3022 -#define WM8915_WRITE_SEQUENCER_35 0x3023 -#define WM8915_WRITE_SEQUENCER_36 0x3024 -#define WM8915_WRITE_SEQUENCER_37 0x3025 -#define WM8915_WRITE_SEQUENCER_38 0x3026 -#define WM8915_WRITE_SEQUENCER_39 0x3027 -#define WM8915_WRITE_SEQUENCER_40 0x3028 -#define WM8915_WRITE_SEQUENCER_41 0x3029 -#define WM8915_WRITE_SEQUENCER_42 0x302A -#define WM8915_WRITE_SEQUENCER_43 0x302B -#define WM8915_WRITE_SEQUENCER_44 0x302C -#define WM8915_WRITE_SEQUENCER_45 0x302D -#define WM8915_WRITE_SEQUENCER_46 0x302E -#define WM8915_WRITE_SEQUENCER_47 0x302F -#define WM8915_WRITE_SEQUENCER_48 0x3030 -#define WM8915_WRITE_SEQUENCER_49 0x3031 -#define WM8915_WRITE_SEQUENCER_50 0x3032 -#define WM8915_WRITE_SEQUENCER_51 0x3033 -#define WM8915_WRITE_SEQUENCER_52 0x3034 -#define WM8915_WRITE_SEQUENCER_53 0x3035 -#define WM8915_WRITE_SEQUENCER_54 0x3036 -#define WM8915_WRITE_SEQUENCER_55 0x3037 -#define WM8915_WRITE_SEQUENCER_56 0x3038 -#define WM8915_WRITE_SEQUENCER_57 0x3039 -#define WM8915_WRITE_SEQUENCER_58 0x303A -#define WM8915_WRITE_SEQUENCER_59 0x303B -#define WM8915_WRITE_SEQUENCER_60 0x303C -#define WM8915_WRITE_SEQUENCER_61 0x303D -#define WM8915_WRITE_SEQUENCER_62 0x303E -#define WM8915_WRITE_SEQUENCER_63 0x303F -#define WM8915_WRITE_SEQUENCER_64 0x3040 -#define WM8915_WRITE_SEQUENCER_65 0x3041 -#define WM8915_WRITE_SEQUENCER_66 0x3042 -#define WM8915_WRITE_SEQUENCER_67 0x3043 -#define WM8915_WRITE_SEQUENCER_68 0x3044 -#define WM8915_WRITE_SEQUENCER_69 0x3045 -#define WM8915_WRITE_SEQUENCER_70 0x3046 -#define WM8915_WRITE_SEQUENCER_71 0x3047 -#define WM8915_WRITE_SEQUENCER_72 0x3048 -#define WM8915_WRITE_SEQUENCER_73 0x3049 -#define WM8915_WRITE_SEQUENCER_74 0x304A -#define WM8915_WRITE_SEQUENCER_75 0x304B -#define WM8915_WRITE_SEQUENCER_76 0x304C -#define WM8915_WRITE_SEQUENCER_77 0x304D -#define WM8915_WRITE_SEQUENCER_78 0x304E -#define WM8915_WRITE_SEQUENCER_79 0x304F -#define WM8915_WRITE_SEQUENCER_80 0x3050 -#define WM8915_WRITE_SEQUENCER_81 0x3051 -#define WM8915_WRITE_SEQUENCER_82 0x3052 -#define WM8915_WRITE_SEQUENCER_83 0x3053 -#define WM8915_WRITE_SEQUENCER_84 0x3054 -#define WM8915_WRITE_SEQUENCER_85 0x3055 -#define WM8915_WRITE_SEQUENCER_86 0x3056 -#define WM8915_WRITE_SEQUENCER_87 0x3057 -#define WM8915_WRITE_SEQUENCER_88 0x3058 -#define WM8915_WRITE_SEQUENCER_89 0x3059 -#define WM8915_WRITE_SEQUENCER_90 0x305A -#define WM8915_WRITE_SEQUENCER_91 0x305B -#define WM8915_WRITE_SEQUENCER_92 0x305C -#define WM8915_WRITE_SEQUENCER_93 0x305D -#define WM8915_WRITE_SEQUENCER_94 0x305E -#define WM8915_WRITE_SEQUENCER_95 0x305F -#define WM8915_WRITE_SEQUENCER_96 0x3060 -#define WM8915_WRITE_SEQUENCER_97 0x3061 -#define WM8915_WRITE_SEQUENCER_98 0x3062 -#define WM8915_WRITE_SEQUENCER_99 0x3063 -#define WM8915_WRITE_SEQUENCER_100 0x3064 -#define WM8915_WRITE_SEQUENCER_101 0x3065 -#define WM8915_WRITE_SEQUENCER_102 0x3066 -#define WM8915_WRITE_SEQUENCER_103 0x3067 -#define WM8915_WRITE_SEQUENCER_104 0x3068 -#define WM8915_WRITE_SEQUENCER_105 0x3069 -#define WM8915_WRITE_SEQUENCER_106 0x306A -#define WM8915_WRITE_SEQUENCER_107 0x306B -#define WM8915_WRITE_SEQUENCER_108 0x306C -#define WM8915_WRITE_SEQUENCER_109 0x306D -#define WM8915_WRITE_SEQUENCER_110 0x306E -#define WM8915_WRITE_SEQUENCER_111 0x306F -#define WM8915_WRITE_SEQUENCER_112 0x3070 -#define WM8915_WRITE_SEQUENCER_113 0x3071 -#define WM8915_WRITE_SEQUENCER_114 0x3072 -#define WM8915_WRITE_SEQUENCER_115 0x3073 -#define WM8915_WRITE_SEQUENCER_116 0x3074 -#define WM8915_WRITE_SEQUENCER_117 0x3075 -#define WM8915_WRITE_SEQUENCER_118 0x3076 -#define WM8915_WRITE_SEQUENCER_119 0x3077 -#define WM8915_WRITE_SEQUENCER_120 0x3078 -#define WM8915_WRITE_SEQUENCER_121 0x3079 -#define WM8915_WRITE_SEQUENCER_122 0x307A -#define WM8915_WRITE_SEQUENCER_123 0x307B -#define WM8915_WRITE_SEQUENCER_124 0x307C -#define WM8915_WRITE_SEQUENCER_125 0x307D -#define WM8915_WRITE_SEQUENCER_126 0x307E -#define WM8915_WRITE_SEQUENCER_127 0x307F -#define WM8915_WRITE_SEQUENCER_128 0x3080 -#define WM8915_WRITE_SEQUENCER_129 0x3081 -#define WM8915_WRITE_SEQUENCER_130 0x3082 -#define WM8915_WRITE_SEQUENCER_131 0x3083 -#define WM8915_WRITE_SEQUENCER_132 0x3084 -#define WM8915_WRITE_SEQUENCER_133 0x3085 -#define WM8915_WRITE_SEQUENCER_134 0x3086 -#define WM8915_WRITE_SEQUENCER_135 0x3087 -#define WM8915_WRITE_SEQUENCER_136 0x3088 -#define WM8915_WRITE_SEQUENCER_137 0x3089 -#define WM8915_WRITE_SEQUENCER_138 0x308A -#define WM8915_WRITE_SEQUENCER_139 0x308B -#define WM8915_WRITE_SEQUENCER_140 0x308C -#define WM8915_WRITE_SEQUENCER_141 0x308D -#define WM8915_WRITE_SEQUENCER_142 0x308E -#define WM8915_WRITE_SEQUENCER_143 0x308F -#define WM8915_WRITE_SEQUENCER_144 0x3090 -#define WM8915_WRITE_SEQUENCER_145 0x3091 -#define WM8915_WRITE_SEQUENCER_146 0x3092 -#define WM8915_WRITE_SEQUENCER_147 0x3093 -#define WM8915_WRITE_SEQUENCER_148 0x3094 -#define WM8915_WRITE_SEQUENCER_149 0x3095 -#define WM8915_WRITE_SEQUENCER_150 0x3096 -#define WM8915_WRITE_SEQUENCER_151 0x3097 -#define WM8915_WRITE_SEQUENCER_152 0x3098 -#define WM8915_WRITE_SEQUENCER_153 0x3099 -#define WM8915_WRITE_SEQUENCER_154 0x309A -#define WM8915_WRITE_SEQUENCER_155 0x309B -#define WM8915_WRITE_SEQUENCER_156 0x309C -#define WM8915_WRITE_SEQUENCER_157 0x309D -#define WM8915_WRITE_SEQUENCER_158 0x309E -#define WM8915_WRITE_SEQUENCER_159 0x309F -#define WM8915_WRITE_SEQUENCER_160 0x30A0 -#define WM8915_WRITE_SEQUENCER_161 0x30A1 -#define WM8915_WRITE_SEQUENCER_162 0x30A2 -#define WM8915_WRITE_SEQUENCER_163 0x30A3 -#define WM8915_WRITE_SEQUENCER_164 0x30A4 -#define WM8915_WRITE_SEQUENCER_165 0x30A5 -#define WM8915_WRITE_SEQUENCER_166 0x30A6 -#define WM8915_WRITE_SEQUENCER_167 0x30A7 -#define WM8915_WRITE_SEQUENCER_168 0x30A8 -#define WM8915_WRITE_SEQUENCER_169 0x30A9 -#define WM8915_WRITE_SEQUENCER_170 0x30AA -#define WM8915_WRITE_SEQUENCER_171 0x30AB -#define WM8915_WRITE_SEQUENCER_172 0x30AC -#define WM8915_WRITE_SEQUENCER_173 0x30AD -#define WM8915_WRITE_SEQUENCER_174 0x30AE -#define WM8915_WRITE_SEQUENCER_175 0x30AF -#define WM8915_WRITE_SEQUENCER_176 0x30B0 -#define WM8915_WRITE_SEQUENCER_177 0x30B1 -#define WM8915_WRITE_SEQUENCER_178 0x30B2 -#define WM8915_WRITE_SEQUENCER_179 0x30B3 -#define WM8915_WRITE_SEQUENCER_180 0x30B4 -#define WM8915_WRITE_SEQUENCER_181 0x30B5 -#define WM8915_WRITE_SEQUENCER_182 0x30B6 -#define WM8915_WRITE_SEQUENCER_183 0x30B7 -#define WM8915_WRITE_SEQUENCER_184 0x30B8 -#define WM8915_WRITE_SEQUENCER_185 0x30B9 -#define WM8915_WRITE_SEQUENCER_186 0x30BA -#define WM8915_WRITE_SEQUENCER_187 0x30BB -#define WM8915_WRITE_SEQUENCER_188 0x30BC -#define WM8915_WRITE_SEQUENCER_189 0x30BD -#define WM8915_WRITE_SEQUENCER_190 0x30BE -#define WM8915_WRITE_SEQUENCER_191 0x30BF -#define WM8915_WRITE_SEQUENCER_192 0x30C0 -#define WM8915_WRITE_SEQUENCER_193 0x30C1 -#define WM8915_WRITE_SEQUENCER_194 0x30C2 -#define WM8915_WRITE_SEQUENCER_195 0x30C3 -#define WM8915_WRITE_SEQUENCER_196 0x30C4 -#define WM8915_WRITE_SEQUENCER_197 0x30C5 -#define WM8915_WRITE_SEQUENCER_198 0x30C6 -#define WM8915_WRITE_SEQUENCER_199 0x30C7 -#define WM8915_WRITE_SEQUENCER_200 0x30C8 -#define WM8915_WRITE_SEQUENCER_201 0x30C9 -#define WM8915_WRITE_SEQUENCER_202 0x30CA -#define WM8915_WRITE_SEQUENCER_203 0x30CB -#define WM8915_WRITE_SEQUENCER_204 0x30CC -#define WM8915_WRITE_SEQUENCER_205 0x30CD -#define WM8915_WRITE_SEQUENCER_206 0x30CE -#define WM8915_WRITE_SEQUENCER_207 0x30CF -#define WM8915_WRITE_SEQUENCER_208 0x30D0 -#define WM8915_WRITE_SEQUENCER_209 0x30D1 -#define WM8915_WRITE_SEQUENCER_210 0x30D2 -#define WM8915_WRITE_SEQUENCER_211 0x30D3 -#define WM8915_WRITE_SEQUENCER_212 0x30D4 -#define WM8915_WRITE_SEQUENCER_213 0x30D5 -#define WM8915_WRITE_SEQUENCER_214 0x30D6 -#define WM8915_WRITE_SEQUENCER_215 0x30D7 -#define WM8915_WRITE_SEQUENCER_216 0x30D8 -#define WM8915_WRITE_SEQUENCER_217 0x30D9 -#define WM8915_WRITE_SEQUENCER_218 0x30DA -#define WM8915_WRITE_SEQUENCER_219 0x30DB -#define WM8915_WRITE_SEQUENCER_220 0x30DC -#define WM8915_WRITE_SEQUENCER_221 0x30DD -#define WM8915_WRITE_SEQUENCER_222 0x30DE -#define WM8915_WRITE_SEQUENCER_223 0x30DF -#define WM8915_WRITE_SEQUENCER_224 0x30E0 -#define WM8915_WRITE_SEQUENCER_225 0x30E1 -#define WM8915_WRITE_SEQUENCER_226 0x30E2 -#define WM8915_WRITE_SEQUENCER_227 0x30E3 -#define WM8915_WRITE_SEQUENCER_228 0x30E4 -#define WM8915_WRITE_SEQUENCER_229 0x30E5 -#define WM8915_WRITE_SEQUENCER_230 0x30E6 -#define WM8915_WRITE_SEQUENCER_231 0x30E7 -#define WM8915_WRITE_SEQUENCER_232 0x30E8 -#define WM8915_WRITE_SEQUENCER_233 0x30E9 -#define WM8915_WRITE_SEQUENCER_234 0x30EA -#define WM8915_WRITE_SEQUENCER_235 0x30EB -#define WM8915_WRITE_SEQUENCER_236 0x30EC -#define WM8915_WRITE_SEQUENCER_237 0x30ED -#define WM8915_WRITE_SEQUENCER_238 0x30EE -#define WM8915_WRITE_SEQUENCER_239 0x30EF -#define WM8915_WRITE_SEQUENCER_240 0x30F0 -#define WM8915_WRITE_SEQUENCER_241 0x30F1 -#define WM8915_WRITE_SEQUENCER_242 0x30F2 -#define WM8915_WRITE_SEQUENCER_243 0x30F3 -#define WM8915_WRITE_SEQUENCER_244 0x30F4 -#define WM8915_WRITE_SEQUENCER_245 0x30F5 -#define WM8915_WRITE_SEQUENCER_246 0x30F6 -#define WM8915_WRITE_SEQUENCER_247 0x30F7 -#define WM8915_WRITE_SEQUENCER_248 0x30F8 -#define WM8915_WRITE_SEQUENCER_249 0x30F9 -#define WM8915_WRITE_SEQUENCER_250 0x30FA -#define WM8915_WRITE_SEQUENCER_251 0x30FB -#define WM8915_WRITE_SEQUENCER_252 0x30FC -#define WM8915_WRITE_SEQUENCER_253 0x30FD -#define WM8915_WRITE_SEQUENCER_254 0x30FE -#define WM8915_WRITE_SEQUENCER_255 0x30FF -#define WM8915_WRITE_SEQUENCER_256 0x3100 -#define WM8915_WRITE_SEQUENCER_257 0x3101 -#define WM8915_WRITE_SEQUENCER_258 0x3102 -#define WM8915_WRITE_SEQUENCER_259 0x3103 -#define WM8915_WRITE_SEQUENCER_260 0x3104 -#define WM8915_WRITE_SEQUENCER_261 0x3105 -#define WM8915_WRITE_SEQUENCER_262 0x3106 -#define WM8915_WRITE_SEQUENCER_263 0x3107 -#define WM8915_WRITE_SEQUENCER_264 0x3108 -#define WM8915_WRITE_SEQUENCER_265 0x3109 -#define WM8915_WRITE_SEQUENCER_266 0x310A -#define WM8915_WRITE_SEQUENCER_267 0x310B -#define WM8915_WRITE_SEQUENCER_268 0x310C -#define WM8915_WRITE_SEQUENCER_269 0x310D -#define WM8915_WRITE_SEQUENCER_270 0x310E -#define WM8915_WRITE_SEQUENCER_271 0x310F -#define WM8915_WRITE_SEQUENCER_272 0x3110 -#define WM8915_WRITE_SEQUENCER_273 0x3111 -#define WM8915_WRITE_SEQUENCER_274 0x3112 -#define WM8915_WRITE_SEQUENCER_275 0x3113 -#define WM8915_WRITE_SEQUENCER_276 0x3114 -#define WM8915_WRITE_SEQUENCER_277 0x3115 -#define WM8915_WRITE_SEQUENCER_278 0x3116 -#define WM8915_WRITE_SEQUENCER_279 0x3117 -#define WM8915_WRITE_SEQUENCER_280 0x3118 -#define WM8915_WRITE_SEQUENCER_281 0x3119 -#define WM8915_WRITE_SEQUENCER_282 0x311A -#define WM8915_WRITE_SEQUENCER_283 0x311B -#define WM8915_WRITE_SEQUENCER_284 0x311C -#define WM8915_WRITE_SEQUENCER_285 0x311D -#define WM8915_WRITE_SEQUENCER_286 0x311E -#define WM8915_WRITE_SEQUENCER_287 0x311F -#define WM8915_WRITE_SEQUENCER_288 0x3120 -#define WM8915_WRITE_SEQUENCER_289 0x3121 -#define WM8915_WRITE_SEQUENCER_290 0x3122 -#define WM8915_WRITE_SEQUENCER_291 0x3123 -#define WM8915_WRITE_SEQUENCER_292 0x3124 -#define WM8915_WRITE_SEQUENCER_293 0x3125 -#define WM8915_WRITE_SEQUENCER_294 0x3126 -#define WM8915_WRITE_SEQUENCER_295 0x3127 -#define WM8915_WRITE_SEQUENCER_296 0x3128 -#define WM8915_WRITE_SEQUENCER_297 0x3129 -#define WM8915_WRITE_SEQUENCER_298 0x312A -#define WM8915_WRITE_SEQUENCER_299 0x312B -#define WM8915_WRITE_SEQUENCER_300 0x312C -#define WM8915_WRITE_SEQUENCER_301 0x312D -#define WM8915_WRITE_SEQUENCER_302 0x312E -#define WM8915_WRITE_SEQUENCER_303 0x312F -#define WM8915_WRITE_SEQUENCER_304 0x3130 -#define WM8915_WRITE_SEQUENCER_305 0x3131 -#define WM8915_WRITE_SEQUENCER_306 0x3132 -#define WM8915_WRITE_SEQUENCER_307 0x3133 -#define WM8915_WRITE_SEQUENCER_308 0x3134 -#define WM8915_WRITE_SEQUENCER_309 0x3135 -#define WM8915_WRITE_SEQUENCER_310 0x3136 -#define WM8915_WRITE_SEQUENCER_311 0x3137 -#define WM8915_WRITE_SEQUENCER_312 0x3138 -#define WM8915_WRITE_SEQUENCER_313 0x3139 -#define WM8915_WRITE_SEQUENCER_314 0x313A -#define WM8915_WRITE_SEQUENCER_315 0x313B -#define WM8915_WRITE_SEQUENCER_316 0x313C -#define WM8915_WRITE_SEQUENCER_317 0x313D -#define WM8915_WRITE_SEQUENCER_318 0x313E -#define WM8915_WRITE_SEQUENCER_319 0x313F -#define WM8915_WRITE_SEQUENCER_320 0x3140 -#define WM8915_WRITE_SEQUENCER_321 0x3141 -#define WM8915_WRITE_SEQUENCER_322 0x3142 -#define WM8915_WRITE_SEQUENCER_323 0x3143 -#define WM8915_WRITE_SEQUENCER_324 0x3144 -#define WM8915_WRITE_SEQUENCER_325 0x3145 -#define WM8915_WRITE_SEQUENCER_326 0x3146 -#define WM8915_WRITE_SEQUENCER_327 0x3147 -#define WM8915_WRITE_SEQUENCER_328 0x3148 -#define WM8915_WRITE_SEQUENCER_329 0x3149 -#define WM8915_WRITE_SEQUENCER_330 0x314A -#define WM8915_WRITE_SEQUENCER_331 0x314B -#define WM8915_WRITE_SEQUENCER_332 0x314C -#define WM8915_WRITE_SEQUENCER_333 0x314D -#define WM8915_WRITE_SEQUENCER_334 0x314E -#define WM8915_WRITE_SEQUENCER_335 0x314F -#define WM8915_WRITE_SEQUENCER_336 0x3150 -#define WM8915_WRITE_SEQUENCER_337 0x3151 -#define WM8915_WRITE_SEQUENCER_338 0x3152 -#define WM8915_WRITE_SEQUENCER_339 0x3153 -#define WM8915_WRITE_SEQUENCER_340 0x3154 -#define WM8915_WRITE_SEQUENCER_341 0x3155 -#define WM8915_WRITE_SEQUENCER_342 0x3156 -#define WM8915_WRITE_SEQUENCER_343 0x3157 -#define WM8915_WRITE_SEQUENCER_344 0x3158 -#define WM8915_WRITE_SEQUENCER_345 0x3159 -#define WM8915_WRITE_SEQUENCER_346 0x315A -#define WM8915_WRITE_SEQUENCER_347 0x315B -#define WM8915_WRITE_SEQUENCER_348 0x315C -#define WM8915_WRITE_SEQUENCER_349 0x315D -#define WM8915_WRITE_SEQUENCER_350 0x315E -#define WM8915_WRITE_SEQUENCER_351 0x315F -#define WM8915_WRITE_SEQUENCER_352 0x3160 -#define WM8915_WRITE_SEQUENCER_353 0x3161 -#define WM8915_WRITE_SEQUENCER_354 0x3162 -#define WM8915_WRITE_SEQUENCER_355 0x3163 -#define WM8915_WRITE_SEQUENCER_356 0x3164 -#define WM8915_WRITE_SEQUENCER_357 0x3165 -#define WM8915_WRITE_SEQUENCER_358 0x3166 -#define WM8915_WRITE_SEQUENCER_359 0x3167 -#define WM8915_WRITE_SEQUENCER_360 0x3168 -#define WM8915_WRITE_SEQUENCER_361 0x3169 -#define WM8915_WRITE_SEQUENCER_362 0x316A -#define WM8915_WRITE_SEQUENCER_363 0x316B -#define WM8915_WRITE_SEQUENCER_364 0x316C -#define WM8915_WRITE_SEQUENCER_365 0x316D -#define WM8915_WRITE_SEQUENCER_366 0x316E -#define WM8915_WRITE_SEQUENCER_367 0x316F -#define WM8915_WRITE_SEQUENCER_368 0x3170 -#define WM8915_WRITE_SEQUENCER_369 0x3171 -#define WM8915_WRITE_SEQUENCER_370 0x3172 -#define WM8915_WRITE_SEQUENCER_371 0x3173 -#define WM8915_WRITE_SEQUENCER_372 0x3174 -#define WM8915_WRITE_SEQUENCER_373 0x3175 -#define WM8915_WRITE_SEQUENCER_374 0x3176 -#define WM8915_WRITE_SEQUENCER_375 0x3177 -#define WM8915_WRITE_SEQUENCER_376 0x3178 -#define WM8915_WRITE_SEQUENCER_377 0x3179 -#define WM8915_WRITE_SEQUENCER_378 0x317A -#define WM8915_WRITE_SEQUENCER_379 0x317B -#define WM8915_WRITE_SEQUENCER_380 0x317C -#define WM8915_WRITE_SEQUENCER_381 0x317D -#define WM8915_WRITE_SEQUENCER_382 0x317E -#define WM8915_WRITE_SEQUENCER_383 0x317F -#define WM8915_WRITE_SEQUENCER_384 0x3180 -#define WM8915_WRITE_SEQUENCER_385 0x3181 -#define WM8915_WRITE_SEQUENCER_386 0x3182 -#define WM8915_WRITE_SEQUENCER_387 0x3183 -#define WM8915_WRITE_SEQUENCER_388 0x3184 -#define WM8915_WRITE_SEQUENCER_389 0x3185 -#define WM8915_WRITE_SEQUENCER_390 0x3186 -#define WM8915_WRITE_SEQUENCER_391 0x3187 -#define WM8915_WRITE_SEQUENCER_392 0x3188 -#define WM8915_WRITE_SEQUENCER_393 0x3189 -#define WM8915_WRITE_SEQUENCER_394 0x318A -#define WM8915_WRITE_SEQUENCER_395 0x318B -#define WM8915_WRITE_SEQUENCER_396 0x318C -#define WM8915_WRITE_SEQUENCER_397 0x318D -#define WM8915_WRITE_SEQUENCER_398 0x318E -#define WM8915_WRITE_SEQUENCER_399 0x318F -#define WM8915_WRITE_SEQUENCER_400 0x3190 -#define WM8915_WRITE_SEQUENCER_401 0x3191 -#define WM8915_WRITE_SEQUENCER_402 0x3192 -#define WM8915_WRITE_SEQUENCER_403 0x3193 -#define WM8915_WRITE_SEQUENCER_404 0x3194 -#define WM8915_WRITE_SEQUENCER_405 0x3195 -#define WM8915_WRITE_SEQUENCER_406 0x3196 -#define WM8915_WRITE_SEQUENCER_407 0x3197 -#define WM8915_WRITE_SEQUENCER_408 0x3198 -#define WM8915_WRITE_SEQUENCER_409 0x3199 -#define WM8915_WRITE_SEQUENCER_410 0x319A -#define WM8915_WRITE_SEQUENCER_411 0x319B -#define WM8915_WRITE_SEQUENCER_412 0x319C -#define WM8915_WRITE_SEQUENCER_413 0x319D -#define WM8915_WRITE_SEQUENCER_414 0x319E -#define WM8915_WRITE_SEQUENCER_415 0x319F -#define WM8915_WRITE_SEQUENCER_416 0x31A0 -#define WM8915_WRITE_SEQUENCER_417 0x31A1 -#define WM8915_WRITE_SEQUENCER_418 0x31A2 -#define WM8915_WRITE_SEQUENCER_419 0x31A3 -#define WM8915_WRITE_SEQUENCER_420 0x31A4 -#define WM8915_WRITE_SEQUENCER_421 0x31A5 -#define WM8915_WRITE_SEQUENCER_422 0x31A6 -#define WM8915_WRITE_SEQUENCER_423 0x31A7 -#define WM8915_WRITE_SEQUENCER_424 0x31A8 -#define WM8915_WRITE_SEQUENCER_425 0x31A9 -#define WM8915_WRITE_SEQUENCER_426 0x31AA -#define WM8915_WRITE_SEQUENCER_427 0x31AB -#define WM8915_WRITE_SEQUENCER_428 0x31AC -#define WM8915_WRITE_SEQUENCER_429 0x31AD -#define WM8915_WRITE_SEQUENCER_430 0x31AE -#define WM8915_WRITE_SEQUENCER_431 0x31AF -#define WM8915_WRITE_SEQUENCER_432 0x31B0 -#define WM8915_WRITE_SEQUENCER_433 0x31B1 -#define WM8915_WRITE_SEQUENCER_434 0x31B2 -#define WM8915_WRITE_SEQUENCER_435 0x31B3 -#define WM8915_WRITE_SEQUENCER_436 0x31B4 -#define WM8915_WRITE_SEQUENCER_437 0x31B5 -#define WM8915_WRITE_SEQUENCER_438 0x31B6 -#define WM8915_WRITE_SEQUENCER_439 0x31B7 -#define WM8915_WRITE_SEQUENCER_440 0x31B8 -#define WM8915_WRITE_SEQUENCER_441 0x31B9 -#define WM8915_WRITE_SEQUENCER_442 0x31BA -#define WM8915_WRITE_SEQUENCER_443 0x31BB -#define WM8915_WRITE_SEQUENCER_444 0x31BC -#define WM8915_WRITE_SEQUENCER_445 0x31BD -#define WM8915_WRITE_SEQUENCER_446 0x31BE -#define WM8915_WRITE_SEQUENCER_447 0x31BF -#define WM8915_WRITE_SEQUENCER_448 0x31C0 -#define WM8915_WRITE_SEQUENCER_449 0x31C1 -#define WM8915_WRITE_SEQUENCER_450 0x31C2 -#define WM8915_WRITE_SEQUENCER_451 0x31C3 -#define WM8915_WRITE_SEQUENCER_452 0x31C4 -#define WM8915_WRITE_SEQUENCER_453 0x31C5 -#define WM8915_WRITE_SEQUENCER_454 0x31C6 -#define WM8915_WRITE_SEQUENCER_455 0x31C7 -#define WM8915_WRITE_SEQUENCER_456 0x31C8 -#define WM8915_WRITE_SEQUENCER_457 0x31C9 -#define WM8915_WRITE_SEQUENCER_458 0x31CA -#define WM8915_WRITE_SEQUENCER_459 0x31CB -#define WM8915_WRITE_SEQUENCER_460 0x31CC -#define WM8915_WRITE_SEQUENCER_461 0x31CD -#define WM8915_WRITE_SEQUENCER_462 0x31CE -#define WM8915_WRITE_SEQUENCER_463 0x31CF -#define WM8915_WRITE_SEQUENCER_464 0x31D0 -#define WM8915_WRITE_SEQUENCER_465 0x31D1 -#define WM8915_WRITE_SEQUENCER_466 0x31D2 -#define WM8915_WRITE_SEQUENCER_467 0x31D3 -#define WM8915_WRITE_SEQUENCER_468 0x31D4 -#define WM8915_WRITE_SEQUENCER_469 0x31D5 -#define WM8915_WRITE_SEQUENCER_470 0x31D6 -#define WM8915_WRITE_SEQUENCER_471 0x31D7 -#define WM8915_WRITE_SEQUENCER_472 0x31D8 -#define WM8915_WRITE_SEQUENCER_473 0x31D9 -#define WM8915_WRITE_SEQUENCER_474 0x31DA -#define WM8915_WRITE_SEQUENCER_475 0x31DB -#define WM8915_WRITE_SEQUENCER_476 0x31DC -#define WM8915_WRITE_SEQUENCER_477 0x31DD -#define WM8915_WRITE_SEQUENCER_478 0x31DE -#define WM8915_WRITE_SEQUENCER_479 0x31DF -#define WM8915_WRITE_SEQUENCER_480 0x31E0 -#define WM8915_WRITE_SEQUENCER_481 0x31E1 -#define WM8915_WRITE_SEQUENCER_482 0x31E2 -#define WM8915_WRITE_SEQUENCER_483 0x31E3 -#define WM8915_WRITE_SEQUENCER_484 0x31E4 -#define WM8915_WRITE_SEQUENCER_485 0x31E5 -#define WM8915_WRITE_SEQUENCER_486 0x31E6 -#define WM8915_WRITE_SEQUENCER_487 0x31E7 -#define WM8915_WRITE_SEQUENCER_488 0x31E8 -#define WM8915_WRITE_SEQUENCER_489 0x31E9 -#define WM8915_WRITE_SEQUENCER_490 0x31EA -#define WM8915_WRITE_SEQUENCER_491 0x31EB -#define WM8915_WRITE_SEQUENCER_492 0x31EC -#define WM8915_WRITE_SEQUENCER_493 0x31ED -#define WM8915_WRITE_SEQUENCER_494 0x31EE -#define WM8915_WRITE_SEQUENCER_495 0x31EF -#define WM8915_WRITE_SEQUENCER_496 0x31F0 -#define WM8915_WRITE_SEQUENCER_497 0x31F1 -#define WM8915_WRITE_SEQUENCER_498 0x31F2 -#define WM8915_WRITE_SEQUENCER_499 0x31F3 -#define WM8915_WRITE_SEQUENCER_500 0x31F4 -#define WM8915_WRITE_SEQUENCER_501 0x31F5 -#define WM8915_WRITE_SEQUENCER_502 0x31F6 -#define WM8915_WRITE_SEQUENCER_503 0x31F7 -#define WM8915_WRITE_SEQUENCER_504 0x31F8 -#define WM8915_WRITE_SEQUENCER_505 0x31F9 -#define WM8915_WRITE_SEQUENCER_506 0x31FA -#define WM8915_WRITE_SEQUENCER_507 0x31FB -#define WM8915_WRITE_SEQUENCER_508 0x31FC -#define WM8915_WRITE_SEQUENCER_509 0x31FD -#define WM8915_WRITE_SEQUENCER_510 0x31FE -#define WM8915_WRITE_SEQUENCER_511 0x31FF - -#define WM8915_REGISTER_COUNT 706 -#define WM8915_MAX_REGISTER 0x31FF - -/* - * Field Definitions. - */ - -/* - * R0 (0x00) - Software Reset - */ -#define WM8915_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ -#define WM8915_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ -#define WM8915_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ - -/* - * R1 (0x01) - Power Management (1) - */ -#define WM8915_MICB2_ENA 0x0200 /* MICB2_ENA */ -#define WM8915_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ -#define WM8915_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ -#define WM8915_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ -#define WM8915_MICB1_ENA 0x0100 /* MICB1_ENA */ -#define WM8915_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ -#define WM8915_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ -#define WM8915_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ -#define WM8915_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ -#define WM8915_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ -#define WM8915_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ -#define WM8915_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ -#define WM8915_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ -#define WM8915_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ -#define WM8915_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ -#define WM8915_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ -#define WM8915_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ -#define WM8915_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ -#define WM8915_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ -#define WM8915_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ -#define WM8915_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ -#define WM8915_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ -#define WM8915_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ -#define WM8915_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ -#define WM8915_BG_ENA 0x0001 /* BG_ENA */ -#define WM8915_BG_ENA_MASK 0x0001 /* BG_ENA */ -#define WM8915_BG_ENA_SHIFT 0 /* BG_ENA */ -#define WM8915_BG_ENA_WIDTH 1 /* BG_ENA */ - -/* - * R2 (0x02) - Power Management (2) - */ -#define WM8915_OPCLK_ENA 0x0800 /* OPCLK_ENA */ -#define WM8915_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ -#define WM8915_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ -#define WM8915_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ -#define WM8915_INL_ENA 0x0020 /* INL_ENA */ -#define WM8915_INL_ENA_MASK 0x0020 /* INL_ENA */ -#define WM8915_INL_ENA_SHIFT 5 /* INL_ENA */ -#define WM8915_INL_ENA_WIDTH 1 /* INL_ENA */ -#define WM8915_INR_ENA 0x0010 /* INR_ENA */ -#define WM8915_INR_ENA_MASK 0x0010 /* INR_ENA */ -#define WM8915_INR_ENA_SHIFT 4 /* INR_ENA */ -#define WM8915_INR_ENA_WIDTH 1 /* INR_ENA */ -#define WM8915_LDO2_ENA 0x0002 /* LDO2_ENA */ -#define WM8915_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ -#define WM8915_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ -#define WM8915_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ - -/* - * R3 (0x03) - Power Management (3) - */ -#define WM8915_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */ -#define WM8915_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */ -#define WM8915_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */ -#define WM8915_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */ -#define WM8915_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */ -#define WM8915_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */ -#define WM8915_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */ -#define WM8915_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */ -#define WM8915_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */ -#define WM8915_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */ -#define WM8915_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */ -#define WM8915_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */ -#define WM8915_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */ -#define WM8915_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */ -#define WM8915_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */ -#define WM8915_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */ -#define WM8915_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ -#define WM8915_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ -#define WM8915_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ -#define WM8915_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ -#define WM8915_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ -#define WM8915_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ -#define WM8915_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ -#define WM8915_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ -#define WM8915_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ -#define WM8915_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ -#define WM8915_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ -#define WM8915_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ -#define WM8915_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ -#define WM8915_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ -#define WM8915_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ -#define WM8915_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ -#define WM8915_ADCL_ENA 0x0002 /* ADCL_ENA */ -#define WM8915_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ -#define WM8915_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ -#define WM8915_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ -#define WM8915_ADCR_ENA 0x0001 /* ADCR_ENA */ -#define WM8915_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ -#define WM8915_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ -#define WM8915_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ - -/* - * R4 (0x04) - Power Management (4) - */ -#define WM8915_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */ -#define WM8915_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */ -#define WM8915_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */ -#define WM8915_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */ -#define WM8915_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */ -#define WM8915_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */ -#define WM8915_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */ -#define WM8915_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */ -#define WM8915_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */ -#define WM8915_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */ -#define WM8915_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */ -#define WM8915_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */ -#define WM8915_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */ -#define WM8915_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */ -#define WM8915_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */ -#define WM8915_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */ -#define WM8915_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */ -#define WM8915_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */ -#define WM8915_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */ -#define WM8915_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */ -#define WM8915_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */ -#define WM8915_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */ -#define WM8915_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */ -#define WM8915_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */ -#define WM8915_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */ -#define WM8915_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */ -#define WM8915_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */ -#define WM8915_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */ -#define WM8915_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */ -#define WM8915_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */ -#define WM8915_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */ -#define WM8915_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */ - -/* - * R5 (0x05) - Power Management (5) - */ -#define WM8915_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */ -#define WM8915_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */ -#define WM8915_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */ -#define WM8915_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */ -#define WM8915_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */ -#define WM8915_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */ -#define WM8915_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */ -#define WM8915_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */ -#define WM8915_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */ -#define WM8915_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */ -#define WM8915_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */ -#define WM8915_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */ -#define WM8915_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */ -#define WM8915_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */ -#define WM8915_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */ -#define WM8915_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */ -#define WM8915_DAC2L_ENA 0x0008 /* DAC2L_ENA */ -#define WM8915_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ -#define WM8915_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ -#define WM8915_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ -#define WM8915_DAC2R_ENA 0x0004 /* DAC2R_ENA */ -#define WM8915_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ -#define WM8915_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ -#define WM8915_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ -#define WM8915_DAC1L_ENA 0x0002 /* DAC1L_ENA */ -#define WM8915_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ -#define WM8915_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ -#define WM8915_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ -#define WM8915_DAC1R_ENA 0x0001 /* DAC1R_ENA */ -#define WM8915_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ -#define WM8915_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ -#define WM8915_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ - -/* - * R6 (0x06) - Power Management (6) - */ -#define WM8915_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */ -#define WM8915_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */ -#define WM8915_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */ -#define WM8915_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */ -#define WM8915_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */ -#define WM8915_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */ -#define WM8915_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */ -#define WM8915_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */ -#define WM8915_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */ -#define WM8915_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */ -#define WM8915_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */ -#define WM8915_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */ -#define WM8915_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */ -#define WM8915_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */ -#define WM8915_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */ -#define WM8915_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */ -#define WM8915_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */ -#define WM8915_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */ -#define WM8915_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */ -#define WM8915_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */ -#define WM8915_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */ -#define WM8915_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */ -#define WM8915_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */ -#define WM8915_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */ -#define WM8915_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */ -#define WM8915_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */ -#define WM8915_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */ -#define WM8915_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */ -#define WM8915_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */ -#define WM8915_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */ -#define WM8915_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */ -#define WM8915_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */ - -/* - * R7 (0x07) - Power Management (7) - */ -#define WM8915_DMIC2_FN 0x0200 /* DMIC2_FN */ -#define WM8915_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */ -#define WM8915_DMIC2_FN_SHIFT 9 /* DMIC2_FN */ -#define WM8915_DMIC2_FN_WIDTH 1 /* DMIC2_FN */ -#define WM8915_DMIC1_FN 0x0100 /* DMIC1_FN */ -#define WM8915_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */ -#define WM8915_DMIC1_FN_SHIFT 8 /* DMIC1_FN */ -#define WM8915_DMIC1_FN_WIDTH 1 /* DMIC1_FN */ -#define WM8915_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */ -#define WM8915_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */ -#define WM8915_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */ -#define WM8915_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */ -#define WM8915_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */ -#define WM8915_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */ -#define WM8915_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */ -#define WM8915_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */ -#define WM8915_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */ -#define WM8915_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */ -#define WM8915_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */ -#define WM8915_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */ -#define WM8915_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */ -#define WM8915_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */ -#define WM8915_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */ -#define WM8915_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */ -#define WM8915_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */ -#define WM8915_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */ -#define WM8915_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */ -#define WM8915_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */ -#define WM8915_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */ -#define WM8915_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */ - -/* - * R8 (0x08) - Power Management (8) - */ -#define WM8915_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */ -#define WM8915_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */ -#define WM8915_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */ -#define WM8915_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */ -#define WM8915_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */ -#define WM8915_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */ -#define WM8915_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */ -#define WM8915_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */ -#define WM8915_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */ -#define WM8915_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */ -#define WM8915_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */ - -/* - * R16 (0x10) - Left Line Input Volume - */ -#define WM8915_IN1_VU 0x0080 /* IN1_VU */ -#define WM8915_IN1_VU_MASK 0x0080 /* IN1_VU */ -#define WM8915_IN1_VU_SHIFT 7 /* IN1_VU */ -#define WM8915_IN1_VU_WIDTH 1 /* IN1_VU */ -#define WM8915_IN1L_ZC 0x0020 /* IN1L_ZC */ -#define WM8915_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ -#define WM8915_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ -#define WM8915_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ -#define WM8915_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ -#define WM8915_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ -#define WM8915_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ - -/* - * R17 (0x11) - Right Line Input Volume - */ -#define WM8915_IN1_VU 0x0080 /* IN1_VU */ -#define WM8915_IN1_VU_MASK 0x0080 /* IN1_VU */ -#define WM8915_IN1_VU_SHIFT 7 /* IN1_VU */ -#define WM8915_IN1_VU_WIDTH 1 /* IN1_VU */ -#define WM8915_IN1R_ZC 0x0020 /* IN1R_ZC */ -#define WM8915_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ -#define WM8915_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ -#define WM8915_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ -#define WM8915_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ -#define WM8915_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ -#define WM8915_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ - -/* - * R18 (0x12) - Line Input Control - */ -#define WM8915_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */ -#define WM8915_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */ -#define WM8915_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */ -#define WM8915_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */ -#define WM8915_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */ -#define WM8915_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */ - -/* - * R21 (0x15) - DAC1 HPOUT1 Volume - */ -#define WM8915_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */ -#define WM8915_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ -#define WM8915_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ -#define WM8915_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */ -#define WM8915_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */ -#define WM8915_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */ - -/* - * R22 (0x16) - DAC2 HPOUT2 Volume - */ -#define WM8915_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */ -#define WM8915_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ -#define WM8915_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ -#define WM8915_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */ -#define WM8915_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */ -#define WM8915_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */ - -/* - * R24 (0x18) - DAC1 Left Volume - */ -#define WM8915_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ -#define WM8915_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ -#define WM8915_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ -#define WM8915_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ -#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */ -#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */ -#define WM8915_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ -#define WM8915_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ -#define WM8915_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ - -/* - * R25 (0x19) - DAC1 Right Volume - */ -#define WM8915_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ -#define WM8915_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ -#define WM8915_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ -#define WM8915_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ -#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */ -#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */ -#define WM8915_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ -#define WM8915_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ -#define WM8915_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ - -/* - * R26 (0x1A) - DAC2 Left Volume - */ -#define WM8915_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ -#define WM8915_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ -#define WM8915_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ -#define WM8915_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ -#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */ -#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */ -#define WM8915_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ -#define WM8915_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ -#define WM8915_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ - -/* - * R27 (0x1B) - DAC2 Right Volume - */ -#define WM8915_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ -#define WM8915_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ -#define WM8915_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ -#define WM8915_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ -#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */ -#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */ -#define WM8915_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ -#define WM8915_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ -#define WM8915_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ - -/* - * R28 (0x1C) - Output1 Left Volume - */ -#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */ -#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */ -#define WM8915_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ -#define WM8915_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ -#define WM8915_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ -#define WM8915_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ -#define WM8915_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */ -#define WM8915_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */ -#define WM8915_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */ - -/* - * R29 (0x1D) - Output1 Right Volume - */ -#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */ -#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */ -#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */ -#define WM8915_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ -#define WM8915_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ -#define WM8915_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ -#define WM8915_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ -#define WM8915_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */ -#define WM8915_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */ -#define WM8915_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */ - -/* - * R30 (0x1E) - Output2 Left Volume - */ -#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */ -#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */ -#define WM8915_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */ -#define WM8915_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */ -#define WM8915_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */ -#define WM8915_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ -#define WM8915_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */ -#define WM8915_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */ -#define WM8915_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */ - -/* - * R31 (0x1F) - Output2 Right Volume - */ -#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */ -#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */ -#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */ -#define WM8915_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */ -#define WM8915_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */ -#define WM8915_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */ -#define WM8915_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ -#define WM8915_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */ -#define WM8915_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */ -#define WM8915_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */ - -/* - * R32 (0x20) - MICBIAS (1) - */ -#define WM8915_MICB1_RATE 0x0020 /* MICB1_RATE */ -#define WM8915_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ -#define WM8915_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ -#define WM8915_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ -#define WM8915_MICB1_MODE 0x0010 /* MICB1_MODE */ -#define WM8915_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */ -#define WM8915_MICB1_MODE_SHIFT 4 /* MICB1_MODE */ -#define WM8915_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ -#define WM8915_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */ -#define WM8915_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */ -#define WM8915_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */ -#define WM8915_MICB1_DISCH 0x0001 /* MICB1_DISCH */ -#define WM8915_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ -#define WM8915_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ -#define WM8915_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ - -/* - * R33 (0x21) - MICBIAS (2) - */ -#define WM8915_MICB2_RATE 0x0020 /* MICB2_RATE */ -#define WM8915_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ -#define WM8915_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ -#define WM8915_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ -#define WM8915_MICB2_MODE 0x0010 /* MICB2_MODE */ -#define WM8915_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */ -#define WM8915_MICB2_MODE_SHIFT 4 /* MICB2_MODE */ -#define WM8915_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ -#define WM8915_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */ -#define WM8915_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */ -#define WM8915_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */ -#define WM8915_MICB2_DISCH 0x0001 /* MICB2_DISCH */ -#define WM8915_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ -#define WM8915_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ -#define WM8915_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ - -/* - * R40 (0x28) - LDO 1 - */ -#define WM8915_LDO1_MODE 0x0020 /* LDO1_MODE */ -#define WM8915_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ -#define WM8915_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ -#define WM8915_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ -#define WM8915_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ -#define WM8915_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ -#define WM8915_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ -#define WM8915_LDO1_DISCH 0x0001 /* LDO1_DISCH */ -#define WM8915_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ -#define WM8915_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ -#define WM8915_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ - -/* - * R41 (0x29) - LDO 2 - */ -#define WM8915_LDO2_MODE 0x0020 /* LDO2_MODE */ -#define WM8915_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ -#define WM8915_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ -#define WM8915_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ -#define WM8915_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ -#define WM8915_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ -#define WM8915_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ -#define WM8915_LDO2_DISCH 0x0001 /* LDO2_DISCH */ -#define WM8915_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ -#define WM8915_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ -#define WM8915_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ - -/* - * R48 (0x30) - Accessory Detect Mode 1 - */ -#define WM8915_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ -#define WM8915_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ -#define WM8915_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ - -/* - * R49 (0x31) - Accessory Detect Mode 2 - */ -#define WM8915_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */ -#define WM8915_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */ -#define WM8915_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */ -#define WM8915_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */ -#define WM8915_MICD_SRC 0x0002 /* MICD_SRC */ -#define WM8915_MICD_SRC_MASK 0x0002 /* MICD_SRC */ -#define WM8915_MICD_SRC_SHIFT 1 /* MICD_SRC */ -#define WM8915_MICD_SRC_WIDTH 1 /* MICD_SRC */ -#define WM8915_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */ -#define WM8915_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */ -#define WM8915_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */ -#define WM8915_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */ - -/* - * R52 (0x34) - Headphone Detect 1 - */ -#define WM8915_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ -#define WM8915_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ -#define WM8915_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ -#define WM8915_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ -#define WM8915_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ -#define WM8915_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ -#define WM8915_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ -#define WM8915_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ -#define WM8915_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ -#define WM8915_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ -#define WM8915_HP_POLL 0x0001 /* HP_POLL */ -#define WM8915_HP_POLL_MASK 0x0001 /* HP_POLL */ -#define WM8915_HP_POLL_SHIFT 0 /* HP_POLL */ -#define WM8915_HP_POLL_WIDTH 1 /* HP_POLL */ - -/* - * R53 (0x35) - Headphone Detect 2 - */ -#define WM8915_HP_DONE 0x0080 /* HP_DONE */ -#define WM8915_HP_DONE_MASK 0x0080 /* HP_DONE */ -#define WM8915_HP_DONE_SHIFT 7 /* HP_DONE */ -#define WM8915_HP_DONE_WIDTH 1 /* HP_DONE */ -#define WM8915_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ -#define WM8915_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ -#define WM8915_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ - -/* - * R56 (0x38) - Mic Detect 1 - */ -#define WM8915_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ -#define WM8915_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ -#define WM8915_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ -#define WM8915_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ -#define WM8915_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ -#define WM8915_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ -#define WM8915_MICD_DBTIME 0x0002 /* MICD_DBTIME */ -#define WM8915_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ -#define WM8915_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ -#define WM8915_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ -#define WM8915_MICD_ENA 0x0001 /* MICD_ENA */ -#define WM8915_MICD_ENA_MASK 0x0001 /* MICD_ENA */ -#define WM8915_MICD_ENA_SHIFT 0 /* MICD_ENA */ -#define WM8915_MICD_ENA_WIDTH 1 /* MICD_ENA */ - -/* - * R57 (0x39) - Mic Detect 2 - */ -#define WM8915_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ -#define WM8915_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ -#define WM8915_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ - -/* - * R58 (0x3A) - Mic Detect 3 - */ -#define WM8915_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ -#define WM8915_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ -#define WM8915_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ -#define WM8915_MICD_VALID 0x0002 /* MICD_VALID */ -#define WM8915_MICD_VALID_MASK 0x0002 /* MICD_VALID */ -#define WM8915_MICD_VALID_SHIFT 1 /* MICD_VALID */ -#define WM8915_MICD_VALID_WIDTH 1 /* MICD_VALID */ -#define WM8915_MICD_STS 0x0001 /* MICD_STS */ -#define WM8915_MICD_STS_MASK 0x0001 /* MICD_STS */ -#define WM8915_MICD_STS_SHIFT 0 /* MICD_STS */ -#define WM8915_MICD_STS_WIDTH 1 /* MICD_STS */ - -/* - * R64 (0x40) - Charge Pump (1) - */ -#define WM8915_CP_ENA 0x8000 /* CP_ENA */ -#define WM8915_CP_ENA_MASK 0x8000 /* CP_ENA */ -#define WM8915_CP_ENA_SHIFT 15 /* CP_ENA */ -#define WM8915_CP_ENA_WIDTH 1 /* CP_ENA */ - -/* - * R65 (0x41) - Charge Pump (2) - */ -#define WM8915_CP_DISCH 0x8000 /* CP_DISCH */ -#define WM8915_CP_DISCH_MASK 0x8000 /* CP_DISCH */ -#define WM8915_CP_DISCH_SHIFT 15 /* CP_DISCH */ -#define WM8915_CP_DISCH_WIDTH 1 /* CP_DISCH */ - -/* - * R80 (0x50) - DC Servo (1) - */ -#define WM8915_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ -#define WM8915_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ -#define WM8915_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ -#define WM8915_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ -#define WM8915_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ -#define WM8915_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ -#define WM8915_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ -#define WM8915_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ -#define WM8915_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ -#define WM8915_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ -#define WM8915_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ -#define WM8915_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ -#define WM8915_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ -#define WM8915_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ -#define WM8915_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ -#define WM8915_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ - -/* - * R81 (0x51) - DC Servo (2) - */ -#define WM8915_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ -#define WM8915_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ -#define WM8915_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ -#define WM8915_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ -#define WM8915_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ -#define WM8915_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ -#define WM8915_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ -#define WM8915_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ -#define WM8915_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ -#define WM8915_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ -#define WM8915_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ -#define WM8915_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ -#define WM8915_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ -#define WM8915_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ -#define WM8915_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ -#define WM8915_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ -#define WM8915_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ -#define WM8915_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ -#define WM8915_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ -#define WM8915_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ -#define WM8915_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ -#define WM8915_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ -#define WM8915_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ -#define WM8915_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ -#define WM8915_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ -#define WM8915_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ -#define WM8915_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ -#define WM8915_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ -#define WM8915_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ -#define WM8915_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ -#define WM8915_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ -#define WM8915_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ -#define WM8915_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ -#define WM8915_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ -#define WM8915_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ -#define WM8915_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ -#define WM8915_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ -#define WM8915_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ -#define WM8915_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ -#define WM8915_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ -#define WM8915_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ -#define WM8915_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ -#define WM8915_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ -#define WM8915_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ -#define WM8915_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ -#define WM8915_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ -#define WM8915_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ -#define WM8915_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ -#define WM8915_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ -#define WM8915_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ -#define WM8915_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ -#define WM8915_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ -#define WM8915_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ -#define WM8915_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ -#define WM8915_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ -#define WM8915_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ -#define WM8915_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ -#define WM8915_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ -#define WM8915_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ -#define WM8915_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ -#define WM8915_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ -#define WM8915_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ -#define WM8915_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ -#define WM8915_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ - -/* - * R82 (0x52) - DC Servo (3) - */ -#define WM8915_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ -#define WM8915_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ -#define WM8915_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ -#define WM8915_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ -#define WM8915_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ -#define WM8915_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ - -/* - * R84 (0x54) - DC Servo (5) - */ -#define WM8915_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ -#define WM8915_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ -#define WM8915_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ -#define WM8915_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ -#define WM8915_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ -#define WM8915_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ - -/* - * R85 (0x55) - DC Servo (6) - */ -#define WM8915_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ -#define WM8915_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ -#define WM8915_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ -#define WM8915_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ -#define WM8915_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ -#define WM8915_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ - -/* - * R86 (0x56) - DC Servo (7) - */ -#define WM8915_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ -#define WM8915_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ -#define WM8915_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ -#define WM8915_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ -#define WM8915_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ -#define WM8915_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ - -/* - * R87 (0x57) - DC Servo Readback 0 - */ -#define WM8915_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ -#define WM8915_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ -#define WM8915_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ -#define WM8915_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ -#define WM8915_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ -#define WM8915_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ -#define WM8915_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ -#define WM8915_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ -#define WM8915_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ - -/* - * R96 (0x60) - Analogue HP (1) - */ -#define WM8915_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ -#define WM8915_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ -#define WM8915_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ -#define WM8915_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ -#define WM8915_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ -#define WM8915_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ -#define WM8915_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ -#define WM8915_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ -#define WM8915_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ -#define WM8915_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ -#define WM8915_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ -#define WM8915_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ -#define WM8915_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ -#define WM8915_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ -#define WM8915_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ -#define WM8915_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ -#define WM8915_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ -#define WM8915_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ -#define WM8915_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ -#define WM8915_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ -#define WM8915_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ -#define WM8915_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ -#define WM8915_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ -#define WM8915_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ - -/* - * R97 (0x61) - Analogue HP (2) - */ -#define WM8915_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ -#define WM8915_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ -#define WM8915_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ -#define WM8915_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ -#define WM8915_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ -#define WM8915_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ -#define WM8915_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ -#define WM8915_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ -#define WM8915_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ -#define WM8915_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ -#define WM8915_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ -#define WM8915_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ -#define WM8915_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ -#define WM8915_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ -#define WM8915_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ -#define WM8915_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ -#define WM8915_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ -#define WM8915_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ -#define WM8915_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ -#define WM8915_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ -#define WM8915_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ -#define WM8915_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ -#define WM8915_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ -#define WM8915_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ - -/* - * R256 (0x100) - Chip Revision - */ -#define WM8915_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ -#define WM8915_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ -#define WM8915_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ - -/* - * R257 (0x101) - Control Interface (1) - */ -#define WM8915_AUTO_INC 0x0004 /* AUTO_INC */ -#define WM8915_AUTO_INC_MASK 0x0004 /* AUTO_INC */ -#define WM8915_AUTO_INC_SHIFT 2 /* AUTO_INC */ -#define WM8915_AUTO_INC_WIDTH 1 /* AUTO_INC */ - -/* - * R272 (0x110) - Write Sequencer Ctrl (1) - */ -#define WM8915_WSEQ_ENA 0x8000 /* WSEQ_ENA */ -#define WM8915_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ -#define WM8915_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ -#define WM8915_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ -#define WM8915_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ -#define WM8915_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ -#define WM8915_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ -#define WM8915_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ -#define WM8915_WSEQ_START 0x0100 /* WSEQ_START */ -#define WM8915_WSEQ_START_MASK 0x0100 /* WSEQ_START */ -#define WM8915_WSEQ_START_SHIFT 8 /* WSEQ_START */ -#define WM8915_WSEQ_START_WIDTH 1 /* WSEQ_START */ -#define WM8915_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ -#define WM8915_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ -#define WM8915_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ - -/* - * R273 (0x111) - Write Sequencer Ctrl (2) - */ -#define WM8915_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ -#define WM8915_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ -#define WM8915_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ -#define WM8915_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ -#define WM8915_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ -#define WM8915_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ -#define WM8915_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ - -/* - * R512 (0x200) - AIF Clocking (1) - */ -#define WM8915_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */ -#define WM8915_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */ -#define WM8915_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */ -#define WM8915_SYSCLK_INV 0x0004 /* SYSCLK_INV */ -#define WM8915_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */ -#define WM8915_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */ -#define WM8915_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */ -#define WM8915_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */ -#define WM8915_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */ -#define WM8915_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */ -#define WM8915_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */ -#define WM8915_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */ -#define WM8915_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */ -#define WM8915_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */ -#define WM8915_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ - -/* - * R513 (0x201) - AIF Clocking (2) - */ -#define WM8915_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */ -#define WM8915_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */ -#define WM8915_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */ -#define WM8915_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */ -#define WM8915_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */ -#define WM8915_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */ - -/* - * R520 (0x208) - Clocking (1) - */ -#define WM8915_LFCLK_ENA 0x0020 /* LFCLK_ENA */ -#define WM8915_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ -#define WM8915_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ -#define WM8915_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ -#define WM8915_TOCLK_ENA 0x0010 /* TOCLK_ENA */ -#define WM8915_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ -#define WM8915_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ -#define WM8915_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ -#define WM8915_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */ -#define WM8915_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */ -#define WM8915_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */ -#define WM8915_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */ -#define WM8915_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ -#define WM8915_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ -#define WM8915_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ -#define WM8915_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ - -/* - * R521 (0x209) - Clocking (2) - */ -#define WM8915_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ -#define WM8915_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ -#define WM8915_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ -#define WM8915_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ -#define WM8915_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ -#define WM8915_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ -#define WM8915_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ -#define WM8915_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ -#define WM8915_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ - -/* - * R528 (0x210) - AIF Rate - */ -#define WM8915_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */ -#define WM8915_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */ -#define WM8915_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */ -#define WM8915_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */ - -/* - * R544 (0x220) - FLL Control (1) - */ -#define WM8915_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ -#define WM8915_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ -#define WM8915_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ -#define WM8915_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ -#define WM8915_FLL_ENA 0x0001 /* FLL_ENA */ -#define WM8915_FLL_ENA_MASK 0x0001 /* FLL_ENA */ -#define WM8915_FLL_ENA_SHIFT 0 /* FLL_ENA */ -#define WM8915_FLL_ENA_WIDTH 1 /* FLL_ENA */ - -/* - * R545 (0x221) - FLL Control (2) - */ -#define WM8915_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ -#define WM8915_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ -#define WM8915_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ -#define WM8915_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ -#define WM8915_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ -#define WM8915_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ - -/* - * R546 (0x222) - FLL Control (3) - */ -#define WM8915_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ -#define WM8915_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ -#define WM8915_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ - -/* - * R547 (0x223) - FLL Control (4) - */ -#define WM8915_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ -#define WM8915_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ -#define WM8915_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ -#define WM8915_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */ -#define WM8915_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */ -#define WM8915_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */ - -/* - * R548 (0x224) - FLL Control (5) - */ -#define WM8915_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */ -#define WM8915_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */ -#define WM8915_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */ -#define WM8915_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */ -#define WM8915_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */ -#define WM8915_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */ -#define WM8915_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ -#define WM8915_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */ -#define WM8915_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */ -#define WM8915_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */ -#define WM8915_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */ -#define WM8915_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */ -#define WM8915_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */ -#define WM8915_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */ -#define WM8915_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */ -#define WM8915_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */ -#define WM8915_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */ - -/* - * R549 (0x225) - FLL Control (6) - */ -#define WM8915_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */ -#define WM8915_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */ -#define WM8915_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */ -#define WM8915_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */ -#define WM8915_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */ -#define WM8915_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */ -#define WM8915_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */ - -/* - * R550 (0x226) - FLL EFS 1 - */ -#define WM8915_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ -#define WM8915_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ -#define WM8915_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ - -/* - * R551 (0x227) - FLL EFS 2 - */ -#define WM8915_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */ -#define WM8915_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */ -#define WM8915_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */ -#define WM8915_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ -#define WM8915_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ -#define WM8915_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ -#define WM8915_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ - -/* - * R768 (0x300) - AIF1 Control - */ -#define WM8915_AIF1_TRI 0x0004 /* AIF1_TRI */ -#define WM8915_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */ -#define WM8915_AIF1_TRI_SHIFT 2 /* AIF1_TRI */ -#define WM8915_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ -#define WM8915_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */ -#define WM8915_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */ -#define WM8915_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */ - -/* - * R769 (0x301) - AIF1 BCLK - */ -#define WM8915_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */ -#define WM8915_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */ -#define WM8915_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */ -#define WM8915_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ -#define WM8915_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */ -#define WM8915_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */ -#define WM8915_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */ -#define WM8915_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ -#define WM8915_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */ -#define WM8915_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */ -#define WM8915_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */ -#define WM8915_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ -#define WM8915_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ -#define WM8915_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ -#define WM8915_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ - -/* - * R770 (0x302) - AIF1 TX LRCLK(1) - */ -#define WM8915_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */ -#define WM8915_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */ -#define WM8915_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */ - -/* - * R771 (0x303) - AIF1 TX LRCLK(2) - */ -#define WM8915_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */ -#define WM8915_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */ -#define WM8915_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */ -#define WM8915_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */ -#define WM8915_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ -#define WM8915_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ -#define WM8915_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ -#define WM8915_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ -#define WM8915_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ -#define WM8915_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ -#define WM8915_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ -#define WM8915_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ -#define WM8915_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ -#define WM8915_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ -#define WM8915_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ -#define WM8915_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ - -/* - * R772 (0x304) - AIF1 RX LRCLK(1) - */ -#define WM8915_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */ -#define WM8915_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */ -#define WM8915_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */ - -/* - * R773 (0x305) - AIF1 RX LRCLK(2) - */ -#define WM8915_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ -#define WM8915_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ -#define WM8915_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ -#define WM8915_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ -#define WM8915_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ -#define WM8915_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ -#define WM8915_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ -#define WM8915_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ -#define WM8915_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ -#define WM8915_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ -#define WM8915_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ -#define WM8915_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ - -/* - * R774 (0x306) - AIF1TX Data Configuration (1) - */ -#define WM8915_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */ -#define WM8915_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */ -#define WM8915_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */ -#define WM8915_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ -#define WM8915_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ -#define WM8915_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ - -/* - * R775 (0x307) - AIF1TX Data Configuration (2) - */ -#define WM8915_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */ -#define WM8915_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */ -#define WM8915_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */ -#define WM8915_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ - -/* - * R776 (0x308) - AIF1RX Data Configuration - */ -#define WM8915_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */ -#define WM8915_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */ -#define WM8915_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */ -#define WM8915_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ -#define WM8915_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ -#define WM8915_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ - -/* - * R777 (0x309) - AIF1TX Channel 0 Configuration - */ -#define WM8915_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */ -#define WM8915_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */ -#define WM8915_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */ -#define WM8915_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */ -#define WM8915_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ - -/* - * R778 (0x30A) - AIF1TX Channel 1 Configuration - */ -#define WM8915_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */ -#define WM8915_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */ -#define WM8915_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */ -#define WM8915_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */ -#define WM8915_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ - -/* - * R779 (0x30B) - AIF1TX Channel 2 Configuration - */ -#define WM8915_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */ -#define WM8915_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */ -#define WM8915_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */ -#define WM8915_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */ -#define WM8915_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ - -/* - * R780 (0x30C) - AIF1TX Channel 3 Configuration - */ -#define WM8915_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */ -#define WM8915_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */ -#define WM8915_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */ -#define WM8915_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */ -#define WM8915_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ - -/* - * R781 (0x30D) - AIF1TX Channel 4 Configuration - */ -#define WM8915_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */ -#define WM8915_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */ -#define WM8915_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */ -#define WM8915_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */ -#define WM8915_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ - -/* - * R782 (0x30E) - AIF1TX Channel 5 Configuration - */ -#define WM8915_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */ -#define WM8915_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */ -#define WM8915_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */ -#define WM8915_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */ -#define WM8915_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */ -#define WM8915_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */ -#define WM8915_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ -#define WM8915_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ - -/* - * R783 (0x30F) - AIF1RX Channel 0 Configuration - */ -#define WM8915_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */ -#define WM8915_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */ -#define WM8915_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */ -#define WM8915_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */ -#define WM8915_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ - -/* - * R784 (0x310) - AIF1RX Channel 1 Configuration - */ -#define WM8915_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */ -#define WM8915_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */ -#define WM8915_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */ -#define WM8915_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */ -#define WM8915_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ - -/* - * R785 (0x311) - AIF1RX Channel 2 Configuration - */ -#define WM8915_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */ -#define WM8915_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */ -#define WM8915_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */ -#define WM8915_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */ -#define WM8915_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ - -/* - * R786 (0x312) - AIF1RX Channel 3 Configuration - */ -#define WM8915_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */ -#define WM8915_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */ -#define WM8915_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */ -#define WM8915_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */ -#define WM8915_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ - -/* - * R787 (0x313) - AIF1RX Channel 4 Configuration - */ -#define WM8915_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */ -#define WM8915_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */ -#define WM8915_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */ -#define WM8915_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */ -#define WM8915_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ - -/* - * R788 (0x314) - AIF1RX Channel 5 Configuration - */ -#define WM8915_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */ -#define WM8915_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */ -#define WM8915_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */ -#define WM8915_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */ -#define WM8915_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */ -#define WM8915_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */ -#define WM8915_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ -#define WM8915_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ - -/* - * R789 (0x315) - AIF1RX Mono Configuration - */ -#define WM8915_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ -#define WM8915_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ -#define WM8915_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */ -#define WM8915_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */ -#define WM8915_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ -#define WM8915_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ -#define WM8915_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */ -#define WM8915_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */ -#define WM8915_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ -#define WM8915_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ -#define WM8915_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */ -#define WM8915_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */ - -/* - * R794 (0x31A) - AIF1TX Test - */ -#define WM8915_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */ -#define WM8915_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */ -#define WM8915_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */ -#define WM8915_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */ -#define WM8915_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */ -#define WM8915_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */ -#define WM8915_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */ -#define WM8915_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */ -#define WM8915_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */ -#define WM8915_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */ -#define WM8915_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */ -#define WM8915_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */ - -/* - * R800 (0x320) - AIF2 Control - */ -#define WM8915_AIF2_TRI 0x0004 /* AIF2_TRI */ -#define WM8915_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */ -#define WM8915_AIF2_TRI_SHIFT 2 /* AIF2_TRI */ -#define WM8915_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ -#define WM8915_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */ -#define WM8915_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */ -#define WM8915_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */ - -/* - * R801 (0x321) - AIF2 BCLK - */ -#define WM8915_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */ -#define WM8915_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */ -#define WM8915_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */ -#define WM8915_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ -#define WM8915_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */ -#define WM8915_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */ -#define WM8915_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */ -#define WM8915_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ -#define WM8915_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */ -#define WM8915_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */ -#define WM8915_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */ -#define WM8915_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ -#define WM8915_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */ -#define WM8915_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */ -#define WM8915_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */ - -/* - * R802 (0x322) - AIF2 TX LRCLK(1) - */ -#define WM8915_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */ -#define WM8915_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */ -#define WM8915_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */ - -/* - * R803 (0x323) - AIF2 TX LRCLK(2) - */ -#define WM8915_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */ -#define WM8915_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */ -#define WM8915_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */ -#define WM8915_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */ -#define WM8915_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ -#define WM8915_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ -#define WM8915_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ -#define WM8915_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ -#define WM8915_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ -#define WM8915_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ -#define WM8915_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ -#define WM8915_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ -#define WM8915_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ -#define WM8915_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ -#define WM8915_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ -#define WM8915_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ - -/* - * R804 (0x324) - AIF2 RX LRCLK(1) - */ -#define WM8915_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */ -#define WM8915_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */ -#define WM8915_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */ - -/* - * R805 (0x325) - AIF2 RX LRCLK(2) - */ -#define WM8915_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ -#define WM8915_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ -#define WM8915_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ -#define WM8915_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ -#define WM8915_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ -#define WM8915_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ -#define WM8915_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ -#define WM8915_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ -#define WM8915_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ -#define WM8915_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ -#define WM8915_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ -#define WM8915_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ - -/* - * R806 (0x326) - AIF2TX Data Configuration (1) - */ -#define WM8915_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */ -#define WM8915_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */ -#define WM8915_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */ -#define WM8915_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ -#define WM8915_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ -#define WM8915_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ - -/* - * R807 (0x327) - AIF2TX Data Configuration (2) - */ -#define WM8915_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */ -#define WM8915_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */ -#define WM8915_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */ -#define WM8915_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ - -/* - * R808 (0x328) - AIF2RX Data Configuration - */ -#define WM8915_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */ -#define WM8915_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */ -#define WM8915_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */ -#define WM8915_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ -#define WM8915_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ -#define WM8915_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ - -/* - * R809 (0x329) - AIF2TX Channel 0 Configuration - */ -#define WM8915_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */ -#define WM8915_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */ -#define WM8915_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */ -#define WM8915_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */ -#define WM8915_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ - -/* - * R810 (0x32A) - AIF2TX Channel 1 Configuration - */ -#define WM8915_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */ -#define WM8915_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */ -#define WM8915_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */ -#define WM8915_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */ -#define WM8915_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ - -/* - * R811 (0x32B) - AIF2RX Channel 0 Configuration - */ -#define WM8915_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */ -#define WM8915_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */ -#define WM8915_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */ -#define WM8915_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */ -#define WM8915_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */ -#define WM8915_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */ -#define WM8915_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ -#define WM8915_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ - -/* - * R812 (0x32C) - AIF2RX Channel 1 Configuration - */ -#define WM8915_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */ -#define WM8915_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */ -#define WM8915_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */ -#define WM8915_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */ -#define WM8915_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */ -#define WM8915_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */ -#define WM8915_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ -#define WM8915_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ - -/* - * R813 (0x32D) - AIF2RX Mono Configuration - */ -#define WM8915_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ -#define WM8915_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ -#define WM8915_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */ -#define WM8915_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */ - -/* - * R815 (0x32F) - AIF2TX Test - */ -#define WM8915_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */ -#define WM8915_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */ -#define WM8915_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */ -#define WM8915_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */ - -/* - * R1024 (0x400) - DSP1 TX Left Volume - */ -#define WM8915_DSP1TX_VU 0x0100 /* DSP1TX_VU */ -#define WM8915_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ -#define WM8915_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ -#define WM8915_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ -#define WM8915_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */ -#define WM8915_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */ -#define WM8915_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */ - -/* - * R1025 (0x401) - DSP1 TX Right Volume - */ -#define WM8915_DSP1TX_VU 0x0100 /* DSP1TX_VU */ -#define WM8915_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ -#define WM8915_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ -#define WM8915_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ -#define WM8915_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */ -#define WM8915_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */ -#define WM8915_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */ - -/* - * R1026 (0x402) - DSP1 RX Left Volume - */ -#define WM8915_DSP1RX_VU 0x0100 /* DSP1RX_VU */ -#define WM8915_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ -#define WM8915_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ -#define WM8915_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ -#define WM8915_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */ -#define WM8915_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */ -#define WM8915_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */ - -/* - * R1027 (0x403) - DSP1 RX Right Volume - */ -#define WM8915_DSP1RX_VU 0x0100 /* DSP1RX_VU */ -#define WM8915_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ -#define WM8915_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ -#define WM8915_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ -#define WM8915_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */ -#define WM8915_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */ -#define WM8915_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */ - -/* - * R1040 (0x410) - DSP1 TX Filters - */ -#define WM8915_DSP1TX_NF 0x2000 /* DSP1TX_NF */ -#define WM8915_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */ -#define WM8915_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */ -#define WM8915_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */ -#define WM8915_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */ -#define WM8915_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */ -#define WM8915_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */ -#define WM8915_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */ -#define WM8915_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */ -#define WM8915_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */ -#define WM8915_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */ -#define WM8915_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */ -#define WM8915_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */ -#define WM8915_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */ -#define WM8915_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */ -#define WM8915_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */ -#define WM8915_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */ -#define WM8915_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */ - -/* - * R1056 (0x420) - DSP1 RX Filters (1) - */ -#define WM8915_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */ -#define WM8915_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */ -#define WM8915_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */ -#define WM8915_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */ -#define WM8915_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */ -#define WM8915_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */ -#define WM8915_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */ -#define WM8915_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */ -#define WM8915_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */ -#define WM8915_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */ -#define WM8915_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */ -#define WM8915_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */ -#define WM8915_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */ -#define WM8915_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */ -#define WM8915_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */ -#define WM8915_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */ - -/* - * R1057 (0x421) - DSP1 RX Filters (2) - */ -#define WM8915_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */ -#define WM8915_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */ -#define WM8915_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */ -#define WM8915_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */ -#define WM8915_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */ -#define WM8915_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */ -#define WM8915_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */ - -/* - * R1088 (0x440) - DSP1 DRC (1) - */ -#define WM8915_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */ -#define WM8915_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */ -#define WM8915_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */ -#define WM8915_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */ -#define WM8915_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */ -#define WM8915_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */ -#define WM8915_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */ -#define WM8915_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */ -#define WM8915_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */ -#define WM8915_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */ -#define WM8915_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */ -#define WM8915_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */ -#define WM8915_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */ -#define WM8915_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */ -#define WM8915_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */ -#define WM8915_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */ -#define WM8915_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */ -#define WM8915_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */ -#define WM8915_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ -#define WM8915_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ -#define WM8915_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */ -#define WM8915_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */ -#define WM8915_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */ -#define WM8915_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */ -#define WM8915_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */ -#define WM8915_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */ -#define WM8915_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */ -#define WM8915_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */ -#define WM8915_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */ -#define WM8915_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */ -#define WM8915_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */ -#define WM8915_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */ -#define WM8915_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */ -#define WM8915_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */ -#define WM8915_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */ -#define WM8915_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */ -#define WM8915_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */ -#define WM8915_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */ -#define WM8915_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */ -#define WM8915_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */ -#define WM8915_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */ -#define WM8915_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */ - -/* - * R1089 (0x441) - DSP1 DRC (2) - */ -#define WM8915_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */ -#define WM8915_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */ -#define WM8915_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */ -#define WM8915_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */ -#define WM8915_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */ -#define WM8915_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */ -#define WM8915_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */ -#define WM8915_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */ -#define WM8915_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */ -#define WM8915_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */ -#define WM8915_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */ -#define WM8915_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */ - -/* - * R1090 (0x442) - DSP1 DRC (3) - */ -#define WM8915_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */ -#define WM8915_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */ -#define WM8915_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */ -#define WM8915_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */ -#define WM8915_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */ -#define WM8915_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */ -#define WM8915_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */ -#define WM8915_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */ -#define WM8915_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */ -#define WM8915_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */ -#define WM8915_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */ -#define WM8915_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */ -#define WM8915_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */ -#define WM8915_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */ -#define WM8915_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */ -#define WM8915_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */ -#define WM8915_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */ -#define WM8915_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */ - -/* - * R1091 (0x443) - DSP1 DRC (4) - */ -#define WM8915_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */ -#define WM8915_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */ -#define WM8915_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */ -#define WM8915_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */ -#define WM8915_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */ -#define WM8915_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */ - -/* - * R1092 (0x444) - DSP1 DRC (5) - */ -#define WM8915_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */ -#define WM8915_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */ -#define WM8915_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */ -#define WM8915_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */ -#define WM8915_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */ -#define WM8915_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */ - -/* - * R1152 (0x480) - DSP1 RX EQ Gains (1) - */ -#define WM8915_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */ -#define WM8915_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */ -#define WM8915_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */ -#define WM8915_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */ -#define WM8915_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */ -#define WM8915_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */ -#define WM8915_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */ -#define WM8915_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */ -#define WM8915_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */ -#define WM8915_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */ -#define WM8915_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */ -#define WM8915_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */ -#define WM8915_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */ - -/* - * R1153 (0x481) - DSP1 RX EQ Gains (2) - */ -#define WM8915_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */ -#define WM8915_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */ -#define WM8915_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */ -#define WM8915_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */ -#define WM8915_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */ -#define WM8915_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */ - -/* - * R1154 (0x482) - DSP1 RX EQ Band 1 A - */ -#define WM8915_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */ - -/* - * R1155 (0x483) - DSP1 RX EQ Band 1 B - */ -#define WM8915_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */ - -/* - * R1156 (0x484) - DSP1 RX EQ Band 1 PG - */ -#define WM8915_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */ - -/* - * R1157 (0x485) - DSP1 RX EQ Band 2 A - */ -#define WM8915_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */ - -/* - * R1158 (0x486) - DSP1 RX EQ Band 2 B - */ -#define WM8915_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */ - -/* - * R1159 (0x487) - DSP1 RX EQ Band 2 C - */ -#define WM8915_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */ - -/* - * R1160 (0x488) - DSP1 RX EQ Band 2 PG - */ -#define WM8915_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */ - -/* - * R1161 (0x489) - DSP1 RX EQ Band 3 A - */ -#define WM8915_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */ - -/* - * R1162 (0x48A) - DSP1 RX EQ Band 3 B - */ -#define WM8915_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */ - -/* - * R1163 (0x48B) - DSP1 RX EQ Band 3 C - */ -#define WM8915_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */ - -/* - * R1164 (0x48C) - DSP1 RX EQ Band 3 PG - */ -#define WM8915_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */ - -/* - * R1165 (0x48D) - DSP1 RX EQ Band 4 A - */ -#define WM8915_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */ - -/* - * R1166 (0x48E) - DSP1 RX EQ Band 4 B - */ -#define WM8915_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */ - -/* - * R1167 (0x48F) - DSP1 RX EQ Band 4 C - */ -#define WM8915_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */ - -/* - * R1168 (0x490) - DSP1 RX EQ Band 4 PG - */ -#define WM8915_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */ - -/* - * R1169 (0x491) - DSP1 RX EQ Band 5 A - */ -#define WM8915_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */ -#define WM8915_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */ - -/* - * R1170 (0x492) - DSP1 RX EQ Band 5 B - */ -#define WM8915_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */ -#define WM8915_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */ - -/* - * R1171 (0x493) - DSP1 RX EQ Band 5 PG - */ -#define WM8915_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */ -#define WM8915_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */ - -/* - * R1280 (0x500) - DSP2 TX Left Volume - */ -#define WM8915_DSP2TX_VU 0x0100 /* DSP2TX_VU */ -#define WM8915_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ -#define WM8915_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ -#define WM8915_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ -#define WM8915_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */ -#define WM8915_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */ -#define WM8915_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */ - -/* - * R1281 (0x501) - DSP2 TX Right Volume - */ -#define WM8915_DSP2TX_VU 0x0100 /* DSP2TX_VU */ -#define WM8915_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ -#define WM8915_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ -#define WM8915_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ -#define WM8915_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */ -#define WM8915_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */ -#define WM8915_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */ - -/* - * R1282 (0x502) - DSP2 RX Left Volume - */ -#define WM8915_DSP2RX_VU 0x0100 /* DSP2RX_VU */ -#define WM8915_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ -#define WM8915_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ -#define WM8915_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ -#define WM8915_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */ -#define WM8915_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */ -#define WM8915_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */ - -/* - * R1283 (0x503) - DSP2 RX Right Volume - */ -#define WM8915_DSP2RX_VU 0x0100 /* DSP2RX_VU */ -#define WM8915_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ -#define WM8915_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ -#define WM8915_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ -#define WM8915_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */ -#define WM8915_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */ -#define WM8915_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */ - -/* - * R1296 (0x510) - DSP2 TX Filters - */ -#define WM8915_DSP2TX_NF 0x2000 /* DSP2TX_NF */ -#define WM8915_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */ -#define WM8915_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */ -#define WM8915_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */ -#define WM8915_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */ -#define WM8915_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */ -#define WM8915_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */ -#define WM8915_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */ -#define WM8915_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */ -#define WM8915_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */ -#define WM8915_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */ -#define WM8915_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */ -#define WM8915_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */ -#define WM8915_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */ -#define WM8915_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */ -#define WM8915_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */ -#define WM8915_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */ -#define WM8915_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */ - -/* - * R1312 (0x520) - DSP2 RX Filters (1) - */ -#define WM8915_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */ -#define WM8915_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */ -#define WM8915_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */ -#define WM8915_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */ -#define WM8915_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */ -#define WM8915_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */ -#define WM8915_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */ -#define WM8915_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */ -#define WM8915_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */ -#define WM8915_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */ -#define WM8915_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */ -#define WM8915_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */ -#define WM8915_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */ -#define WM8915_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */ -#define WM8915_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */ -#define WM8915_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */ - -/* - * R1313 (0x521) - DSP2 RX Filters (2) - */ -#define WM8915_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */ -#define WM8915_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */ -#define WM8915_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */ -#define WM8915_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */ -#define WM8915_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */ -#define WM8915_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */ -#define WM8915_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */ - -/* - * R1344 (0x540) - DSP2 DRC (1) - */ -#define WM8915_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */ -#define WM8915_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */ -#define WM8915_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */ -#define WM8915_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */ -#define WM8915_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */ -#define WM8915_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */ -#define WM8915_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */ -#define WM8915_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */ -#define WM8915_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */ -#define WM8915_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */ -#define WM8915_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */ -#define WM8915_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */ -#define WM8915_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */ -#define WM8915_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */ -#define WM8915_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */ -#define WM8915_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */ -#define WM8915_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */ -#define WM8915_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */ -#define WM8915_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ -#define WM8915_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ -#define WM8915_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */ -#define WM8915_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */ -#define WM8915_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */ -#define WM8915_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */ -#define WM8915_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */ -#define WM8915_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */ -#define WM8915_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */ -#define WM8915_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */ -#define WM8915_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */ -#define WM8915_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */ -#define WM8915_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */ -#define WM8915_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */ -#define WM8915_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */ -#define WM8915_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */ -#define WM8915_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */ -#define WM8915_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */ -#define WM8915_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */ -#define WM8915_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */ -#define WM8915_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */ -#define WM8915_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */ -#define WM8915_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */ -#define WM8915_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */ - -/* - * R1345 (0x541) - DSP2 DRC (2) - */ -#define WM8915_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */ -#define WM8915_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */ -#define WM8915_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */ -#define WM8915_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */ -#define WM8915_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */ -#define WM8915_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */ -#define WM8915_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */ -#define WM8915_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */ -#define WM8915_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */ -#define WM8915_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */ -#define WM8915_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */ -#define WM8915_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */ - -/* - * R1346 (0x542) - DSP2 DRC (3) - */ -#define WM8915_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */ -#define WM8915_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */ -#define WM8915_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */ -#define WM8915_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */ -#define WM8915_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */ -#define WM8915_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */ -#define WM8915_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */ -#define WM8915_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */ -#define WM8915_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */ -#define WM8915_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */ -#define WM8915_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */ -#define WM8915_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */ -#define WM8915_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */ -#define WM8915_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */ -#define WM8915_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */ -#define WM8915_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */ -#define WM8915_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */ -#define WM8915_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */ - -/* - * R1347 (0x543) - DSP2 DRC (4) - */ -#define WM8915_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */ -#define WM8915_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */ -#define WM8915_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */ -#define WM8915_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */ -#define WM8915_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */ -#define WM8915_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */ - -/* - * R1348 (0x544) - DSP2 DRC (5) - */ -#define WM8915_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */ -#define WM8915_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */ -#define WM8915_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */ -#define WM8915_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */ -#define WM8915_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */ -#define WM8915_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */ - -/* - * R1408 (0x580) - DSP2 RX EQ Gains (1) - */ -#define WM8915_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */ -#define WM8915_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */ -#define WM8915_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */ -#define WM8915_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */ -#define WM8915_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */ -#define WM8915_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */ -#define WM8915_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */ -#define WM8915_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */ -#define WM8915_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */ -#define WM8915_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */ -#define WM8915_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */ -#define WM8915_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */ -#define WM8915_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */ - -/* - * R1409 (0x581) - DSP2 RX EQ Gains (2) - */ -#define WM8915_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */ -#define WM8915_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */ -#define WM8915_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */ -#define WM8915_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */ -#define WM8915_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */ -#define WM8915_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */ - -/* - * R1410 (0x582) - DSP2 RX EQ Band 1 A - */ -#define WM8915_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */ - -/* - * R1411 (0x583) - DSP2 RX EQ Band 1 B - */ -#define WM8915_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */ - -/* - * R1412 (0x584) - DSP2 RX EQ Band 1 PG - */ -#define WM8915_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */ - -/* - * R1413 (0x585) - DSP2 RX EQ Band 2 A - */ -#define WM8915_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */ - -/* - * R1414 (0x586) - DSP2 RX EQ Band 2 B - */ -#define WM8915_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */ - -/* - * R1415 (0x587) - DSP2 RX EQ Band 2 C - */ -#define WM8915_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */ - -/* - * R1416 (0x588) - DSP2 RX EQ Band 2 PG - */ -#define WM8915_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */ - -/* - * R1417 (0x589) - DSP2 RX EQ Band 3 A - */ -#define WM8915_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */ - -/* - * R1418 (0x58A) - DSP2 RX EQ Band 3 B - */ -#define WM8915_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */ - -/* - * R1419 (0x58B) - DSP2 RX EQ Band 3 C - */ -#define WM8915_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */ - -/* - * R1420 (0x58C) - DSP2 RX EQ Band 3 PG - */ -#define WM8915_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */ - -/* - * R1421 (0x58D) - DSP2 RX EQ Band 4 A - */ -#define WM8915_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */ - -/* - * R1422 (0x58E) - DSP2 RX EQ Band 4 B - */ -#define WM8915_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */ - -/* - * R1423 (0x58F) - DSP2 RX EQ Band 4 C - */ -#define WM8915_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */ - -/* - * R1424 (0x590) - DSP2 RX EQ Band 4 PG - */ -#define WM8915_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */ - -/* - * R1425 (0x591) - DSP2 RX EQ Band 5 A - */ -#define WM8915_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */ -#define WM8915_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */ - -/* - * R1426 (0x592) - DSP2 RX EQ Band 5 B - */ -#define WM8915_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */ -#define WM8915_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */ - -/* - * R1427 (0x593) - DSP2 RX EQ Band 5 PG - */ -#define WM8915_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */ -#define WM8915_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */ - -/* - * R1536 (0x600) - DAC1 Mixer Volumes - */ -#define WM8915_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ -#define WM8915_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ -#define WM8915_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ -#define WM8915_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ -#define WM8915_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ -#define WM8915_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ - -/* - * R1537 (0x601) - DAC1 Left Mixer Routing - */ -#define WM8915_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ -#define WM8915_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ -#define WM8915_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ -#define WM8915_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ -#define WM8915_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ -#define WM8915_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ -#define WM8915_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ -#define WM8915_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ -#define WM8915_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */ -#define WM8915_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */ -#define WM8915_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */ -#define WM8915_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */ -#define WM8915_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */ -#define WM8915_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */ -#define WM8915_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */ -#define WM8915_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */ - -/* - * R1538 (0x602) - DAC1 Right Mixer Routing - */ -#define WM8915_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ -#define WM8915_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ -#define WM8915_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ -#define WM8915_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ -#define WM8915_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ -#define WM8915_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ -#define WM8915_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ -#define WM8915_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ -#define WM8915_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */ -#define WM8915_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */ -#define WM8915_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */ -#define WM8915_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */ -#define WM8915_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */ -#define WM8915_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */ -#define WM8915_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */ -#define WM8915_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */ - -/* - * R1539 (0x603) - DAC2 Mixer Volumes - */ -#define WM8915_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ -#define WM8915_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ -#define WM8915_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ -#define WM8915_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ -#define WM8915_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ -#define WM8915_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ - -/* - * R1540 (0x604) - DAC2 Left Mixer Routing - */ -#define WM8915_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ -#define WM8915_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ -#define WM8915_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ -#define WM8915_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ -#define WM8915_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ -#define WM8915_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ -#define WM8915_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ -#define WM8915_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ -#define WM8915_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */ -#define WM8915_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */ -#define WM8915_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */ -#define WM8915_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */ -#define WM8915_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */ -#define WM8915_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */ -#define WM8915_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */ -#define WM8915_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */ - -/* - * R1541 (0x605) - DAC2 Right Mixer Routing - */ -#define WM8915_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ -#define WM8915_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ -#define WM8915_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ -#define WM8915_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ -#define WM8915_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ -#define WM8915_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ -#define WM8915_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ -#define WM8915_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ -#define WM8915_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */ -#define WM8915_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */ -#define WM8915_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */ -#define WM8915_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */ -#define WM8915_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */ -#define WM8915_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */ -#define WM8915_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */ -#define WM8915_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */ - -/* - * R1542 (0x606) - DSP1 TX Left Mixer Routing - */ -#define WM8915_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */ -#define WM8915_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */ -#define WM8915_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */ -#define WM8915_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */ -#define WM8915_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */ -#define WM8915_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */ -#define WM8915_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */ -#define WM8915_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */ - -/* - * R1543 (0x607) - DSP1 TX Right Mixer Routing - */ -#define WM8915_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */ -#define WM8915_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */ -#define WM8915_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */ -#define WM8915_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */ -#define WM8915_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */ -#define WM8915_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */ -#define WM8915_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */ -#define WM8915_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */ - -/* - * R1544 (0x608) - DSP2 TX Left Mixer Routing - */ -#define WM8915_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */ -#define WM8915_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */ -#define WM8915_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */ -#define WM8915_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */ -#define WM8915_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */ -#define WM8915_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */ -#define WM8915_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */ -#define WM8915_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */ - -/* - * R1545 (0x609) - DSP2 TX Right Mixer Routing - */ -#define WM8915_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */ -#define WM8915_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */ -#define WM8915_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */ -#define WM8915_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */ -#define WM8915_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */ -#define WM8915_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */ -#define WM8915_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */ -#define WM8915_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */ - -/* - * R1546 (0x60A) - DSP TX Mixer Select - */ -#define WM8915_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */ -#define WM8915_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */ -#define WM8915_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */ -#define WM8915_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */ - -/* - * R1552 (0x610) - DAC Softmute - */ -#define WM8915_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ -#define WM8915_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ -#define WM8915_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ -#define WM8915_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ -#define WM8915_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ -#define WM8915_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ -#define WM8915_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ -#define WM8915_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ - -/* - * R1568 (0x620) - Oversampling - */ -#define WM8915_SPK_OSR128 0x0008 /* SPK_OSR128 */ -#define WM8915_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */ -#define WM8915_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */ -#define WM8915_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */ -#define WM8915_DMIC_OSR64 0x0004 /* DMIC_OSR64 */ -#define WM8915_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */ -#define WM8915_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */ -#define WM8915_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */ -#define WM8915_ADC_OSR128 0x0002 /* ADC_OSR128 */ -#define WM8915_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ -#define WM8915_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ -#define WM8915_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ -#define WM8915_DAC_OSR128 0x0001 /* DAC_OSR128 */ -#define WM8915_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ -#define WM8915_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ -#define WM8915_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ - -/* - * R1569 (0x621) - Sidetone - */ -#define WM8915_ST_LPF 0x1000 /* ST_LPF */ -#define WM8915_ST_LPF_MASK 0x1000 /* ST_LPF */ -#define WM8915_ST_LPF_SHIFT 12 /* ST_LPF */ -#define WM8915_ST_LPF_WIDTH 1 /* ST_LPF */ -#define WM8915_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ -#define WM8915_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ -#define WM8915_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ -#define WM8915_ST_HPF 0x0040 /* ST_HPF */ -#define WM8915_ST_HPF_MASK 0x0040 /* ST_HPF */ -#define WM8915_ST_HPF_SHIFT 6 /* ST_HPF */ -#define WM8915_ST_HPF_WIDTH 1 /* ST_HPF */ -#define WM8915_STR_SEL 0x0002 /* STR_SEL */ -#define WM8915_STR_SEL_MASK 0x0002 /* STR_SEL */ -#define WM8915_STR_SEL_SHIFT 1 /* STR_SEL */ -#define WM8915_STR_SEL_WIDTH 1 /* STR_SEL */ -#define WM8915_STL_SEL 0x0001 /* STL_SEL */ -#define WM8915_STL_SEL_MASK 0x0001 /* STL_SEL */ -#define WM8915_STL_SEL_SHIFT 0 /* STL_SEL */ -#define WM8915_STL_SEL_WIDTH 1 /* STL_SEL */ - -/* - * R1792 (0x700) - GPIO 1 - */ -#define WM8915_GP1_DIR 0x8000 /* GP1_DIR */ -#define WM8915_GP1_DIR_MASK 0x8000 /* GP1_DIR */ -#define WM8915_GP1_DIR_SHIFT 15 /* GP1_DIR */ -#define WM8915_GP1_DIR_WIDTH 1 /* GP1_DIR */ -#define WM8915_GP1_PU 0x4000 /* GP1_PU */ -#define WM8915_GP1_PU_MASK 0x4000 /* GP1_PU */ -#define WM8915_GP1_PU_SHIFT 14 /* GP1_PU */ -#define WM8915_GP1_PU_WIDTH 1 /* GP1_PU */ -#define WM8915_GP1_PD 0x2000 /* GP1_PD */ -#define WM8915_GP1_PD_MASK 0x2000 /* GP1_PD */ -#define WM8915_GP1_PD_SHIFT 13 /* GP1_PD */ -#define WM8915_GP1_PD_WIDTH 1 /* GP1_PD */ -#define WM8915_GP1_POL 0x0400 /* GP1_POL */ -#define WM8915_GP1_POL_MASK 0x0400 /* GP1_POL */ -#define WM8915_GP1_POL_SHIFT 10 /* GP1_POL */ -#define WM8915_GP1_POL_WIDTH 1 /* GP1_POL */ -#define WM8915_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ -#define WM8915_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ -#define WM8915_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ -#define WM8915_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ -#define WM8915_GP1_DB 0x0100 /* GP1_DB */ -#define WM8915_GP1_DB_MASK 0x0100 /* GP1_DB */ -#define WM8915_GP1_DB_SHIFT 8 /* GP1_DB */ -#define WM8915_GP1_DB_WIDTH 1 /* GP1_DB */ -#define WM8915_GP1_LVL 0x0040 /* GP1_LVL */ -#define WM8915_GP1_LVL_MASK 0x0040 /* GP1_LVL */ -#define WM8915_GP1_LVL_SHIFT 6 /* GP1_LVL */ -#define WM8915_GP1_LVL_WIDTH 1 /* GP1_LVL */ -#define WM8915_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */ -#define WM8915_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */ -#define WM8915_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */ - -/* - * R1793 (0x701) - GPIO 2 - */ -#define WM8915_GP2_DIR 0x8000 /* GP2_DIR */ -#define WM8915_GP2_DIR_MASK 0x8000 /* GP2_DIR */ -#define WM8915_GP2_DIR_SHIFT 15 /* GP2_DIR */ -#define WM8915_GP2_DIR_WIDTH 1 /* GP2_DIR */ -#define WM8915_GP2_PU 0x4000 /* GP2_PU */ -#define WM8915_GP2_PU_MASK 0x4000 /* GP2_PU */ -#define WM8915_GP2_PU_SHIFT 14 /* GP2_PU */ -#define WM8915_GP2_PU_WIDTH 1 /* GP2_PU */ -#define WM8915_GP2_PD 0x2000 /* GP2_PD */ -#define WM8915_GP2_PD_MASK 0x2000 /* GP2_PD */ -#define WM8915_GP2_PD_SHIFT 13 /* GP2_PD */ -#define WM8915_GP2_PD_WIDTH 1 /* GP2_PD */ -#define WM8915_GP2_POL 0x0400 /* GP2_POL */ -#define WM8915_GP2_POL_MASK 0x0400 /* GP2_POL */ -#define WM8915_GP2_POL_SHIFT 10 /* GP2_POL */ -#define WM8915_GP2_POL_WIDTH 1 /* GP2_POL */ -#define WM8915_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ -#define WM8915_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ -#define WM8915_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ -#define WM8915_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ -#define WM8915_GP2_DB 0x0100 /* GP2_DB */ -#define WM8915_GP2_DB_MASK 0x0100 /* GP2_DB */ -#define WM8915_GP2_DB_SHIFT 8 /* GP2_DB */ -#define WM8915_GP2_DB_WIDTH 1 /* GP2_DB */ -#define WM8915_GP2_LVL 0x0040 /* GP2_LVL */ -#define WM8915_GP2_LVL_MASK 0x0040 /* GP2_LVL */ -#define WM8915_GP2_LVL_SHIFT 6 /* GP2_LVL */ -#define WM8915_GP2_LVL_WIDTH 1 /* GP2_LVL */ -#define WM8915_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */ -#define WM8915_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */ -#define WM8915_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */ - -/* - * R1794 (0x702) - GPIO 3 - */ -#define WM8915_GP3_DIR 0x8000 /* GP3_DIR */ -#define WM8915_GP3_DIR_MASK 0x8000 /* GP3_DIR */ -#define WM8915_GP3_DIR_SHIFT 15 /* GP3_DIR */ -#define WM8915_GP3_DIR_WIDTH 1 /* GP3_DIR */ -#define WM8915_GP3_PU 0x4000 /* GP3_PU */ -#define WM8915_GP3_PU_MASK 0x4000 /* GP3_PU */ -#define WM8915_GP3_PU_SHIFT 14 /* GP3_PU */ -#define WM8915_GP3_PU_WIDTH 1 /* GP3_PU */ -#define WM8915_GP3_PD 0x2000 /* GP3_PD */ -#define WM8915_GP3_PD_MASK 0x2000 /* GP3_PD */ -#define WM8915_GP3_PD_SHIFT 13 /* GP3_PD */ -#define WM8915_GP3_PD_WIDTH 1 /* GP3_PD */ -#define WM8915_GP3_POL 0x0400 /* GP3_POL */ -#define WM8915_GP3_POL_MASK 0x0400 /* GP3_POL */ -#define WM8915_GP3_POL_SHIFT 10 /* GP3_POL */ -#define WM8915_GP3_POL_WIDTH 1 /* GP3_POL */ -#define WM8915_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ -#define WM8915_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ -#define WM8915_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ -#define WM8915_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ -#define WM8915_GP3_DB 0x0100 /* GP3_DB */ -#define WM8915_GP3_DB_MASK 0x0100 /* GP3_DB */ -#define WM8915_GP3_DB_SHIFT 8 /* GP3_DB */ -#define WM8915_GP3_DB_WIDTH 1 /* GP3_DB */ -#define WM8915_GP3_LVL 0x0040 /* GP3_LVL */ -#define WM8915_GP3_LVL_MASK 0x0040 /* GP3_LVL */ -#define WM8915_GP3_LVL_SHIFT 6 /* GP3_LVL */ -#define WM8915_GP3_LVL_WIDTH 1 /* GP3_LVL */ -#define WM8915_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */ -#define WM8915_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */ -#define WM8915_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */ - -/* - * R1795 (0x703) - GPIO 4 - */ -#define WM8915_GP4_DIR 0x8000 /* GP4_DIR */ -#define WM8915_GP4_DIR_MASK 0x8000 /* GP4_DIR */ -#define WM8915_GP4_DIR_SHIFT 15 /* GP4_DIR */ -#define WM8915_GP4_DIR_WIDTH 1 /* GP4_DIR */ -#define WM8915_GP4_PU 0x4000 /* GP4_PU */ -#define WM8915_GP4_PU_MASK 0x4000 /* GP4_PU */ -#define WM8915_GP4_PU_SHIFT 14 /* GP4_PU */ -#define WM8915_GP4_PU_WIDTH 1 /* GP4_PU */ -#define WM8915_GP4_PD 0x2000 /* GP4_PD */ -#define WM8915_GP4_PD_MASK 0x2000 /* GP4_PD */ -#define WM8915_GP4_PD_SHIFT 13 /* GP4_PD */ -#define WM8915_GP4_PD_WIDTH 1 /* GP4_PD */ -#define WM8915_GP4_POL 0x0400 /* GP4_POL */ -#define WM8915_GP4_POL_MASK 0x0400 /* GP4_POL */ -#define WM8915_GP4_POL_SHIFT 10 /* GP4_POL */ -#define WM8915_GP4_POL_WIDTH 1 /* GP4_POL */ -#define WM8915_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ -#define WM8915_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ -#define WM8915_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ -#define WM8915_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ -#define WM8915_GP4_DB 0x0100 /* GP4_DB */ -#define WM8915_GP4_DB_MASK 0x0100 /* GP4_DB */ -#define WM8915_GP4_DB_SHIFT 8 /* GP4_DB */ -#define WM8915_GP4_DB_WIDTH 1 /* GP4_DB */ -#define WM8915_GP4_LVL 0x0040 /* GP4_LVL */ -#define WM8915_GP4_LVL_MASK 0x0040 /* GP4_LVL */ -#define WM8915_GP4_LVL_SHIFT 6 /* GP4_LVL */ -#define WM8915_GP4_LVL_WIDTH 1 /* GP4_LVL */ -#define WM8915_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */ -#define WM8915_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */ -#define WM8915_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */ - -/* - * R1796 (0x704) - GPIO 5 - */ -#define WM8915_GP5_DIR 0x8000 /* GP5_DIR */ -#define WM8915_GP5_DIR_MASK 0x8000 /* GP5_DIR */ -#define WM8915_GP5_DIR_SHIFT 15 /* GP5_DIR */ -#define WM8915_GP5_DIR_WIDTH 1 /* GP5_DIR */ -#define WM8915_GP5_PU 0x4000 /* GP5_PU */ -#define WM8915_GP5_PU_MASK 0x4000 /* GP5_PU */ -#define WM8915_GP5_PU_SHIFT 14 /* GP5_PU */ -#define WM8915_GP5_PU_WIDTH 1 /* GP5_PU */ -#define WM8915_GP5_PD 0x2000 /* GP5_PD */ -#define WM8915_GP5_PD_MASK 0x2000 /* GP5_PD */ -#define WM8915_GP5_PD_SHIFT 13 /* GP5_PD */ -#define WM8915_GP5_PD_WIDTH 1 /* GP5_PD */ -#define WM8915_GP5_POL 0x0400 /* GP5_POL */ -#define WM8915_GP5_POL_MASK 0x0400 /* GP5_POL */ -#define WM8915_GP5_POL_SHIFT 10 /* GP5_POL */ -#define WM8915_GP5_POL_WIDTH 1 /* GP5_POL */ -#define WM8915_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ -#define WM8915_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ -#define WM8915_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ -#define WM8915_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ -#define WM8915_GP5_DB 0x0100 /* GP5_DB */ -#define WM8915_GP5_DB_MASK 0x0100 /* GP5_DB */ -#define WM8915_GP5_DB_SHIFT 8 /* GP5_DB */ -#define WM8915_GP5_DB_WIDTH 1 /* GP5_DB */ -#define WM8915_GP5_LVL 0x0040 /* GP5_LVL */ -#define WM8915_GP5_LVL_MASK 0x0040 /* GP5_LVL */ -#define WM8915_GP5_LVL_SHIFT 6 /* GP5_LVL */ -#define WM8915_GP5_LVL_WIDTH 1 /* GP5_LVL */ -#define WM8915_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */ -#define WM8915_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */ -#define WM8915_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */ - -/* - * R1824 (0x720) - Pull Control (1) - */ -#define WM8915_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ -#define WM8915_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ -#define WM8915_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ -#define WM8915_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ -#define WM8915_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ -#define WM8915_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ -#define WM8915_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ -#define WM8915_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ -#define WM8915_MCLK2_PU 0x0200 /* MCLK2_PU */ -#define WM8915_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ -#define WM8915_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ -#define WM8915_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ -#define WM8915_MCLK2_PD 0x0100 /* MCLK2_PD */ -#define WM8915_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ -#define WM8915_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ -#define WM8915_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ -#define WM8915_MCLK1_PU 0x0080 /* MCLK1_PU */ -#define WM8915_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ -#define WM8915_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ -#define WM8915_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ -#define WM8915_MCLK1_PD 0x0040 /* MCLK1_PD */ -#define WM8915_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ -#define WM8915_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ -#define WM8915_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ -#define WM8915_DACDAT1_PU 0x0020 /* DACDAT1_PU */ -#define WM8915_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ -#define WM8915_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ -#define WM8915_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ -#define WM8915_DACDAT1_PD 0x0010 /* DACDAT1_PD */ -#define WM8915_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ -#define WM8915_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ -#define WM8915_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ -#define WM8915_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ -#define WM8915_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ -#define WM8915_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ -#define WM8915_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ -#define WM8915_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ -#define WM8915_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ -#define WM8915_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ -#define WM8915_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ -#define WM8915_BCLK1_PU 0x0002 /* BCLK1_PU */ -#define WM8915_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ -#define WM8915_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ -#define WM8915_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ -#define WM8915_BCLK1_PD 0x0001 /* BCLK1_PD */ -#define WM8915_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ -#define WM8915_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ -#define WM8915_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ - -/* - * R1825 (0x721) - Pull Control (2) - */ -#define WM8915_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */ -#define WM8915_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */ -#define WM8915_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */ -#define WM8915_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ -#define WM8915_ADDR_PD 0x0040 /* ADDR_PD */ -#define WM8915_ADDR_PD_MASK 0x0040 /* ADDR_PD */ -#define WM8915_ADDR_PD_SHIFT 6 /* ADDR_PD */ -#define WM8915_ADDR_PD_WIDTH 1 /* ADDR_PD */ -#define WM8915_DACDAT2_PU 0x0020 /* DACDAT2_PU */ -#define WM8915_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */ -#define WM8915_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */ -#define WM8915_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */ -#define WM8915_DACDAT2_PD 0x0010 /* DACDAT2_PD */ -#define WM8915_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */ -#define WM8915_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */ -#define WM8915_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */ -#define WM8915_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */ -#define WM8915_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */ -#define WM8915_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */ -#define WM8915_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */ -#define WM8915_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */ -#define WM8915_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */ -#define WM8915_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */ -#define WM8915_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */ -#define WM8915_BCLK2_PU 0x0002 /* BCLK2_PU */ -#define WM8915_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */ -#define WM8915_BCLK2_PU_SHIFT 1 /* BCLK2_PU */ -#define WM8915_BCLK2_PU_WIDTH 1 /* BCLK2_PU */ -#define WM8915_BCLK2_PD 0x0001 /* BCLK2_PD */ -#define WM8915_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */ -#define WM8915_BCLK2_PD_SHIFT 0 /* BCLK2_PD */ -#define WM8915_BCLK2_PD_WIDTH 1 /* BCLK2_PD */ - -/* - * R1840 (0x730) - Interrupt Status 1 - */ -#define WM8915_GP5_EINT 0x0010 /* GP5_EINT */ -#define WM8915_GP5_EINT_MASK 0x0010 /* GP5_EINT */ -#define WM8915_GP5_EINT_SHIFT 4 /* GP5_EINT */ -#define WM8915_GP5_EINT_WIDTH 1 /* GP5_EINT */ -#define WM8915_GP4_EINT 0x0008 /* GP4_EINT */ -#define WM8915_GP4_EINT_MASK 0x0008 /* GP4_EINT */ -#define WM8915_GP4_EINT_SHIFT 3 /* GP4_EINT */ -#define WM8915_GP4_EINT_WIDTH 1 /* GP4_EINT */ -#define WM8915_GP3_EINT 0x0004 /* GP3_EINT */ -#define WM8915_GP3_EINT_MASK 0x0004 /* GP3_EINT */ -#define WM8915_GP3_EINT_SHIFT 2 /* GP3_EINT */ -#define WM8915_GP3_EINT_WIDTH 1 /* GP3_EINT */ -#define WM8915_GP2_EINT 0x0002 /* GP2_EINT */ -#define WM8915_GP2_EINT_MASK 0x0002 /* GP2_EINT */ -#define WM8915_GP2_EINT_SHIFT 1 /* GP2_EINT */ -#define WM8915_GP2_EINT_WIDTH 1 /* GP2_EINT */ -#define WM8915_GP1_EINT 0x0001 /* GP1_EINT */ -#define WM8915_GP1_EINT_MASK 0x0001 /* GP1_EINT */ -#define WM8915_GP1_EINT_SHIFT 0 /* GP1_EINT */ -#define WM8915_GP1_EINT_WIDTH 1 /* GP1_EINT */ - -/* - * R1841 (0x731) - Interrupt Status 2 - */ -#define WM8915_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ -#define WM8915_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ -#define WM8915_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ -#define WM8915_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ -#define WM8915_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ -#define WM8915_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ -#define WM8915_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ -#define WM8915_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ -#define WM8915_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ -#define WM8915_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ -#define WM8915_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ -#define WM8915_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ -#define WM8915_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ -#define WM8915_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ -#define WM8915_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ -#define WM8915_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ -#define WM8915_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */ -#define WM8915_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */ -#define WM8915_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */ -#define WM8915_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */ -#define WM8915_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */ -#define WM8915_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */ -#define WM8915_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */ -#define WM8915_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */ -#define WM8915_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */ -#define WM8915_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */ -#define WM8915_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */ -#define WM8915_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */ -#define WM8915_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ -#define WM8915_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ -#define WM8915_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ -#define WM8915_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ -#define WM8915_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ -#define WM8915_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ -#define WM8915_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ -#define WM8915_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ -#define WM8915_MICD_EINT 0x0001 /* MICD_EINT */ -#define WM8915_MICD_EINT_MASK 0x0001 /* MICD_EINT */ -#define WM8915_MICD_EINT_SHIFT 0 /* MICD_EINT */ -#define WM8915_MICD_EINT_WIDTH 1 /* MICD_EINT */ - -/* - * R1842 (0x732) - Interrupt Raw Status 2 - */ -#define WM8915_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ -#define WM8915_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ -#define WM8915_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ -#define WM8915_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ -#define WM8915_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ -#define WM8915_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ -#define WM8915_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ -#define WM8915_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ -#define WM8915_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ -#define WM8915_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ -#define WM8915_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ -#define WM8915_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ -#define WM8915_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ -#define WM8915_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ -#define WM8915_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ -#define WM8915_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ -#define WM8915_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */ -#define WM8915_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */ -#define WM8915_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */ -#define WM8915_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */ -#define WM8915_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */ -#define WM8915_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */ -#define WM8915_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */ -#define WM8915_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */ -#define WM8915_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */ -#define WM8915_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */ -#define WM8915_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */ -#define WM8915_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ - -/* - * R1848 (0x738) - Interrupt Status 1 Mask - */ -#define WM8915_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ -#define WM8915_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ -#define WM8915_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ -#define WM8915_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ -#define WM8915_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ -#define WM8915_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ -#define WM8915_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ -#define WM8915_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ -#define WM8915_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ -#define WM8915_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ -#define WM8915_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ -#define WM8915_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ -#define WM8915_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ -#define WM8915_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ -#define WM8915_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ -#define WM8915_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ -#define WM8915_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ -#define WM8915_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ -#define WM8915_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ -#define WM8915_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ - -/* - * R1849 (0x739) - Interrupt Status 2 Mask - */ -#define WM8915_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ -#define WM8915_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ -#define WM8915_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ -#define WM8915_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ -#define WM8915_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ -#define WM8915_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ -#define WM8915_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ -#define WM8915_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ -#define WM8915_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ -#define WM8915_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ -#define WM8915_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ -#define WM8915_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ -#define WM8915_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ -#define WM8915_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ -#define WM8915_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ -#define WM8915_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ -#define WM8915_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */ -#define WM8915_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */ -#define WM8915_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ -#define WM8915_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ -#define WM8915_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */ -#define WM8915_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */ -#define WM8915_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ -#define WM8915_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ -#define WM8915_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ -#define WM8915_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ -#define WM8915_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ -#define WM8915_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ -#define WM8915_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ -#define WM8915_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ -#define WM8915_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ -#define WM8915_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ -#define WM8915_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ -#define WM8915_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ - -/* - * R1856 (0x740) - Interrupt Control - */ -#define WM8915_IM_IRQ 0x0001 /* IM_IRQ */ -#define WM8915_IM_IRQ_MASK 0x0001 /* IM_IRQ */ -#define WM8915_IM_IRQ_SHIFT 0 /* IM_IRQ */ -#define WM8915_IM_IRQ_WIDTH 1 /* IM_IRQ */ - -/* - * R2048 (0x800) - Left PDM Speaker - */ -#define WM8915_SPKL_ENA 0x0010 /* SPKL_ENA */ -#define WM8915_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */ -#define WM8915_SPKL_ENA_SHIFT 4 /* SPKL_ENA */ -#define WM8915_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ -#define WM8915_SPKL_MUTE 0x0008 /* SPKL_MUTE */ -#define WM8915_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */ -#define WM8915_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */ -#define WM8915_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ -#define WM8915_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */ -#define WM8915_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */ -#define WM8915_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */ -#define WM8915_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */ -#define WM8915_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */ -#define WM8915_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */ -#define WM8915_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */ - -/* - * R2049 (0x801) - Right PDM Speaker - */ -#define WM8915_SPKR_ENA 0x0010 /* SPKR_ENA */ -#define WM8915_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */ -#define WM8915_SPKR_ENA_SHIFT 4 /* SPKR_ENA */ -#define WM8915_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ -#define WM8915_SPKR_MUTE 0x0008 /* SPKR_MUTE */ -#define WM8915_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */ -#define WM8915_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */ -#define WM8915_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ -#define WM8915_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */ -#define WM8915_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */ -#define WM8915_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */ -#define WM8915_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */ -#define WM8915_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */ -#define WM8915_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */ -#define WM8915_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */ - -/* - * R2050 (0x802) - PDM Speaker Mute Sequence - */ -#define WM8915_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */ -#define WM8915_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */ -#define WM8915_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */ -#define WM8915_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */ -#define WM8915_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */ -#define WM8915_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */ -#define WM8915_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */ - -/* - * R2051 (0x803) - PDM Speaker Volume - */ -#define WM8915_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */ -#define WM8915_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */ -#define WM8915_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */ -#define WM8915_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */ -#define WM8915_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */ -#define WM8915_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */ - -#endif diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c new file mode 100644 index 000000000000..ab8e9d1aaff0 --- /dev/null +++ b/sound/soc/codecs/wm8996.c @@ -0,0 +1,2994 @@ +/* + * wm8996.c - WM8996 audio codec interface + * + * Copyright 2011 Wolfson Microelectronics PLC. + * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/gcd.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/regulator/consumer.h> +#include <linux/slab.h> +#include <linux/workqueue.h> +#include <sound/core.h> +#include <sound/jack.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <trace/events/asoc.h> + +#include <sound/wm8996.h> +#include "wm8996.h" + +#define WM8996_AIFS 2 + +#define HPOUT1L 1 +#define HPOUT1R 2 +#define HPOUT2L 4 +#define HPOUT2R 8 + +#define WM8996_NUM_SUPPLIES 4 +static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { + "DBVDD", + "AVDD1", + "AVDD2", + "CPVDD", +}; + +struct wm8996_priv { + struct snd_soc_codec *codec; + + int ldo1ena; + + int sysclk; + int sysclk_src; + + int fll_src; + int fll_fref; + int fll_fout; + + struct completion fll_lock; + + u16 dcs_pending; + struct completion dcs_done; + + u16 hpout_ena; + u16 hpout_pending; + + struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; + struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; + + struct wm8996_pdata pdata; + + int rx_rate[WM8996_AIFS]; + int bclk_rate[WM8996_AIFS]; + + /* Platform dependant ReTune mobile configuration */ + int num_retune_mobile_texts; + const char **retune_mobile_texts; + int retune_mobile_cfg[2]; + struct soc_enum retune_mobile_enum; + + struct snd_soc_jack *jack; + bool detecting; + bool jack_mic; + wm8996_polarity_fn polarity_cb; + +#ifdef CONFIG_GPIOLIB + struct gpio_chip gpio_chip; +#endif +}; + +/* We can't use the same notifier block for more than one supply and + * there's no way I can see to get from a callback to the caller + * except container_of(). + */ +#define WM8996_REGULATOR_EVENT(n) \ +static int wm8996_regulator_event_##n(struct notifier_block *nb, \ + unsigned long event, void *data) \ +{ \ + struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ + disable_nb[n]); \ + if (event & REGULATOR_EVENT_DISABLE) { \ + wm8996->codec->cache_sync = 1; \ + } \ + return 0; \ +} + +WM8996_REGULATOR_EVENT(0) +WM8996_REGULATOR_EVENT(1) +WM8996_REGULATOR_EVENT(2) +WM8996_REGULATOR_EVENT(3) + +static const u16 wm8996_reg[WM8996_MAX_REGISTER] = { + [WM8996_SOFTWARE_RESET] = 0x8996, + [WM8996_POWER_MANAGEMENT_7] = 0x10, + [WM8996_DAC1_HPOUT1_VOLUME] = 0x88, + [WM8996_DAC2_HPOUT2_VOLUME] = 0x88, + [WM8996_DAC1_LEFT_VOLUME] = 0x2c0, + [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0, + [WM8996_DAC2_LEFT_VOLUME] = 0x2c0, + [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0, + [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80, + [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80, + [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80, + [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80, + [WM8996_MICBIAS_1] = 0x39, + [WM8996_MICBIAS_2] = 0x39, + [WM8996_LDO_1] = 0x3, + [WM8996_LDO_2] = 0x13, + [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4, + [WM8996_HEADPHONE_DETECT_1] = 0x20, + [WM8996_MIC_DETECT_1] = 0x7600, + [WM8996_MIC_DETECT_2] = 0xbf, + [WM8996_CHARGE_PUMP_1] = 0x1f25, + [WM8996_CHARGE_PUMP_2] = 0xab19, + [WM8996_DC_SERVO_5] = 0x2a2a, + [WM8996_CONTROL_INTERFACE_1] = 0x8004, + [WM8996_CLOCKING_1] = 0x10, + [WM8996_AIF_RATE] = 0x83, + [WM8996_FLL_CONTROL_4] = 0x5dc0, + [WM8996_FLL_CONTROL_5] = 0xc84, + [WM8996_FLL_EFS_2] = 0x2, + [WM8996_AIF1_TX_LRCLK_1] = 0x80, + [WM8996_AIF1_TX_LRCLK_2] = 0x8, + [WM8996_AIF1_RX_LRCLK_1] = 0x80, + [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818, + [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818, + [WM8996_AIF1TX_TEST] = 0x7, + [WM8996_AIF2_TX_LRCLK_1] = 0x80, + [WM8996_AIF2_TX_LRCLK_2] = 0x8, + [WM8996_AIF2_RX_LRCLK_1] = 0x80, + [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818, + [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818, + [WM8996_AIF2TX_TEST] = 0x1, + [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0, + [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0, + [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0, + [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0, + [WM8996_DSP1_TX_FILTERS] = 0x2000, + [WM8996_DSP1_RX_FILTERS_1] = 0x200, + [WM8996_DSP1_RX_FILTERS_2] = 0x10, + [WM8996_DSP1_DRC_1] = 0x98, + [WM8996_DSP1_DRC_2] = 0x845, + [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318, + [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300, + [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca, + [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400, + [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8, + [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5, + [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145, + [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75, + [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5, + [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58, + [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373, + [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54, + [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558, + [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e, + [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829, + [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad, + [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103, + [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564, + [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559, + [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000, + [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0, + [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0, + [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0, + [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0, + [WM8996_DSP2_TX_FILTERS] = 0x2000, + [WM8996_DSP2_RX_FILTERS_1] = 0x200, + [WM8996_DSP2_RX_FILTERS_2] = 0x10, + [WM8996_DSP2_DRC_1] = 0x98, + [WM8996_DSP2_DRC_2] = 0x845, + [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318, + [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300, + [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca, + [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400, + [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8, + [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5, + [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145, + [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75, + [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5, + [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58, + [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373, + [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54, + [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558, + [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e, + [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829, + [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad, + [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103, + [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564, + [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559, + [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000, + [WM8996_OVERSAMPLING] = 0xd, + [WM8996_SIDETONE] = 0x1040, + [WM8996_GPIO_1] = 0xa101, + [WM8996_GPIO_2] = 0xa101, + [WM8996_GPIO_3] = 0xa101, + [WM8996_GPIO_4] = 0xa101, + [WM8996_GPIO_5] = 0xa101, + [WM8996_PULL_CONTROL_2] = 0x140, + [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f, + [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf, + [WM8996_RIGHT_PDM_SPEAKER] = 0x1, + [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69, + [WM8996_PDM_SPEAKER_VOLUME] = 0x66, + [WM8996_WRITE_SEQUENCER_0] = 0x1, + [WM8996_WRITE_SEQUENCER_1] = 0x1, + [WM8996_WRITE_SEQUENCER_3] = 0x6, + [WM8996_WRITE_SEQUENCER_4] = 0x40, + [WM8996_WRITE_SEQUENCER_5] = 0x1, + [WM8996_WRITE_SEQUENCER_6] = 0xf, + [WM8996_WRITE_SEQUENCER_7] = 0x6, + [WM8996_WRITE_SEQUENCER_8] = 0x1, + [WM8996_WRITE_SEQUENCER_9] = 0x3, + [WM8996_WRITE_SEQUENCER_10] = 0x104, + [WM8996_WRITE_SEQUENCER_12] = 0x60, + [WM8996_WRITE_SEQUENCER_13] = 0x11, + [WM8996_WRITE_SEQUENCER_14] = 0x401, + [WM8996_WRITE_SEQUENCER_16] = 0x50, + [WM8996_WRITE_SEQUENCER_17] = 0x3, + [WM8996_WRITE_SEQUENCER_18] = 0x100, + [WM8996_WRITE_SEQUENCER_20] = 0x51, + [WM8996_WRITE_SEQUENCER_21] = 0x3, + [WM8996_WRITE_SEQUENCER_22] = 0x104, + [WM8996_WRITE_SEQUENCER_23] = 0xa, + [WM8996_WRITE_SEQUENCER_24] = 0x60, + [WM8996_WRITE_SEQUENCER_25] = 0x3b, + [WM8996_WRITE_SEQUENCER_26] = 0x502, + [WM8996_WRITE_SEQUENCER_27] = 0x100, + [WM8996_WRITE_SEQUENCER_28] = 0x2fff, + [WM8996_WRITE_SEQUENCER_32] = 0x2fff, + [WM8996_WRITE_SEQUENCER_36] = 0x2fff, + [WM8996_WRITE_SEQUENCER_40] = 0x2fff, + [WM8996_WRITE_SEQUENCER_44] = 0x2fff, + [WM8996_WRITE_SEQUENCER_48] = 0x2fff, + [WM8996_WRITE_SEQUENCER_52] = 0x2fff, + [WM8996_WRITE_SEQUENCER_56] = 0x2fff, + [WM8996_WRITE_SEQUENCER_60] = 0x2fff, + [WM8996_WRITE_SEQUENCER_64] = 0x1, + [WM8996_WRITE_SEQUENCER_65] = 0x1, + [WM8996_WRITE_SEQUENCER_67] = 0x6, + [WM8996_WRITE_SEQUENCER_68] = 0x40, + [WM8996_WRITE_SEQUENCER_69] = 0x1, + [WM8996_WRITE_SEQUENCER_70] = 0xf, + [WM8996_WRITE_SEQUENCER_71] = 0x6, + [WM8996_WRITE_SEQUENCER_72] = 0x1, + [WM8996_WRITE_SEQUENCER_73] = 0x3, + [WM8996_WRITE_SEQUENCER_74] = 0x104, + [WM8996_WRITE_SEQUENCER_76] = 0x60, + [WM8996_WRITE_SEQUENCER_77] = 0x11, + [WM8996_WRITE_SEQUENCER_78] = 0x401, + [WM8996_WRITE_SEQUENCER_80] = 0x50, + [WM8996_WRITE_SEQUENCER_81] = 0x3, + [WM8996_WRITE_SEQUENCER_82] = 0x100, + [WM8996_WRITE_SEQUENCER_84] = 0x60, + [WM8996_WRITE_SEQUENCER_85] = 0x3b, + [WM8996_WRITE_SEQUENCER_86] = 0x502, + [WM8996_WRITE_SEQUENCER_87] = 0x100, + [WM8996_WRITE_SEQUENCER_88] = 0x2fff, + [WM8996_WRITE_SEQUENCER_92] = 0x2fff, + [WM8996_WRITE_SEQUENCER_96] = 0x2fff, + [WM8996_WRITE_SEQUENCER_100] = 0x2fff, + [WM8996_WRITE_SEQUENCER_104] = 0x2fff, + [WM8996_WRITE_SEQUENCER_108] = 0x2fff, + [WM8996_WRITE_SEQUENCER_112] = 0x2fff, + [WM8996_WRITE_SEQUENCER_116] = 0x2fff, + [WM8996_WRITE_SEQUENCER_120] = 0x2fff, + [WM8996_WRITE_SEQUENCER_124] = 0x2fff, + [WM8996_WRITE_SEQUENCER_128] = 0x1, + [WM8996_WRITE_SEQUENCER_129] = 0x1, + [WM8996_WRITE_SEQUENCER_131] = 0x6, + [WM8996_WRITE_SEQUENCER_132] = 0x40, + [WM8996_WRITE_SEQUENCER_133] = 0x1, + [WM8996_WRITE_SEQUENCER_134] = 0xf, + [WM8996_WRITE_SEQUENCER_135] = 0x6, + [WM8996_WRITE_SEQUENCER_136] = 0x1, + [WM8996_WRITE_SEQUENCER_137] = 0x3, + [WM8996_WRITE_SEQUENCER_138] = 0x106, + [WM8996_WRITE_SEQUENCER_140] = 0x61, + [WM8996_WRITE_SEQUENCER_141] = 0x11, + [WM8996_WRITE_SEQUENCER_142] = 0x401, + [WM8996_WRITE_SEQUENCER_144] = 0x50, + [WM8996_WRITE_SEQUENCER_145] = 0x3, + [WM8996_WRITE_SEQUENCER_146] = 0x102, + [WM8996_WRITE_SEQUENCER_148] = 0x51, + [WM8996_WRITE_SEQUENCER_149] = 0x3, + [WM8996_WRITE_SEQUENCER_150] = 0x106, + [WM8996_WRITE_SEQUENCER_151] = 0xa, + [WM8996_WRITE_SEQUENCER_152] = 0x61, + [WM8996_WRITE_SEQUENCER_153] = 0x3b, + [WM8996_WRITE_SEQUENCER_154] = 0x502, + [WM8996_WRITE_SEQUENCER_155] = 0x100, + [WM8996_WRITE_SEQUENCER_156] = 0x2fff, + [WM8996_WRITE_SEQUENCER_160] = 0x2fff, + [WM8996_WRITE_SEQUENCER_164] = 0x2fff, + [WM8996_WRITE_SEQUENCER_168] = 0x2fff, + [WM8996_WRITE_SEQUENCER_172] = 0x2fff, + [WM8996_WRITE_SEQUENCER_176] = 0x2fff, + [WM8996_WRITE_SEQUENCER_180] = 0x2fff, + [WM8996_WRITE_SEQUENCER_184] = 0x2fff, + [WM8996_WRITE_SEQUENCER_188] = 0x2fff, + [WM8996_WRITE_SEQUENCER_192] = 0x1, + [WM8996_WRITE_SEQUENCER_193] = 0x1, + [WM8996_WRITE_SEQUENCER_195] = 0x6, + [WM8996_WRITE_SEQUENCER_196] = 0x40, + [WM8996_WRITE_SEQUENCER_197] = 0x1, + [WM8996_WRITE_SEQUENCER_198] = 0xf, + [WM8996_WRITE_SEQUENCER_199] = 0x6, + [WM8996_WRITE_SEQUENCER_200] = 0x1, + [WM8996_WRITE_SEQUENCER_201] = 0x3, + [WM8996_WRITE_SEQUENCER_202] = 0x106, + [WM8996_WRITE_SEQUENCER_204] = 0x61, + [WM8996_WRITE_SEQUENCER_205] = 0x11, + [WM8996_WRITE_SEQUENCER_206] = 0x401, + [WM8996_WRITE_SEQUENCER_208] = 0x50, + [WM8996_WRITE_SEQUENCER_209] = 0x3, + [WM8996_WRITE_SEQUENCER_210] = 0x102, + [WM8996_WRITE_SEQUENCER_212] = 0x61, + [WM8996_WRITE_SEQUENCER_213] = 0x3b, + [WM8996_WRITE_SEQUENCER_214] = 0x502, + [WM8996_WRITE_SEQUENCER_215] = 0x100, + [WM8996_WRITE_SEQUENCER_216] = 0x2fff, + [WM8996_WRITE_SEQUENCER_220] = 0x2fff, + [WM8996_WRITE_SEQUENCER_224] = 0x2fff, + [WM8996_WRITE_SEQUENCER_228] = 0x2fff, + [WM8996_WRITE_SEQUENCER_232] = 0x2fff, + [WM8996_WRITE_SEQUENCER_236] = 0x2fff, + [WM8996_WRITE_SEQUENCER_240] = 0x2fff, + [WM8996_WRITE_SEQUENCER_244] = 0x2fff, + [WM8996_WRITE_SEQUENCER_248] = 0x2fff, + [WM8996_WRITE_SEQUENCER_252] = 0x2fff, + [WM8996_WRITE_SEQUENCER_256] = 0x60, + [WM8996_WRITE_SEQUENCER_258] = 0x601, + [WM8996_WRITE_SEQUENCER_260] = 0x50, + [WM8996_WRITE_SEQUENCER_262] = 0x100, + [WM8996_WRITE_SEQUENCER_264] = 0x1, + [WM8996_WRITE_SEQUENCER_266] = 0x104, + [WM8996_WRITE_SEQUENCER_267] = 0x100, + [WM8996_WRITE_SEQUENCER_268] = 0x2fff, + [WM8996_WRITE_SEQUENCER_272] = 0x2fff, + [WM8996_WRITE_SEQUENCER_276] = 0x2fff, + [WM8996_WRITE_SEQUENCER_280] = 0x2fff, + [WM8996_WRITE_SEQUENCER_284] = 0x2fff, + [WM8996_WRITE_SEQUENCER_288] = 0x2fff, + [WM8996_WRITE_SEQUENCER_292] = 0x2fff, + [WM8996_WRITE_SEQUENCER_296] = 0x2fff, + [WM8996_WRITE_SEQUENCER_300] = 0x2fff, + [WM8996_WRITE_SEQUENCER_304] = 0x2fff, + [WM8996_WRITE_SEQUENCER_308] = 0x2fff, + [WM8996_WRITE_SEQUENCER_312] = 0x2fff, + [WM8996_WRITE_SEQUENCER_316] = 0x2fff, + [WM8996_WRITE_SEQUENCER_320] = 0x61, + [WM8996_WRITE_SEQUENCER_322] = 0x601, + [WM8996_WRITE_SEQUENCER_324] = 0x50, + [WM8996_WRITE_SEQUENCER_326] = 0x102, + [WM8996_WRITE_SEQUENCER_328] = 0x1, + [WM8996_WRITE_SEQUENCER_330] = 0x106, + [WM8996_WRITE_SEQUENCER_331] = 0x100, + [WM8996_WRITE_SEQUENCER_332] = 0x2fff, + [WM8996_WRITE_SEQUENCER_336] = 0x2fff, + [WM8996_WRITE_SEQUENCER_340] = 0x2fff, + [WM8996_WRITE_SEQUENCER_344] = 0x2fff, + [WM8996_WRITE_SEQUENCER_348] = 0x2fff, + [WM8996_WRITE_SEQUENCER_352] = 0x2fff, + [WM8996_WRITE_SEQUENCER_356] = 0x2fff, + [WM8996_WRITE_SEQUENCER_360] = 0x2fff, + [WM8996_WRITE_SEQUENCER_364] = 0x2fff, + [WM8996_WRITE_SEQUENCER_368] = 0x2fff, + [WM8996_WRITE_SEQUENCER_372] = 0x2fff, + [WM8996_WRITE_SEQUENCER_376] = 0x2fff, + [WM8996_WRITE_SEQUENCER_380] = 0x2fff, + [WM8996_WRITE_SEQUENCER_384] = 0x60, + [WM8996_WRITE_SEQUENCER_386] = 0x601, + [WM8996_WRITE_SEQUENCER_388] = 0x61, + [WM8996_WRITE_SEQUENCER_390] = 0x601, + [WM8996_WRITE_SEQUENCER_392] = 0x50, + [WM8996_WRITE_SEQUENCER_394] = 0x300, + [WM8996_WRITE_SEQUENCER_396] = 0x1, + [WM8996_WRITE_SEQUENCER_398] = 0x304, + [WM8996_WRITE_SEQUENCER_400] = 0x40, + [WM8996_WRITE_SEQUENCER_402] = 0xf, + [WM8996_WRITE_SEQUENCER_404] = 0x1, + [WM8996_WRITE_SEQUENCER_407] = 0x100, +}; + +static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); +static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); +static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); +static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); +static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); +static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); +static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); + +static const char *sidetone_hpf_text[] = { + "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" +}; + +static const struct soc_enum sidetone_hpf = + SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 6, sidetone_hpf_text); + +static const char *hpf_mode_text[] = { + "HiFi", "Custom", "Voice" +}; + +static const struct soc_enum dsp1tx_hpf_mode = + SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text); + +static const struct soc_enum dsp2tx_hpf_mode = + SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text); + +static const char *hpf_cutoff_text[] = { + "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" +}; + +static const struct soc_enum dsp1tx_hpf_cutoff = + SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text); + +static const struct soc_enum dsp2tx_hpf_cutoff = + SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text); + +static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + struct wm8996_pdata *pdata = &wm8996->pdata; + int base, best, best_val, save, i, cfg, iface; + + if (!wm8996->num_retune_mobile_texts) + return; + + switch (block) { + case 0: + base = WM8996_DSP1_RX_EQ_GAINS_1; + if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & + WM8996_DSP1RX_SRC) + iface = 1; + else + iface = 0; + break; + case 1: + base = WM8996_DSP1_RX_EQ_GAINS_2; + if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & + WM8996_DSP2RX_SRC) + iface = 1; + else + iface = 0; + break; + default: + return; + } + + /* Find the version of the currently selected configuration + * with the nearest sample rate. */ + cfg = wm8996->retune_mobile_cfg[block]; + best = 0; + best_val = INT_MAX; + for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { + if (strcmp(pdata->retune_mobile_cfgs[i].name, + wm8996->retune_mobile_texts[cfg]) == 0 && + abs(pdata->retune_mobile_cfgs[i].rate + - wm8996->rx_rate[iface]) < best_val) { + best = i; + best_val = abs(pdata->retune_mobile_cfgs[i].rate + - wm8996->rx_rate[iface]); + } + } + + dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", + block, + pdata->retune_mobile_cfgs[best].name, + pdata->retune_mobile_cfgs[best].rate, + wm8996->rx_rate[iface]); + + /* The EQ will be disabled while reconfiguring it, remember the + * current configuration. + */ + save = snd_soc_read(codec, base); + save &= WM8996_DSP1RX_EQ_ENA; + + for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) + snd_soc_update_bits(codec, base + i, 0xffff, + pdata->retune_mobile_cfgs[best].regs[i]); + + snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save); +} + +/* Icky as hell but saves code duplication */ +static int wm8996_get_retune_mobile_block(const char *name) +{ + if (strcmp(name, "DSP1 EQ Mode") == 0) + return 0; + if (strcmp(name, "DSP2 EQ Mode") == 0) + return 1; + return -EINVAL; +} + +static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + struct wm8996_pdata *pdata = &wm8996->pdata; + int block = wm8996_get_retune_mobile_block(kcontrol->id.name); + int value = ucontrol->value.integer.value[0]; + + if (block < 0) + return block; + + if (value >= pdata->num_retune_mobile_cfgs) + return -EINVAL; + + wm8996->retune_mobile_cfg[block] = value; + + wm8996_set_retune_mobile(codec, block); + + return 0; +} + +static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int block = wm8996_get_retune_mobile_block(kcontrol->id.name); + + ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; + + return 0; +} + +static const struct snd_kcontrol_new wm8996_snd_controls[] = { +SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, + WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), +SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, + WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), + +SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, + 0, 5, 24, 0, sidetone_tlv), +SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, + 0, 5, 24, 0, sidetone_tlv), +SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), +SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), +SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), + +SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, + WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), +SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, + WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), + +SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, + 13, 1, 0), +SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), +SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), +SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), + +SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, + 13, 1, 0), +SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), +SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), +SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), + +SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, + WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), +SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), + +SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, + WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), +SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), + +SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, + WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), +SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, + WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), + +SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, + WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), +SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, + WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), + +SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), +SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), +SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), +SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), + +SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), +SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), + +SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, + 8, 0, out_digital_tlv), +SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, + 8, 0, out_digital_tlv), + +SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, + WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), +SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, + WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), + +SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, + WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), +SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, + WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), + +SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, + spk_tlv), +SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, + WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), +SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, + WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), + +SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), +SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), +}; + +static const struct snd_kcontrol_new wm8996_eq_controls[] = { +SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, + eq_tlv), + +SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, + eq_tlv), +SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, + eq_tlv), +}; + +static int cp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + switch (event) { + case SND_SOC_DAPM_POST_PMU: + msleep(5); + break; + default: + BUG(); + return -EINVAL; + } + + return 0; +} + +static int rmv_short_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); + + /* Record which outputs we enabled */ + switch (event) { + case SND_SOC_DAPM_PRE_PMD: + wm8996->hpout_pending &= ~w->shift; + break; + case SND_SOC_DAPM_PRE_PMU: + wm8996->hpout_pending |= w->shift; + break; + default: + BUG(); + return -EINVAL; + } + + return 0; +} + +static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) +{ + struct i2c_client *i2c = to_i2c_client(codec->dev); + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int i, ret; + unsigned long timeout = 200; + + snd_soc_write(codec, WM8996_DC_SERVO_2, mask); + + /* Use the interrupt if possible */ + do { + if (i2c->irq) { + timeout = wait_for_completion_timeout(&wm8996->dcs_done, + msecs_to_jiffies(200)); + if (timeout == 0) + dev_err(codec->dev, "DC servo timed out\n"); + + } else { + msleep(1); + if (--i) { + timeout = 0; + break; + } + } + + ret = snd_soc_read(codec, WM8996_DC_SERVO_2); + dev_dbg(codec->dev, "DC servo state: %x\n", ret); + } while (ret & mask); + + if (timeout == 0) + dev_err(codec->dev, "DC servo timed out for %x\n", mask); + else + dev_dbg(codec->dev, "DC servo complete for %x\n", mask); +} + +static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm, + enum snd_soc_dapm_type event, int subseq) +{ + struct snd_soc_codec *codec = container_of(dapm, + struct snd_soc_codec, dapm); + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + u16 val, mask; + + /* Complete any pending DC servo starts */ + if (wm8996->dcs_pending) { + dev_dbg(codec->dev, "Starting DC servo for %x\n", + wm8996->dcs_pending); + + /* Trigger a startup sequence */ + wait_for_dc_servo(codec, wm8996->dcs_pending + << WM8996_DCS_TRIG_STARTUP_0_SHIFT); + + wm8996->dcs_pending = 0; + } + + if (wm8996->hpout_pending != wm8996->hpout_ena) { + dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", + wm8996->hpout_ena, wm8996->hpout_pending); + + val = 0; + mask = 0; + if (wm8996->hpout_pending & HPOUT1L) { + val |= WM8996_HPOUT1L_RMV_SHORT; + mask |= WM8996_HPOUT1L_RMV_SHORT; + } else { + mask |= WM8996_HPOUT1L_RMV_SHORT | + WM8996_HPOUT1L_OUTP | + WM8996_HPOUT1L_DLY; + } + + if (wm8996->hpout_pending & HPOUT1R) { + val |= WM8996_HPOUT1R_RMV_SHORT; + mask |= WM8996_HPOUT1R_RMV_SHORT; + } else { + mask |= WM8996_HPOUT1R_RMV_SHORT | + WM8996_HPOUT1R_OUTP | + WM8996_HPOUT1R_DLY; + } + + snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val); + + val = 0; + mask = 0; + if (wm8996->hpout_pending & HPOUT2L) { + val |= WM8996_HPOUT2L_RMV_SHORT; + mask |= WM8996_HPOUT2L_RMV_SHORT; + } else { + mask |= WM8996_HPOUT2L_RMV_SHORT | + WM8996_HPOUT2L_OUTP | + WM8996_HPOUT2L_DLY; + } + + if (wm8996->hpout_pending & HPOUT2R) { + val |= WM8996_HPOUT2R_RMV_SHORT; + mask |= WM8996_HPOUT2R_RMV_SHORT; + } else { + mask |= WM8996_HPOUT2R_RMV_SHORT | + WM8996_HPOUT2R_OUTP | + WM8996_HPOUT2R_DLY; + } + + snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val); + + wm8996->hpout_ena = wm8996->hpout_pending; + } +} + +static int dcs_start(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + wm8996->dcs_pending |= 1 << w->shift; + break; + default: + BUG(); + return -EINVAL; + } + + return 0; +} + +static const char *sidetone_text[] = { + "IN1", "IN2", +}; + +static const struct soc_enum left_sidetone_enum = + SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text); + +static const struct snd_kcontrol_new left_sidetone = + SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); + +static const struct soc_enum right_sidetone_enum = + SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text); + +static const struct snd_kcontrol_new right_sidetone = + SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); + +static const char *spk_text[] = { + "DAC1L", "DAC1R", "DAC2L", "DAC2R" +}; + +static const struct soc_enum spkl_enum = + SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text); + +static const struct snd_kcontrol_new spkl_mux = + SOC_DAPM_ENUM("SPKL", spkl_enum); + +static const struct soc_enum spkr_enum = + SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text); + +static const struct snd_kcontrol_new spkr_mux = + SOC_DAPM_ENUM("SPKR", spkr_enum); + +static const char *dsp1rx_text[] = { + "AIF1", "AIF2" +}; + +static const struct soc_enum dsp1rx_enum = + SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text); + +static const struct snd_kcontrol_new dsp1rx = + SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); + +static const char *dsp2rx_text[] = { + "AIF2", "AIF1" +}; + +static const struct soc_enum dsp2rx_enum = + SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text); + +static const struct snd_kcontrol_new dsp2rx = + SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); + +static const char *aif2tx_text[] = { + "DSP2", "DSP1", "AIF1" +}; + +static const struct soc_enum aif2tx_enum = + SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text); + +static const struct snd_kcontrol_new aif2tx = + SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); + +static const char *inmux_text[] = { + "ADC", "DMIC1", "DMIC2" +}; + +static const struct soc_enum in1_enum = + SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text); + +static const struct snd_kcontrol_new in1_mux = + SOC_DAPM_ENUM("IN1 Mux", in1_enum); + +static const struct soc_enum in2_enum = + SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text); + +static const struct snd_kcontrol_new in2_mux = + SOC_DAPM_ENUM("IN2 Mux", in2_enum); + +static const struct snd_kcontrol_new dac2r_mix[] = { +SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, + 5, 1, 0), +SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, + 4, 1, 0), +SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), +SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), +}; + +static const struct snd_kcontrol_new dac2l_mix[] = { +SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, + 5, 1, 0), +SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, + 4, 1, 0), +SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), +SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), +}; + +static const struct snd_kcontrol_new dac1r_mix[] = { +SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, + 5, 1, 0), +SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, + 4, 1, 0), +SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), +SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), +}; + +static const struct snd_kcontrol_new dac1l_mix[] = { +SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, + 5, 1, 0), +SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, + 4, 1, 0), +SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), +SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), +}; + +static const struct snd_kcontrol_new dsp1txl[] = { +SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, + 1, 1, 0), +SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new dsp1txr[] = { +SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, + 1, 1, 0), +SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new dsp2txl[] = { +SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, + 1, 1, 0), +SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, + 0, 1, 0), +}; + +static const struct snd_kcontrol_new dsp2txr[] = { +SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, + 1, 1, 0), +SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, + 0, 1, 0), +}; + + +static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { +SND_SOC_DAPM_INPUT("IN1LN"), +SND_SOC_DAPM_INPUT("IN1LP"), +SND_SOC_DAPM_INPUT("IN1RN"), +SND_SOC_DAPM_INPUT("IN1RP"), + +SND_SOC_DAPM_INPUT("IN2LN"), +SND_SOC_DAPM_INPUT("IN2LP"), +SND_SOC_DAPM_INPUT("IN2RN"), +SND_SOC_DAPM_INPUT("IN2RP"), + +SND_SOC_DAPM_INPUT("DMIC1DAT"), +SND_SOC_DAPM_INPUT("DMIC2DAT"), + +SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, + SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), +SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), +SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), + +SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux), +SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux), +SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux), + +SND_SOC_DAPM_PGA("IN1L", WM8996_POWER_MANAGEMENT_7, 2, 0, NULL, 0), +SND_SOC_DAPM_PGA("IN1R", WM8996_POWER_MANAGEMENT_7, 3, 0, NULL, 0), +SND_SOC_DAPM_PGA("IN2L", WM8996_POWER_MANAGEMENT_7, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("IN2R", WM8996_POWER_MANAGEMENT_7, 7, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), + +SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), +SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), +SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), +SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), + +SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), +SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), + +SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), +SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), + +SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), +SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), +SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), +SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), + +SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, + dsp2txl, ARRAY_SIZE(dsp2txl)), +SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, + dsp2txr, ARRAY_SIZE(dsp2txr)), +SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, + dsp1txl, ARRAY_SIZE(dsp1txl)), +SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, + dsp1txr, ARRAY_SIZE(dsp1txr)), + +SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, + dac2l_mix, ARRAY_SIZE(dac2l_mix)), +SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, + dac2r_mix, ARRAY_SIZE(dac2r_mix)), +SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, + dac1l_mix, ARRAY_SIZE(dac1l_mix)), +SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, + dac1r_mix, ARRAY_SIZE(dac1r_mix)), + +SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), +SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), +SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), +SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1, + WM8996_POWER_MANAGEMENT_4, 9, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2, + WM8996_POWER_MANAGEMENT_4, 8, 0), + +SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1, + WM8996_POWER_MANAGEMENT_6, 9, 0), +SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2, + WM8996_POWER_MANAGEMENT_6, 8, 0), + +SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5, + WM8996_POWER_MANAGEMENT_4, 5, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4, + WM8996_POWER_MANAGEMENT_4, 4, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3, + WM8996_POWER_MANAGEMENT_4, 3, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2, + WM8996_POWER_MANAGEMENT_4, 2, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1, + WM8996_POWER_MANAGEMENT_4, 1, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0, + WM8996_POWER_MANAGEMENT_4, 0, 0), + +SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5, + WM8996_POWER_MANAGEMENT_6, 5, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4, + WM8996_POWER_MANAGEMENT_6, 4, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3, + WM8996_POWER_MANAGEMENT_6, 3, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2, + WM8996_POWER_MANAGEMENT_6, 2, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1, + WM8996_POWER_MANAGEMENT_6, 1, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0, + WM8996_POWER_MANAGEMENT_6, 0, 0), + +/* We route as stereo pairs so define some dummy widgets to squash + * things down for now. RXA = 0,1, RXB = 2,3 and so on */ +SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), +SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), +SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), + +SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), +SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), +SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), +SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), + +SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, + rmv_short_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, + rmv_short_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, + rmv_short_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0), +SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, + rmv_short_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_OUTPUT("HPOUT1L"), +SND_SOC_DAPM_OUTPUT("HPOUT1R"), +SND_SOC_DAPM_OUTPUT("HPOUT2L"), +SND_SOC_DAPM_OUTPUT("HPOUT2R"), +SND_SOC_DAPM_OUTPUT("SPKDAT"), +}; + +static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { + { "AIFCLK", NULL, "SYSCLK" }, + { "SYSDSPCLK", NULL, "SYSCLK" }, + { "Charge Pump", NULL, "SYSCLK" }, + + { "MICB1", NULL, "LDO2" }, + { "MICB2", NULL, "LDO2" }, + + { "IN1L PGA", NULL, "IN2LN" }, + { "IN1L PGA", NULL, "IN2LP" }, + { "IN1L PGA", NULL, "IN1LN" }, + { "IN1L PGA", NULL, "IN1LP" }, + + { "IN1R PGA", NULL, "IN2RN" }, + { "IN1R PGA", NULL, "IN2RP" }, + { "IN1R PGA", NULL, "IN1RN" }, + { "IN1R PGA", NULL, "IN1RP" }, + + { "ADCL", NULL, "IN1L PGA" }, + + { "ADCR", NULL, "IN1R PGA" }, + + { "DMIC1L", NULL, "DMIC1DAT" }, + { "DMIC1R", NULL, "DMIC1DAT" }, + { "DMIC2L", NULL, "DMIC2DAT" }, + { "DMIC2R", NULL, "DMIC2DAT" }, + + { "DMIC2L", NULL, "DMIC2" }, + { "DMIC2R", NULL, "DMIC2" }, + { "DMIC1L", NULL, "DMIC1" }, + { "DMIC1R", NULL, "DMIC1" }, + + { "IN1L Mux", "ADC", "ADCL" }, + { "IN1L Mux", "DMIC1", "DMIC1L" }, + { "IN1L Mux", "DMIC2", "DMIC2L" }, + + { "IN1R Mux", "ADC", "ADCR" }, + { "IN1R Mux", "DMIC1", "DMIC1R" }, + { "IN1R Mux", "DMIC2", "DMIC2R" }, + + { "IN2L Mux", "ADC", "ADCL" }, + { "IN2L Mux", "DMIC1", "DMIC1L" }, + { "IN2L Mux", "DMIC2", "DMIC2L" }, + + { "IN2R Mux", "ADC", "ADCR" }, + { "IN2R Mux", "DMIC1", "DMIC1R" }, + { "IN2R Mux", "DMIC2", "DMIC2R" }, + + { "Left Sidetone", "IN1", "IN1L Mux" }, + { "Left Sidetone", "IN2", "IN2L Mux" }, + + { "Right Sidetone", "IN1", "IN1R Mux" }, + { "Right Sidetone", "IN2", "IN2R Mux" }, + + { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, + { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, + + { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, + { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, + + { "AIF1TX0", NULL, "DSP1TXL" }, + { "AIF1TX1", NULL, "DSP1TXR" }, + { "AIF1TX2", NULL, "DSP2TXL" }, + { "AIF1TX3", NULL, "DSP2TXR" }, + { "AIF1TX4", NULL, "AIF2RX0" }, + { "AIF1TX5", NULL, "AIF2RX1" }, + + { "AIF1RX0", NULL, "AIFCLK" }, + { "AIF1RX1", NULL, "AIFCLK" }, + { "AIF1RX2", NULL, "AIFCLK" }, + { "AIF1RX3", NULL, "AIFCLK" }, + { "AIF1RX4", NULL, "AIFCLK" }, + { "AIF1RX5", NULL, "AIFCLK" }, + + { "AIF2RX0", NULL, "AIFCLK" }, + { "AIF2RX1", NULL, "AIFCLK" }, + + { "DSP1RXL", NULL, "SYSDSPCLK" }, + { "DSP1RXR", NULL, "SYSDSPCLK" }, + { "DSP2RXL", NULL, "SYSDSPCLK" }, + { "DSP2RXR", NULL, "SYSDSPCLK" }, + { "DSP1TXL", NULL, "SYSDSPCLK" }, + { "DSP1TXR", NULL, "SYSDSPCLK" }, + { "DSP2TXL", NULL, "SYSDSPCLK" }, + { "DSP2TXR", NULL, "SYSDSPCLK" }, + + { "AIF1RXA", NULL, "AIF1RX0" }, + { "AIF1RXA", NULL, "AIF1RX1" }, + { "AIF1RXB", NULL, "AIF1RX2" }, + { "AIF1RXB", NULL, "AIF1RX3" }, + { "AIF1RXC", NULL, "AIF1RX4" }, + { "AIF1RXC", NULL, "AIF1RX5" }, + + { "AIF2RX", NULL, "AIF2RX0" }, + { "AIF2RX", NULL, "AIF2RX1" }, + + { "AIF2TX", "DSP2", "DSP2TX" }, + { "AIF2TX", "DSP1", "DSP1RX" }, + { "AIF2TX", "AIF1", "AIF1RXC" }, + + { "DSP1RXL", NULL, "DSP1RX" }, + { "DSP1RXR", NULL, "DSP1RX" }, + { "DSP2RXL", NULL, "DSP2RX" }, + { "DSP2RXR", NULL, "DSP2RX" }, + + { "DSP2TX", NULL, "DSP2TXL" }, + { "DSP2TX", NULL, "DSP2TXR" }, + + { "DSP1RX", "AIF1", "AIF1RXA" }, + { "DSP1RX", "AIF2", "AIF2RX" }, + + { "DSP2RX", "AIF1", "AIF1RXB" }, + { "DSP2RX", "AIF2", "AIF2RX" }, + + { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, + { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, + { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, + { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, + + { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, + { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, + { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, + { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, + + { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, + { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, + { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, + { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, + + { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, + { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, + { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, + { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, + + { "DAC1L", NULL, "DAC1L Mixer" }, + { "DAC1R", NULL, "DAC1R Mixer" }, + { "DAC2L", NULL, "DAC2L Mixer" }, + { "DAC2R", NULL, "DAC2R Mixer" }, + + { "HPOUT2L PGA", NULL, "Charge Pump" }, + { "HPOUT2L PGA", NULL, "DAC2L" }, + { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, + { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, + { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" }, + { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" }, + + { "HPOUT2R PGA", NULL, "Charge Pump" }, + { "HPOUT2R PGA", NULL, "DAC2R" }, + { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, + { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, + { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" }, + { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" }, + + { "HPOUT1L PGA", NULL, "Charge Pump" }, + { "HPOUT1L PGA", NULL, "DAC1L" }, + { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, + { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, + { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" }, + { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" }, + + { "HPOUT1R PGA", NULL, "Charge Pump" }, + { "HPOUT1R PGA", NULL, "DAC1R" }, + { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, + { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, + { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" }, + { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" }, + + { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, + { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, + { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, + { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, + + { "SPKL", "DAC1L", "DAC1L" }, + { "SPKL", "DAC1R", "DAC1R" }, + { "SPKL", "DAC2L", "DAC2L" }, + { "SPKL", "DAC2R", "DAC2R" }, + + { "SPKR", "DAC1L", "DAC1L" }, + { "SPKR", "DAC1R", "DAC1R" }, + { "SPKR", "DAC2L", "DAC2L" }, + { "SPKR", "DAC2R", "DAC2R" }, + + { "SPKL PGA", NULL, "SPKL" }, + { "SPKR PGA", NULL, "SPKR" }, + + { "SPKDAT", NULL, "SPKL PGA" }, + { "SPKDAT", NULL, "SPKR PGA" }, +}; + +static int wm8996_readable_register(struct snd_soc_codec *codec, + unsigned int reg) +{ + /* Due to the sparseness of the register map the compiler + * output from an explicit switch statement ends up being much + * more efficient than a table. + */ + switch (reg) { + case WM8996_SOFTWARE_RESET: + case WM8996_POWER_MANAGEMENT_1: + case WM8996_POWER_MANAGEMENT_2: + case WM8996_POWER_MANAGEMENT_3: + case WM8996_POWER_MANAGEMENT_4: + case WM8996_POWER_MANAGEMENT_5: + case WM8996_POWER_MANAGEMENT_6: + case WM8996_POWER_MANAGEMENT_7: + case WM8996_POWER_MANAGEMENT_8: + case WM8996_LEFT_LINE_INPUT_VOLUME: + case WM8996_RIGHT_LINE_INPUT_VOLUME: + case WM8996_LINE_INPUT_CONTROL: + case WM8996_DAC1_HPOUT1_VOLUME: + case WM8996_DAC2_HPOUT2_VOLUME: + case WM8996_DAC1_LEFT_VOLUME: + case WM8996_DAC1_RIGHT_VOLUME: + case WM8996_DAC2_LEFT_VOLUME: + case WM8996_DAC2_RIGHT_VOLUME: + case WM8996_OUTPUT1_LEFT_VOLUME: + case WM8996_OUTPUT1_RIGHT_VOLUME: + case WM8996_OUTPUT2_LEFT_VOLUME: + case WM8996_OUTPUT2_RIGHT_VOLUME: + case WM8996_MICBIAS_1: + case WM8996_MICBIAS_2: + case WM8996_LDO_1: + case WM8996_LDO_2: + case WM8996_ACCESSORY_DETECT_MODE_1: + case WM8996_ACCESSORY_DETECT_MODE_2: + case WM8996_HEADPHONE_DETECT_1: + case WM8996_HEADPHONE_DETECT_2: + case WM8996_MIC_DETECT_1: + case WM8996_MIC_DETECT_2: + case WM8996_MIC_DETECT_3: + case WM8996_CHARGE_PUMP_1: + case WM8996_CHARGE_PUMP_2: + case WM8996_DC_SERVO_1: + case WM8996_DC_SERVO_2: + case WM8996_DC_SERVO_3: + case WM8996_DC_SERVO_5: + case WM8996_DC_SERVO_6: + case WM8996_DC_SERVO_7: + case WM8996_DC_SERVO_READBACK_0: + case WM8996_ANALOGUE_HP_1: + case WM8996_ANALOGUE_HP_2: + case WM8996_CHIP_REVISION: + case WM8996_CONTROL_INTERFACE_1: + case WM8996_WRITE_SEQUENCER_CTRL_1: + case WM8996_WRITE_SEQUENCER_CTRL_2: + case WM8996_AIF_CLOCKING_1: + case WM8996_AIF_CLOCKING_2: + case WM8996_CLOCKING_1: + case WM8996_CLOCKING_2: + case WM8996_AIF_RATE: + case WM8996_FLL_CONTROL_1: + case WM8996_FLL_CONTROL_2: + case WM8996_FLL_CONTROL_3: + case WM8996_FLL_CONTROL_4: + case WM8996_FLL_CONTROL_5: + case WM8996_FLL_CONTROL_6: + case WM8996_FLL_EFS_1: + case WM8996_FLL_EFS_2: + case WM8996_AIF1_CONTROL: + case WM8996_AIF1_BCLK: + case WM8996_AIF1_TX_LRCLK_1: + case WM8996_AIF1_TX_LRCLK_2: + case WM8996_AIF1_RX_LRCLK_1: + case WM8996_AIF1_RX_LRCLK_2: + case WM8996_AIF1TX_DATA_CONFIGURATION_1: + case WM8996_AIF1TX_DATA_CONFIGURATION_2: + case WM8996_AIF1RX_DATA_CONFIGURATION: + case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: + case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: + case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: + case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: + case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: + case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: + case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: + case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: + case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: + case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: + case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: + case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: + case WM8996_AIF1RX_MONO_CONFIGURATION: + case WM8996_AIF1TX_TEST: + case WM8996_AIF2_CONTROL: + case WM8996_AIF2_BCLK: + case WM8996_AIF2_TX_LRCLK_1: + case WM8996_AIF2_TX_LRCLK_2: + case WM8996_AIF2_RX_LRCLK_1: + case WM8996_AIF2_RX_LRCLK_2: + case WM8996_AIF2TX_DATA_CONFIGURATION_1: + case WM8996_AIF2TX_DATA_CONFIGURATION_2: + case WM8996_AIF2RX_DATA_CONFIGURATION: + case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: + case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: + case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: + case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: + case WM8996_AIF2RX_MONO_CONFIGURATION: + case WM8996_AIF2TX_TEST: + case WM8996_DSP1_TX_LEFT_VOLUME: + case WM8996_DSP1_TX_RIGHT_VOLUME: + case WM8996_DSP1_RX_LEFT_VOLUME: + case WM8996_DSP1_RX_RIGHT_VOLUME: + case WM8996_DSP1_TX_FILTERS: + case WM8996_DSP1_RX_FILTERS_1: + case WM8996_DSP1_RX_FILTERS_2: + case WM8996_DSP1_DRC_1: + case WM8996_DSP1_DRC_2: + case WM8996_DSP1_DRC_3: + case WM8996_DSP1_DRC_4: + case WM8996_DSP1_DRC_5: + case WM8996_DSP1_RX_EQ_GAINS_1: + case WM8996_DSP1_RX_EQ_GAINS_2: + case WM8996_DSP1_RX_EQ_BAND_1_A: + case WM8996_DSP1_RX_EQ_BAND_1_B: + case WM8996_DSP1_RX_EQ_BAND_1_PG: + case WM8996_DSP1_RX_EQ_BAND_2_A: + case WM8996_DSP1_RX_EQ_BAND_2_B: + case WM8996_DSP1_RX_EQ_BAND_2_C: + case WM8996_DSP1_RX_EQ_BAND_2_PG: + case WM8996_DSP1_RX_EQ_BAND_3_A: + case WM8996_DSP1_RX_EQ_BAND_3_B: + case WM8996_DSP1_RX_EQ_BAND_3_C: + case WM8996_DSP1_RX_EQ_BAND_3_PG: + case WM8996_DSP1_RX_EQ_BAND_4_A: + case WM8996_DSP1_RX_EQ_BAND_4_B: + case WM8996_DSP1_RX_EQ_BAND_4_C: + case WM8996_DSP1_RX_EQ_BAND_4_PG: + case WM8996_DSP1_RX_EQ_BAND_5_A: + case WM8996_DSP1_RX_EQ_BAND_5_B: + case WM8996_DSP1_RX_EQ_BAND_5_PG: + case WM8996_DSP2_TX_LEFT_VOLUME: + case WM8996_DSP2_TX_RIGHT_VOLUME: + case WM8996_DSP2_RX_LEFT_VOLUME: + case WM8996_DSP2_RX_RIGHT_VOLUME: + case WM8996_DSP2_TX_FILTERS: + case WM8996_DSP2_RX_FILTERS_1: + case WM8996_DSP2_RX_FILTERS_2: + case WM8996_DSP2_DRC_1: + case WM8996_DSP2_DRC_2: + case WM8996_DSP2_DRC_3: + case WM8996_DSP2_DRC_4: + case WM8996_DSP2_DRC_5: + case WM8996_DSP2_RX_EQ_GAINS_1: + case WM8996_DSP2_RX_EQ_GAINS_2: + case WM8996_DSP2_RX_EQ_BAND_1_A: + case WM8996_DSP2_RX_EQ_BAND_1_B: + case WM8996_DSP2_RX_EQ_BAND_1_PG: + case WM8996_DSP2_RX_EQ_BAND_2_A: + case WM8996_DSP2_RX_EQ_BAND_2_B: + case WM8996_DSP2_RX_EQ_BAND_2_C: + case WM8996_DSP2_RX_EQ_BAND_2_PG: + case WM8996_DSP2_RX_EQ_BAND_3_A: + case WM8996_DSP2_RX_EQ_BAND_3_B: + case WM8996_DSP2_RX_EQ_BAND_3_C: + case WM8996_DSP2_RX_EQ_BAND_3_PG: + case WM8996_DSP2_RX_EQ_BAND_4_A: + case WM8996_DSP2_RX_EQ_BAND_4_B: + case WM8996_DSP2_RX_EQ_BAND_4_C: + case WM8996_DSP2_RX_EQ_BAND_4_PG: + case WM8996_DSP2_RX_EQ_BAND_5_A: + case WM8996_DSP2_RX_EQ_BAND_5_B: + case WM8996_DSP2_RX_EQ_BAND_5_PG: + case WM8996_DAC1_MIXER_VOLUMES: + case WM8996_DAC1_LEFT_MIXER_ROUTING: + case WM8996_DAC1_RIGHT_MIXER_ROUTING: + case WM8996_DAC2_MIXER_VOLUMES: + case WM8996_DAC2_LEFT_MIXER_ROUTING: + case WM8996_DAC2_RIGHT_MIXER_ROUTING: + case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: + case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: + case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: + case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: + case WM8996_DSP_TX_MIXER_SELECT: + case WM8996_DAC_SOFTMUTE: + case WM8996_OVERSAMPLING: + case WM8996_SIDETONE: + case WM8996_GPIO_1: + case WM8996_GPIO_2: + case WM8996_GPIO_3: + case WM8996_GPIO_4: + case WM8996_GPIO_5: + case WM8996_PULL_CONTROL_1: + case WM8996_PULL_CONTROL_2: + case WM8996_INTERRUPT_STATUS_1: + case WM8996_INTERRUPT_STATUS_2: + case WM8996_INTERRUPT_RAW_STATUS_2: + case WM8996_INTERRUPT_STATUS_1_MASK: + case WM8996_INTERRUPT_STATUS_2_MASK: + case WM8996_INTERRUPT_CONTROL: + case WM8996_LEFT_PDM_SPEAKER: + case WM8996_RIGHT_PDM_SPEAKER: + case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: + case WM8996_PDM_SPEAKER_VOLUME: + return 1; + default: + return 0; + } +} + +static int wm8996_volatile_register(struct snd_soc_codec *codec, + unsigned int reg) +{ + switch (reg) { + case WM8996_SOFTWARE_RESET: + case WM8996_CHIP_REVISION: + case WM8996_LDO_1: + case WM8996_LDO_2: + case WM8996_INTERRUPT_STATUS_1: + case WM8996_INTERRUPT_STATUS_2: + case WM8996_INTERRUPT_RAW_STATUS_2: + case WM8996_DC_SERVO_READBACK_0: + case WM8996_DC_SERVO_2: + case WM8996_DC_SERVO_6: + case WM8996_DC_SERVO_7: + case WM8996_FLL_CONTROL_6: + case WM8996_MIC_DETECT_3: + case WM8996_HEADPHONE_DETECT_1: + case WM8996_HEADPHONE_DETECT_2: + return 1; + default: + return 0; + } +} + +static int wm8996_reset(struct snd_soc_codec *codec) +{ + return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915); +} + +static const int bclk_divs[] = { + 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 +}; + +static void wm8996_update_bclk(struct snd_soc_codec *codec) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int aif, best, cur_val, bclk_rate, bclk_reg, i; + + /* Don't bother if we're in a low frequency idle mode that + * can't support audio. + */ + if (wm8996->sysclk < 64000) + return; + + for (aif = 0; aif < WM8996_AIFS; aif++) { + switch (aif) { + case 0: + bclk_reg = WM8996_AIF1_BCLK; + break; + case 1: + bclk_reg = WM8996_AIF2_BCLK; + break; + } + + bclk_rate = wm8996->bclk_rate[aif]; + + /* Pick a divisor for BCLK as close as we can get to ideal */ + best = 0; + for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { + cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; + if (cur_val < 0) /* BCLK table is sorted */ + break; + best = i; + } + bclk_rate = wm8996->sysclk / bclk_divs[best]; + dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", + bclk_divs[best], bclk_rate); + + snd_soc_update_bits(codec, bclk_reg, + WM8996_AIF1_BCLK_DIV_MASK, best); + } +} + +static int wm8996_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int ret; + + switch (level) { + case SND_SOC_BIAS_ON: + break; + + case SND_SOC_BIAS_PREPARE: + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { + snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, + WM8996_BG_ENA, WM8996_BG_ENA); + msleep(2); + } + break; + + case SND_SOC_BIAS_STANDBY: + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { + ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), + wm8996->supplies); + if (ret != 0) { + dev_err(codec->dev, + "Failed to enable supplies: %d\n", + ret); + return ret; + } + + if (wm8996->pdata.ldo_ena >= 0) { + gpio_set_value_cansleep(wm8996->pdata.ldo_ena, + 1); + msleep(5); + } + + codec->cache_only = false; + snd_soc_cache_sync(codec); + } + + snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, + WM8996_BG_ENA, 0); + break; + + case SND_SOC_BIAS_OFF: + codec->cache_only = true; + if (wm8996->pdata.ldo_ena >= 0) + gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); + regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), + wm8996->supplies); + break; + } + + codec->dapm.bias_level = level; + + return 0; +} + +static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = dai->codec; + int aifctrl = 0; + int bclk = 0; + int lrclk_tx = 0; + int lrclk_rx = 0; + int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; + + switch (dai->id) { + case 0: + aifctrl_reg = WM8996_AIF1_CONTROL; + bclk_reg = WM8996_AIF1_BCLK; + lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; + lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; + break; + case 1: + aifctrl_reg = WM8996_AIF2_CONTROL; + bclk_reg = WM8996_AIF2_BCLK; + lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; + lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; + break; + default: + BUG(); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + bclk |= WM8996_AIF1_BCLK_INV; + break; + case SND_SOC_DAIFMT_NB_IF: + lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; + lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; + break; + case SND_SOC_DAIFMT_IB_IF: + bclk |= WM8996_AIF1_BCLK_INV; + lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; + lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; + break; + } + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + break; + case SND_SOC_DAIFMT_CBS_CFM: + lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; + lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; + break; + case SND_SOC_DAIFMT_CBM_CFS: + bclk |= WM8996_AIF1_BCLK_MSTR; + break; + case SND_SOC_DAIFMT_CBM_CFM: + bclk |= WM8996_AIF1_BCLK_MSTR; + lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; + lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + break; + case SND_SOC_DAIFMT_DSP_B: + aifctrl |= 1; + break; + case SND_SOC_DAIFMT_I2S: + aifctrl |= 2; + break; + case SND_SOC_DAIFMT_LEFT_J: + aifctrl |= 3; + break; + default: + return -EINVAL; + } + + snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); + snd_soc_update_bits(codec, bclk_reg, + WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, + bclk); + snd_soc_update_bits(codec, lrclk_tx_reg, + WM8996_AIF1TX_LRCLK_INV | + WM8996_AIF1TX_LRCLK_MSTR, + lrclk_tx); + snd_soc_update_bits(codec, lrclk_rx_reg, + WM8996_AIF1RX_LRCLK_INV | + WM8996_AIF1RX_LRCLK_MSTR, + lrclk_rx); + + return 0; +} + +static const int dsp_divs[] = { + 48000, 32000, 16000, 8000 +}; + +static int wm8996_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int bits, i, bclk_rate; + int aifdata = 0; + int lrclk = 0; + int dsp = 0; + int aifdata_reg, lrclk_reg, dsp_shift; + + switch (dai->id) { + case 0: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || + (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { + aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; + lrclk_reg = WM8996_AIF1_RX_LRCLK_1; + } else { + aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; + lrclk_reg = WM8996_AIF1_TX_LRCLK_1; + } + dsp_shift = 0; + break; + case 1: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || + (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { + aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; + lrclk_reg = WM8996_AIF2_RX_LRCLK_1; + } else { + aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; + lrclk_reg = WM8996_AIF2_TX_LRCLK_1; + } + dsp_shift = WM8996_DSP2_DIV_SHIFT; + break; + default: + BUG(); + return -EINVAL; + } + + bclk_rate = snd_soc_params_to_bclk(params); + if (bclk_rate < 0) { + dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); + return bclk_rate; + } + + wm8996->bclk_rate[dai->id] = bclk_rate; + wm8996->rx_rate[dai->id] = params_rate(params); + + /* Needs looking at for TDM */ + bits = snd_pcm_format_width(params_format(params)); + if (bits < 0) + return bits; + aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; + + for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { + if (dsp_divs[i] == params_rate(params)) + break; + } + if (i == ARRAY_SIZE(dsp_divs)) { + dev_err(codec->dev, "Unsupported sample rate %dHz\n", + params_rate(params)); + return -EINVAL; + } + dsp |= i << dsp_shift; + + wm8996_update_bclk(codec); + + lrclk = bclk_rate / params_rate(params); + dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", + lrclk, bclk_rate / lrclk); + + snd_soc_update_bits(codec, aifdata_reg, + WM8996_AIF1TX_WL_MASK | + WM8996_AIF1TX_SLOT_LEN_MASK, + aifdata); + snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK, + lrclk); + snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2, + WM8996_DSP1_DIV_SHIFT << dsp_shift, dsp); + + return 0; +} + +static int wm8996_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int lfclk = 0; + int ratediv = 0; + int src; + int old; + + if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) + return 0; + + /* Disable SYSCLK while we reconfigure */ + old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; + snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, + WM8996_SYSCLK_ENA, 0); + + switch (clk_id) { + case WM8996_SYSCLK_MCLK1: + wm8996->sysclk = freq; + src = 0; + break; + case WM8996_SYSCLK_MCLK2: + wm8996->sysclk = freq; + src = 1; + break; + case WM8996_SYSCLK_FLL: + wm8996->sysclk = freq; + src = 2; + break; + default: + dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); + return -EINVAL; + } + + switch (wm8996->sysclk) { + case 6144000: + snd_soc_update_bits(codec, WM8996_AIF_RATE, + WM8996_SYSCLK_RATE, 0); + break; + case 24576000: + ratediv = WM8996_SYSCLK_DIV; + case 12288000: + snd_soc_update_bits(codec, WM8996_AIF_RATE, + WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); + break; + case 32000: + case 32768: + lfclk = WM8996_LFCLK_ENA; + break; + default: + dev_warn(codec->dev, "Unsupported clock rate %dHz\n", + wm8996->sysclk); + return -EINVAL; + } + + wm8996_update_bclk(codec); + + snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, + WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, + src << WM8996_SYSCLK_SRC_SHIFT | ratediv); + snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); + snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, + WM8996_SYSCLK_ENA, old); + + wm8996->sysclk_src = clk_id; + + return 0; +} + +struct _fll_div { + u16 fll_fratio; + u16 fll_outdiv; + u16 fll_refclk_div; + u16 fll_loop_gain; + u16 fll_ref_freq; + u16 n; + u16 theta; + u16 lambda; +}; + +static struct { + unsigned int min; + unsigned int max; + u16 fll_fratio; + int ratio; +} fll_fratios[] = { + { 0, 64000, 4, 16 }, + { 64000, 128000, 3, 8 }, + { 128000, 256000, 2, 4 }, + { 256000, 1000000, 1, 2 }, + { 1000000, 13500000, 0, 1 }, +}; + +static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, + unsigned int Fout) +{ + unsigned int target; + unsigned int div; + unsigned int fratio, gcd_fll; + int i; + + /* Fref must be <=13.5MHz */ + div = 1; + fll_div->fll_refclk_div = 0; + while ((Fref / div) > 13500000) { + div *= 2; + fll_div->fll_refclk_div++; + + if (div > 8) { + pr_err("Can't scale %dMHz input down to <=13.5MHz\n", + Fref); + return -EINVAL; + } + } + + pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); + + /* Apply the division for our remaining calculations */ + Fref /= div; + + if (Fref >= 3000000) + fll_div->fll_loop_gain = 5; + else + fll_div->fll_loop_gain = 0; + + if (Fref >= 48000) + fll_div->fll_ref_freq = 0; + else + fll_div->fll_ref_freq = 1; + + /* Fvco should be 90-100MHz; don't check the upper bound */ + div = 2; + while (Fout * div < 90000000) { + div++; + if (div > 64) { + pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", + Fout); + return -EINVAL; + } + } + target = Fout * div; + fll_div->fll_outdiv = div - 1; + + pr_debug("FLL Fvco=%dHz\n", target); + + /* Find an appropraite FLL_FRATIO and factor it out of the target */ + for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { + if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { + fll_div->fll_fratio = fll_fratios[i].fll_fratio; + fratio = fll_fratios[i].ratio; + break; + } + } + if (i == ARRAY_SIZE(fll_fratios)) { + pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); + return -EINVAL; + } + + fll_div->n = target / (fratio * Fref); + + if (target % Fref == 0) { + fll_div->theta = 0; + fll_div->lambda = 0; + } else { + gcd_fll = gcd(target, fratio * Fref); + + fll_div->theta = (target - (fll_div->n * fratio * Fref)) + / gcd_fll; + fll_div->lambda = (fratio * Fref) / gcd_fll; + } + + pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", + fll_div->n, fll_div->theta, fll_div->lambda); + pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", + fll_div->fll_fratio, fll_div->fll_outdiv, + fll_div->fll_refclk_div); + + return 0; +} + +static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *i2c = to_i2c_client(codec->dev); + struct _fll_div fll_div; + unsigned long timeout; + int ret, reg; + + /* Any change? */ + if (source == wm8996->fll_src && Fref == wm8996->fll_fref && + Fout == wm8996->fll_fout) + return 0; + + if (Fout == 0) { + dev_dbg(codec->dev, "FLL disabled\n"); + + wm8996->fll_fref = 0; + wm8996->fll_fout = 0; + + snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, + WM8996_FLL_ENA, 0); + + return 0; + } + + ret = fll_factors(&fll_div, Fref, Fout); + if (ret != 0) + return ret; + + switch (source) { + case WM8996_FLL_MCLK1: + reg = 0; + break; + case WM8996_FLL_MCLK2: + reg = 1; + break; + case WM8996_FLL_DACLRCLK1: + reg = 2; + break; + case WM8996_FLL_BCLK1: + reg = 3; + break; + default: + dev_err(codec->dev, "Unknown FLL source %d\n", ret); + return -EINVAL; + } + + reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; + reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; + + snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5, + WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | + WM8996_FLL_REFCLK_SRC_MASK, reg); + + reg = 0; + if (fll_div.theta || fll_div.lambda) + reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); + else + reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; + snd_soc_write(codec, WM8996_FLL_EFS_2, reg); + + snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2, + WM8996_FLL_OUTDIV_MASK | + WM8996_FLL_FRATIO_MASK, + (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | + (fll_div.fll_fratio)); + + snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta); + + snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4, + WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, + (fll_div.n << WM8996_FLL_N_SHIFT) | + fll_div.fll_loop_gain); + + snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda); + + snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, + WM8996_FLL_ENA, WM8996_FLL_ENA); + + /* The FLL supports live reconfiguration - kick that in case we were + * already enabled. + */ + snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); + + /* Wait for the FLL to lock, using the interrupt if possible */ + if (Fref > 1000000) + timeout = usecs_to_jiffies(300); + else + timeout = msecs_to_jiffies(2); + + /* Allow substantially longer if we've actually got the IRQ */ + if (i2c->irq) + timeout *= 1000; + + ret = wait_for_completion_timeout(&wm8996->fll_lock, timeout); + + if (ret == 0 && i2c->irq) { + dev_err(codec->dev, "Timed out waiting for FLL\n"); + ret = -ETIMEDOUT; + } else { + ret = 0; + } + + dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); + + wm8996->fll_fref = Fref; + wm8996->fll_fout = Fout; + wm8996->fll_src = source; + + return ret; +} + +#ifdef CONFIG_GPIOLIB +static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip) +{ + return container_of(chip, struct wm8996_priv, gpio_chip); +} + +static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); + struct snd_soc_codec *codec = wm8996->codec; + + snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, + WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); +} + +static int wm8996_gpio_direction_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); + struct snd_soc_codec *codec = wm8996->codec; + int val; + + val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); + + return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, + WM8996_GP1_FN_MASK | WM8996_GP1_DIR | + WM8996_GP1_LVL, val); +} + +static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); + struct snd_soc_codec *codec = wm8996->codec; + int ret; + + ret = snd_soc_read(codec, WM8996_GPIO_1 + offset); + if (ret < 0) + return ret; + + return (ret & WM8996_GP1_LVL) != 0; +} + +static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) +{ + struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); + struct snd_soc_codec *codec = wm8996->codec; + + return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, + WM8996_GP1_FN_MASK | WM8996_GP1_DIR, + (1 << WM8996_GP1_FN_SHIFT) | + (1 << WM8996_GP1_DIR_SHIFT)); +} + +static struct gpio_chip wm8996_template_chip = { + .label = "wm8996", + .owner = THIS_MODULE, + .direction_output = wm8996_gpio_direction_out, + .set = wm8996_gpio_set, + .direction_input = wm8996_gpio_direction_in, + .get = wm8996_gpio_get, + .can_sleep = 1, +}; + +static void wm8996_init_gpio(struct snd_soc_codec *codec) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int ret; + + wm8996->gpio_chip = wm8996_template_chip; + wm8996->gpio_chip.ngpio = 5; + wm8996->gpio_chip.dev = codec->dev; + + if (wm8996->pdata.gpio_base) + wm8996->gpio_chip.base = wm8996->pdata.gpio_base; + else + wm8996->gpio_chip.base = -1; + + ret = gpiochip_add(&wm8996->gpio_chip); + if (ret != 0) + dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); +} + +static void wm8996_free_gpio(struct snd_soc_codec *codec) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int ret; + + ret = gpiochip_remove(&wm8996->gpio_chip); + if (ret != 0) + dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); +} +#else +static void wm8996_init_gpio(struct snd_soc_codec *codec) +{ +} + +static void wm8996_free_gpio(struct snd_soc_codec *codec) +{ +} +#endif + +/** + * wm8996_detect - Enable default WM8996 jack detection + * + * The WM8996 has advanced accessory detection support for headsets. + * This function provides a default implementation which integrates + * the majority of this functionality with minimal user configuration. + * + * This will detect headset, headphone and short circuit button and + * will also detect inverted microphone ground connections and update + * the polarity of the connections. + */ +int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, + wm8996_polarity_fn polarity_cb) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + + wm8996->jack = jack; + wm8996->detecting = true; + wm8996->polarity_cb = polarity_cb; + + if (wm8996->polarity_cb) + wm8996->polarity_cb(codec, 0); + + /* Clear discarge to avoid noise during detection */ + snd_soc_update_bits(codec, WM8996_MICBIAS_1, + WM8996_MICB1_DISCH, 0); + snd_soc_update_bits(codec, WM8996_MICBIAS_2, + WM8996_MICB2_DISCH, 0); + + /* LDO2 powers the microphones, SYSCLK clocks detection */ + snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); + snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); + + /* We start off just enabling microphone detection - even a + * plain headphone will trigger detection. + */ + snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, + WM8996_MICD_ENA, WM8996_MICD_ENA); + + /* Slowest detection rate, gives debounce for initial detection */ + snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, + WM8996_MICD_RATE_MASK, + WM8996_MICD_RATE_MASK); + + /* Enable interrupts and we're off */ + snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK, + WM8996_IM_MICD_EINT, 0); + + return 0; +} +EXPORT_SYMBOL_GPL(wm8996_detect); + +static void wm8996_micd(struct snd_soc_codec *codec) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int val, reg; + + val = snd_soc_read(codec, WM8996_MIC_DETECT_3); + + dev_dbg(codec->dev, "Microphone event: %x\n", val); + + if (!(val & WM8996_MICD_VALID)) { + dev_warn(codec->dev, "Microphone detection state invalid\n"); + return; + } + + /* No accessory, reset everything and report removal */ + if (!(val & WM8996_MICD_STS)) { + dev_dbg(codec->dev, "Jack removal detected\n"); + wm8996->jack_mic = false; + wm8996->detecting = true; + snd_soc_jack_report(wm8996->jack, 0, + SND_JACK_HEADSET | SND_JACK_BTN_0); + snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, + WM8996_MICD_RATE_MASK, + WM8996_MICD_RATE_MASK); + return; + } + + /* If the measurement is very high we've got a microphone but + * do a little debounce to account for mechanical issues. + */ + if (val & 0x400) { + dev_dbg(codec->dev, "Microphone detected\n"); + snd_soc_jack_report(wm8996->jack, SND_JACK_HEADSET, + SND_JACK_HEADSET | SND_JACK_BTN_0); + wm8996->jack_mic = true; + wm8996->detecting = false; + + /* Increase poll rate to give better responsiveness + * for buttons */ + snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, + WM8996_MICD_RATE_MASK, + 5 << WM8996_MICD_RATE_SHIFT); + } + + /* If we detected a lower impedence during initial startup + * then we probably have the wrong polarity, flip it. Don't + * do this for the lowest impedences to speed up detection of + * plain headphones. + */ + if (wm8996->detecting && (val & 0x3f0)) { + reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2); + reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | + WM8996_MICD_BIAS_SRC; + snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, + WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | + WM8996_MICD_BIAS_SRC, reg); + + if (wm8996->polarity_cb) + wm8996->polarity_cb(codec, + (reg & WM8996_MICD_SRC) != 0); + + dev_dbg(codec->dev, "Set microphone polarity to %d\n", + (reg & WM8996_MICD_SRC) != 0); + + return; + } + + /* Don't distinguish between buttons, just report any low + * impedence as BTN_0. + */ + if (val & 0x3fc) { + if (wm8996->jack_mic) { + dev_dbg(codec->dev, "Mic button detected\n"); + snd_soc_jack_report(wm8996->jack, + SND_JACK_HEADSET | SND_JACK_BTN_0, + SND_JACK_HEADSET | SND_JACK_BTN_0); + } else { + dev_dbg(codec->dev, "Headphone detected\n"); + snd_soc_jack_report(wm8996->jack, + SND_JACK_HEADPHONE, + SND_JACK_HEADSET | + SND_JACK_BTN_0); + + /* Increase the detection rate a bit for + * responsiveness. + */ + snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, + WM8996_MICD_RATE_MASK, + 7 << WM8996_MICD_RATE_SHIFT); + + wm8996->detecting = false; + } + } +} + +static irqreturn_t wm8996_irq(int irq, void *data) +{ + struct snd_soc_codec *codec = data; + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + int irq_val; + + irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2); + if (irq_val < 0) { + dev_err(codec->dev, "Failed to read IRQ status: %d\n", + irq_val); + return IRQ_NONE; + } + irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK); + + snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val); + + if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { + dev_dbg(codec->dev, "DC servo IRQ\n"); + complete(&wm8996->dcs_done); + } + + if (irq_val & WM8996_FIFOS_ERR_EINT) + dev_err(codec->dev, "Digital core FIFO error\n"); + + if (irq_val & WM8996_FLL_LOCK_EINT) { + dev_dbg(codec->dev, "FLL locked\n"); + complete(&wm8996->fll_lock); + } + + if (irq_val & WM8996_MICD_EINT) + wm8996_micd(codec); + + if (irq_val) + return IRQ_HANDLED; + else + return IRQ_NONE; +} + +static irqreturn_t wm8996_edge_irq(int irq, void *data) +{ + irqreturn_t ret = IRQ_NONE; + irqreturn_t val; + + do { + val = wm8996_irq(irq, data); + if (val != IRQ_NONE) + ret = val; + } while (val != IRQ_NONE); + + return ret; +} + +static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + struct wm8996_pdata *pdata = &wm8996->pdata; + + struct snd_kcontrol_new controls[] = { + SOC_ENUM_EXT("DSP1 EQ Mode", + wm8996->retune_mobile_enum, + wm8996_get_retune_mobile_enum, + wm8996_put_retune_mobile_enum), + SOC_ENUM_EXT("DSP2 EQ Mode", + wm8996->retune_mobile_enum, + wm8996_get_retune_mobile_enum, + wm8996_put_retune_mobile_enum), + }; + int ret, i, j; + const char **t; + + /* We need an array of texts for the enum API but the number + * of texts is likely to be less than the number of + * configurations due to the sample rate dependency of the + * configurations. */ + wm8996->num_retune_mobile_texts = 0; + wm8996->retune_mobile_texts = NULL; + for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { + for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { + if (strcmp(pdata->retune_mobile_cfgs[i].name, + wm8996->retune_mobile_texts[j]) == 0) + break; + } + + if (j != wm8996->num_retune_mobile_texts) + continue; + + /* Expand the array... */ + t = krealloc(wm8996->retune_mobile_texts, + sizeof(char *) * + (wm8996->num_retune_mobile_texts + 1), + GFP_KERNEL); + if (t == NULL) + continue; + + /* ...store the new entry... */ + t[wm8996->num_retune_mobile_texts] = + pdata->retune_mobile_cfgs[i].name; + + /* ...and remember the new version. */ + wm8996->num_retune_mobile_texts++; + wm8996->retune_mobile_texts = t; + } + + dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", + wm8996->num_retune_mobile_texts); + + wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts; + wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; + + ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); + if (ret != 0) + dev_err(codec->dev, + "Failed to add ReTune Mobile controls: %d\n", ret); +} + +static int wm8996_probe(struct snd_soc_codec *codec) +{ + int ret; + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *i2c = to_i2c_client(codec->dev); + struct snd_soc_dapm_context *dapm = &codec->dapm; + int i, irq_flags; + + wm8996->codec = codec; + + init_completion(&wm8996->dcs_done); + init_completion(&wm8996->fll_lock); + + dapm->idle_bias_off = true; + dapm->bias_level = SND_SOC_BIAS_OFF; + + ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); + if (ret != 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + goto err; + } + + for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) + wm8996->supplies[i].supply = wm8996_supply_names[i]; + + ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies), + wm8996->supplies); + if (ret != 0) { + dev_err(codec->dev, "Failed to request supplies: %d\n", ret); + goto err; + } + + wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; + wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; + wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; + wm8996->disable_nb[3].notifier_call = wm8996_regulator_event_3; + + /* This should really be moved into the regulator core */ + for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { + ret = regulator_register_notifier(wm8996->supplies[i].consumer, + &wm8996->disable_nb[i]); + if (ret != 0) { + dev_err(codec->dev, + "Failed to register regulator notifier: %d\n", + ret); + } + } + + ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), + wm8996->supplies); + if (ret != 0) { + dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); + goto err_get; + } + + if (wm8996->pdata.ldo_ena >= 0) { + gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); + msleep(5); + } + + ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET); + if (ret < 0) { + dev_err(codec->dev, "Failed to read ID register: %d\n", ret); + goto err_enable; + } + if (ret != 0x8915) { + dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret); + ret = -EINVAL; + goto err_enable; + } + + ret = snd_soc_read(codec, WM8996_CHIP_REVISION); + if (ret < 0) { + dev_err(codec->dev, "Failed to read device revision: %d\n", + ret); + goto err_enable; + } + + dev_info(codec->dev, "revision %c\n", + (ret & WM8996_CHIP_REV_MASK) + 'A'); + + if (wm8996->pdata.ldo_ena >= 0) { + gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); + } else { + ret = wm8996_reset(codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to issue reset\n"); + goto err_enable; + } + } + + codec->cache_only = true; + + /* Apply platform data settings */ + snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL, + WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, + wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | + wm8996->pdata.inr_mode); + + for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { + if (!wm8996->pdata.gpio_default[i]) + continue; + + snd_soc_write(codec, WM8996_GPIO_1 + i, + wm8996->pdata.gpio_default[i] & 0xffff); + } + + if (wm8996->pdata.spkmute_seq) + snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE, + WM8996_SPK_MUTE_ENDIAN | + WM8996_SPK_MUTE_SEQ1_MASK, + wm8996->pdata.spkmute_seq); + + snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, + WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | + WM8996_MICD_SRC, wm8996->pdata.micdet_def); + + /* Latch volume update bits */ + snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME, + WM8996_IN1_VU, WM8996_IN1_VU); + snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME, + WM8996_IN1_VU, WM8996_IN1_VU); + + snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME, + WM8996_DAC1_VU, WM8996_DAC1_VU); + snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME, + WM8996_DAC1_VU, WM8996_DAC1_VU); + snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME, + WM8996_DAC2_VU, WM8996_DAC2_VU); + snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME, + WM8996_DAC2_VU, WM8996_DAC2_VU); + + snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME, + WM8996_DAC1_VU, WM8996_DAC1_VU); + snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME, + WM8996_DAC1_VU, WM8996_DAC1_VU); + snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME, + WM8996_DAC2_VU, WM8996_DAC2_VU); + snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME, + WM8996_DAC2_VU, WM8996_DAC2_VU); + + snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME, + WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); + snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME, + WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); + snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME, + WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); + snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME, + WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); + + snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME, + WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); + snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME, + WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); + snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME, + WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); + snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME, + WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); + + /* No support currently for the underclocked TDM modes and + * pick a default TDM layout with each channel pair working with + * slots 0 and 1. */ + snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, + WM8996_AIF1RX_CHAN0_SLOTS_MASK | + WM8996_AIF1RX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, + WM8996_AIF1RX_CHAN1_SLOTS_MASK | + WM8996_AIF1RX_CHAN1_START_SLOT_MASK, + 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); + snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, + WM8996_AIF1RX_CHAN2_SLOTS_MASK | + WM8996_AIF1RX_CHAN2_START_SLOT_MASK, + 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, + WM8996_AIF1RX_CHAN3_SLOTS_MASK | + WM8996_AIF1RX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); + snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, + WM8996_AIF1RX_CHAN4_SLOTS_MASK | + WM8996_AIF1RX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, + WM8996_AIF1RX_CHAN5_SLOTS_MASK | + WM8996_AIF1RX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); + + snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, + WM8996_AIF2RX_CHAN0_SLOTS_MASK | + WM8996_AIF2RX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, + WM8996_AIF2RX_CHAN1_SLOTS_MASK | + WM8996_AIF2RX_CHAN1_START_SLOT_MASK, + 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); + + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, + WM8996_AIF1TX_CHAN0_SLOTS_MASK | + WM8996_AIF1TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, + WM8996_AIF1TX_CHAN1_SLOTS_MASK | + WM8996_AIF1TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, + WM8996_AIF1TX_CHAN2_SLOTS_MASK | + WM8996_AIF1TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, + WM8996_AIF1TX_CHAN3_SLOTS_MASK | + WM8996_AIF1TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, + WM8996_AIF1TX_CHAN4_SLOTS_MASK | + WM8996_AIF1TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, + WM8996_AIF1TX_CHAN5_SLOTS_MASK | + WM8996_AIF1TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); + + snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, + WM8996_AIF2TX_CHAN0_SLOTS_MASK | + WM8996_AIF2TX_CHAN0_START_SLOT_MASK, + 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); + snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, + WM8996_AIF2TX_CHAN1_SLOTS_MASK | + WM8996_AIF2TX_CHAN1_START_SLOT_MASK, + 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); + + if (wm8996->pdata.num_retune_mobile_cfgs) + wm8996_retune_mobile_pdata(codec); + else + snd_soc_add_controls(codec, wm8996_eq_controls, + ARRAY_SIZE(wm8996_eq_controls)); + + /* If the TX LRCLK pins are not in LRCLK mode configure the + * AIFs to source their clocks from the RX LRCLKs. + */ + if ((snd_soc_read(codec, WM8996_GPIO_1))) + snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2, + WM8996_AIF1TX_LRCLK_MODE, + WM8996_AIF1TX_LRCLK_MODE); + + if ((snd_soc_read(codec, WM8996_GPIO_2))) + snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2, + WM8996_AIF2TX_LRCLK_MODE, + WM8996_AIF2TX_LRCLK_MODE); + + regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); + + wm8996_init_gpio(codec); + + if (i2c->irq) { + if (wm8996->pdata.irq_flags) + irq_flags = wm8996->pdata.irq_flags; + else + irq_flags = IRQF_TRIGGER_LOW; + + irq_flags |= IRQF_ONESHOT; + + if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) + ret = request_threaded_irq(i2c->irq, NULL, + wm8996_edge_irq, + irq_flags, "wm8996", codec); + else + ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, + irq_flags, "wm8996", codec); + + if (ret == 0) { + /* Unmask the interrupt */ + snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, + WM8996_IM_IRQ, 0); + + /* Enable error reporting and DC servo status */ + snd_soc_update_bits(codec, + WM8996_INTERRUPT_STATUS_2_MASK, + WM8996_IM_DCS_DONE_23_EINT | + WM8996_IM_DCS_DONE_01_EINT | + WM8996_IM_FLL_LOCK_EINT | + WM8996_IM_FIFOS_ERR_EINT, + 0); + } else { + dev_err(codec->dev, "Failed to request IRQ: %d\n", + ret); + } + } + + return 0; + +err_enable: + if (wm8996->pdata.ldo_ena >= 0) + gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); + + regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); +err_get: + regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); +err: + return ret; +} + +static int wm8996_remove(struct snd_soc_codec *codec) +{ + struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *i2c = to_i2c_client(codec->dev); + int i; + + snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, + WM8996_IM_IRQ, WM8996_IM_IRQ); + + if (i2c->irq) + free_irq(i2c->irq, codec); + + wm8996_free_gpio(codec); + + for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) + regulator_unregister_notifier(wm8996->supplies[i].consumer, + &wm8996->disable_nb[i]); + regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); + + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_wm8996 = { + .probe = wm8996_probe, + .remove = wm8996_remove, + .set_bias_level = wm8996_set_bias_level, + .seq_notifier = wm8996_seq_notifier, + .reg_cache_size = WM8996_MAX_REGISTER + 1, + .reg_word_size = sizeof(u16), + .reg_cache_default = wm8996_reg, + .volatile_register = wm8996_volatile_register, + .readable_register = wm8996_readable_register, + .compress_type = SND_SOC_RBTREE_COMPRESSION, + .controls = wm8996_snd_controls, + .num_controls = ARRAY_SIZE(wm8996_snd_controls), + .dapm_widgets = wm8996_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), + .dapm_routes = wm8996_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), + .set_pll = wm8996_set_fll, +}; + +#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) +#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops wm8996_dai_ops = { + .set_fmt = wm8996_set_fmt, + .hw_params = wm8996_hw_params, + .set_sysclk = wm8996_set_sysclk, +}; + +static struct snd_soc_dai_driver wm8996_dai[] = { + { + .name = "wm8996-aif1", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = WM8996_RATES, + .formats = WM8996_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = WM8996_RATES, + .formats = WM8996_FORMATS, + }, + .ops = &wm8996_dai_ops, + }, + { + .name = "wm8996-aif2", + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8996_RATES, + .formats = WM8996_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8996_RATES, + .formats = WM8996_FORMATS, + }, + .ops = &wm8996_dai_ops, + }, +}; + +static __devinit int wm8996_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct wm8996_priv *wm8996; + int ret; + + wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL); + if (wm8996 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, wm8996); + + if (dev_get_platdata(&i2c->dev)) + memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), + sizeof(wm8996->pdata)); + + if (wm8996->pdata.ldo_ena > 0) { + ret = gpio_request_one(wm8996->pdata.ldo_ena, + GPIOF_OUT_INIT_LOW, "WM8996 ENA"); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", + wm8996->pdata.ldo_ena, ret); + goto err; + } + } + + ret = snd_soc_register_codec(&i2c->dev, + &soc_codec_dev_wm8996, wm8996_dai, + ARRAY_SIZE(wm8996_dai)); + if (ret < 0) + goto err_gpio; + + return ret; + +err_gpio: + if (wm8996->pdata.ldo_ena > 0) + gpio_free(wm8996->pdata.ldo_ena); +err: + kfree(wm8996); + + return ret; +} + +static __devexit int wm8996_i2c_remove(struct i2c_client *client) +{ + struct wm8996_priv *wm8996 = i2c_get_clientdata(client); + + snd_soc_unregister_codec(&client->dev); + if (wm8996->pdata.ldo_ena > 0) + gpio_free(wm8996->pdata.ldo_ena); + kfree(i2c_get_clientdata(client)); + return 0; +} + +static const struct i2c_device_id wm8996_i2c_id[] = { + { "wm8996", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); + +static struct i2c_driver wm8996_i2c_driver = { + .driver = { + .name = "wm8996", + .owner = THIS_MODULE, + }, + .probe = wm8996_i2c_probe, + .remove = __devexit_p(wm8996_i2c_remove), + .id_table = wm8996_i2c_id, +}; + +static int __init wm8996_modinit(void) +{ + int ret; + + ret = i2c_add_driver(&wm8996_i2c_driver); + if (ret != 0) { + printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n", + ret); + } + + return ret; +} +module_init(wm8996_modinit); + +static void __exit wm8996_exit(void) +{ + i2c_del_driver(&wm8996_i2c_driver); +} +module_exit(wm8996_exit); + +MODULE_DESCRIPTION("ASoC WM8996 driver"); +MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8996.h b/sound/soc/codecs/wm8996.h new file mode 100644 index 000000000000..0fde643194ce --- /dev/null +++ b/sound/soc/codecs/wm8996.h @@ -0,0 +1,3717 @@ +/* + * wm8996.h - WM8996 audio codec interface + * + * Copyright 2011 Wolfson Microelectronics PLC. + * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _WM8996_H +#define _WM8996_H + +#define WM8996_SYSCLK_MCLK1 1 +#define WM8996_SYSCLK_MCLK2 2 +#define WM8996_SYSCLK_FLL 3 + +#define WM8996_FLL_MCLK1 1 +#define WM8996_FLL_MCLK2 2 +#define WM8996_FLL_DACLRCLK1 3 +#define WM8996_FLL_BCLK1 4 + +typedef void (*wm8996_polarity_fn)(struct snd_soc_codec *codec, int polarity); + +int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, + wm8996_polarity_fn polarity_cb); + +/* + * Register values. + */ +#define WM8996_SOFTWARE_RESET 0x00 +#define WM8996_POWER_MANAGEMENT_1 0x01 +#define WM8996_POWER_MANAGEMENT_2 0x02 +#define WM8996_POWER_MANAGEMENT_3 0x03 +#define WM8996_POWER_MANAGEMENT_4 0x04 +#define WM8996_POWER_MANAGEMENT_5 0x05 +#define WM8996_POWER_MANAGEMENT_6 0x06 +#define WM8996_POWER_MANAGEMENT_7 0x07 +#define WM8996_POWER_MANAGEMENT_8 0x08 +#define WM8996_LEFT_LINE_INPUT_VOLUME 0x10 +#define WM8996_RIGHT_LINE_INPUT_VOLUME 0x11 +#define WM8996_LINE_INPUT_CONTROL 0x12 +#define WM8996_DAC1_HPOUT1_VOLUME 0x15 +#define WM8996_DAC2_HPOUT2_VOLUME 0x16 +#define WM8996_DAC1_LEFT_VOLUME 0x18 +#define WM8996_DAC1_RIGHT_VOLUME 0x19 +#define WM8996_DAC2_LEFT_VOLUME 0x1A +#define WM8996_DAC2_RIGHT_VOLUME 0x1B +#define WM8996_OUTPUT1_LEFT_VOLUME 0x1C +#define WM8996_OUTPUT1_RIGHT_VOLUME 0x1D +#define WM8996_OUTPUT2_LEFT_VOLUME 0x1E +#define WM8996_OUTPUT2_RIGHT_VOLUME 0x1F +#define WM8996_MICBIAS_1 0x20 +#define WM8996_MICBIAS_2 0x21 +#define WM8996_LDO_1 0x28 +#define WM8996_LDO_2 0x29 +#define WM8996_ACCESSORY_DETECT_MODE_1 0x30 +#define WM8996_ACCESSORY_DETECT_MODE_2 0x31 +#define WM8996_HEADPHONE_DETECT_1 0x34 +#define WM8996_HEADPHONE_DETECT_2 0x35 +#define WM8996_MIC_DETECT_1 0x38 +#define WM8996_MIC_DETECT_2 0x39 +#define WM8996_MIC_DETECT_3 0x3A +#define WM8996_CHARGE_PUMP_1 0x40 +#define WM8996_CHARGE_PUMP_2 0x41 +#define WM8996_DC_SERVO_1 0x50 +#define WM8996_DC_SERVO_2 0x51 +#define WM8996_DC_SERVO_3 0x52 +#define WM8996_DC_SERVO_5 0x54 +#define WM8996_DC_SERVO_6 0x55 +#define WM8996_DC_SERVO_7 0x56 +#define WM8996_DC_SERVO_READBACK_0 0x57 +#define WM8996_ANALOGUE_HP_1 0x60 +#define WM8996_ANALOGUE_HP_2 0x61 +#define WM8996_CHIP_REVISION 0x100 +#define WM8996_CONTROL_INTERFACE_1 0x101 +#define WM8996_WRITE_SEQUENCER_CTRL_1 0x110 +#define WM8996_WRITE_SEQUENCER_CTRL_2 0x111 +#define WM8996_AIF_CLOCKING_1 0x200 +#define WM8996_AIF_CLOCKING_2 0x201 +#define WM8996_CLOCKING_1 0x208 +#define WM8996_CLOCKING_2 0x209 +#define WM8996_AIF_RATE 0x210 +#define WM8996_FLL_CONTROL_1 0x220 +#define WM8996_FLL_CONTROL_2 0x221 +#define WM8996_FLL_CONTROL_3 0x222 +#define WM8996_FLL_CONTROL_4 0x223 +#define WM8996_FLL_CONTROL_5 0x224 +#define WM8996_FLL_CONTROL_6 0x225 +#define WM8996_FLL_EFS_1 0x226 +#define WM8996_FLL_EFS_2 0x227 +#define WM8996_AIF1_CONTROL 0x300 +#define WM8996_AIF1_BCLK 0x301 +#define WM8996_AIF1_TX_LRCLK_1 0x302 +#define WM8996_AIF1_TX_LRCLK_2 0x303 +#define WM8996_AIF1_RX_LRCLK_1 0x304 +#define WM8996_AIF1_RX_LRCLK_2 0x305 +#define WM8996_AIF1TX_DATA_CONFIGURATION_1 0x306 +#define WM8996_AIF1TX_DATA_CONFIGURATION_2 0x307 +#define WM8996_AIF1RX_DATA_CONFIGURATION 0x308 +#define WM8996_AIF1TX_CHANNEL_0_CONFIGURATION 0x309 +#define WM8996_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A +#define WM8996_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B +#define WM8996_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C +#define WM8996_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D +#define WM8996_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E +#define WM8996_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F +#define WM8996_AIF1RX_CHANNEL_1_CONFIGURATION 0x310 +#define WM8996_AIF1RX_CHANNEL_2_CONFIGURATION 0x311 +#define WM8996_AIF1RX_CHANNEL_3_CONFIGURATION 0x312 +#define WM8996_AIF1RX_CHANNEL_4_CONFIGURATION 0x313 +#define WM8996_AIF1RX_CHANNEL_5_CONFIGURATION 0x314 +#define WM8996_AIF1RX_MONO_CONFIGURATION 0x315 +#define WM8996_AIF1TX_TEST 0x31A +#define WM8996_AIF2_CONTROL 0x320 +#define WM8996_AIF2_BCLK 0x321 +#define WM8996_AIF2_TX_LRCLK_1 0x322 +#define WM8996_AIF2_TX_LRCLK_2 0x323 +#define WM8996_AIF2_RX_LRCLK_1 0x324 +#define WM8996_AIF2_RX_LRCLK_2 0x325 +#define WM8996_AIF2TX_DATA_CONFIGURATION_1 0x326 +#define WM8996_AIF2TX_DATA_CONFIGURATION_2 0x327 +#define WM8996_AIF2RX_DATA_CONFIGURATION 0x328 +#define WM8996_AIF2TX_CHANNEL_0_CONFIGURATION 0x329 +#define WM8996_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A +#define WM8996_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B +#define WM8996_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C +#define WM8996_AIF2RX_MONO_CONFIGURATION 0x32D +#define WM8996_AIF2TX_TEST 0x32F +#define WM8996_DSP1_TX_LEFT_VOLUME 0x400 +#define WM8996_DSP1_TX_RIGHT_VOLUME 0x401 +#define WM8996_DSP1_RX_LEFT_VOLUME 0x402 +#define WM8996_DSP1_RX_RIGHT_VOLUME 0x403 +#define WM8996_DSP1_TX_FILTERS 0x410 +#define WM8996_DSP1_RX_FILTERS_1 0x420 +#define WM8996_DSP1_RX_FILTERS_2 0x421 +#define WM8996_DSP1_DRC_1 0x440 +#define WM8996_DSP1_DRC_2 0x441 +#define WM8996_DSP1_DRC_3 0x442 +#define WM8996_DSP1_DRC_4 0x443 +#define WM8996_DSP1_DRC_5 0x444 +#define WM8996_DSP1_RX_EQ_GAINS_1 0x480 +#define WM8996_DSP1_RX_EQ_GAINS_2 0x481 +#define WM8996_DSP1_RX_EQ_BAND_1_A 0x482 +#define WM8996_DSP1_RX_EQ_BAND_1_B 0x483 +#define WM8996_DSP1_RX_EQ_BAND_1_PG 0x484 +#define WM8996_DSP1_RX_EQ_BAND_2_A 0x485 +#define WM8996_DSP1_RX_EQ_BAND_2_B 0x486 +#define WM8996_DSP1_RX_EQ_BAND_2_C 0x487 +#define WM8996_DSP1_RX_EQ_BAND_2_PG 0x488 +#define WM8996_DSP1_RX_EQ_BAND_3_A 0x489 +#define WM8996_DSP1_RX_EQ_BAND_3_B 0x48A +#define WM8996_DSP1_RX_EQ_BAND_3_C 0x48B +#define WM8996_DSP1_RX_EQ_BAND_3_PG 0x48C +#define WM8996_DSP1_RX_EQ_BAND_4_A 0x48D +#define WM8996_DSP1_RX_EQ_BAND_4_B 0x48E +#define WM8996_DSP1_RX_EQ_BAND_4_C 0x48F +#define WM8996_DSP1_RX_EQ_BAND_4_PG 0x490 +#define WM8996_DSP1_RX_EQ_BAND_5_A 0x491 +#define WM8996_DSP1_RX_EQ_BAND_5_B 0x492 +#define WM8996_DSP1_RX_EQ_BAND_5_PG 0x493 +#define WM8996_DSP2_TX_LEFT_VOLUME 0x500 +#define WM8996_DSP2_TX_RIGHT_VOLUME 0x501 +#define WM8996_DSP2_RX_LEFT_VOLUME 0x502 +#define WM8996_DSP2_RX_RIGHT_VOLUME 0x503 +#define WM8996_DSP2_TX_FILTERS 0x510 +#define WM8996_DSP2_RX_FILTERS_1 0x520 +#define WM8996_DSP2_RX_FILTERS_2 0x521 +#define WM8996_DSP2_DRC_1 0x540 +#define WM8996_DSP2_DRC_2 0x541 +#define WM8996_DSP2_DRC_3 0x542 +#define WM8996_DSP2_DRC_4 0x543 +#define WM8996_DSP2_DRC_5 0x544 +#define WM8996_DSP2_RX_EQ_GAINS_1 0x580 +#define WM8996_DSP2_RX_EQ_GAINS_2 0x581 +#define WM8996_DSP2_RX_EQ_BAND_1_A 0x582 +#define WM8996_DSP2_RX_EQ_BAND_1_B 0x583 +#define WM8996_DSP2_RX_EQ_BAND_1_PG 0x584 +#define WM8996_DSP2_RX_EQ_BAND_2_A 0x585 +#define WM8996_DSP2_RX_EQ_BAND_2_B 0x586 +#define WM8996_DSP2_RX_EQ_BAND_2_C 0x587 +#define WM8996_DSP2_RX_EQ_BAND_2_PG 0x588 +#define WM8996_DSP2_RX_EQ_BAND_3_A 0x589 +#define WM8996_DSP2_RX_EQ_BAND_3_B 0x58A +#define WM8996_DSP2_RX_EQ_BAND_3_C 0x58B +#define WM8996_DSP2_RX_EQ_BAND_3_PG 0x58C +#define WM8996_DSP2_RX_EQ_BAND_4_A 0x58D +#define WM8996_DSP2_RX_EQ_BAND_4_B 0x58E +#define WM8996_DSP2_RX_EQ_BAND_4_C 0x58F +#define WM8996_DSP2_RX_EQ_BAND_4_PG 0x590 +#define WM8996_DSP2_RX_EQ_BAND_5_A 0x591 +#define WM8996_DSP2_RX_EQ_BAND_5_B 0x592 +#define WM8996_DSP2_RX_EQ_BAND_5_PG 0x593 +#define WM8996_DAC1_MIXER_VOLUMES 0x600 +#define WM8996_DAC1_LEFT_MIXER_ROUTING 0x601 +#define WM8996_DAC1_RIGHT_MIXER_ROUTING 0x602 +#define WM8996_DAC2_MIXER_VOLUMES 0x603 +#define WM8996_DAC2_LEFT_MIXER_ROUTING 0x604 +#define WM8996_DAC2_RIGHT_MIXER_ROUTING 0x605 +#define WM8996_DSP1_TX_LEFT_MIXER_ROUTING 0x606 +#define WM8996_DSP1_TX_RIGHT_MIXER_ROUTING 0x607 +#define WM8996_DSP2_TX_LEFT_MIXER_ROUTING 0x608 +#define WM8996_DSP2_TX_RIGHT_MIXER_ROUTING 0x609 +#define WM8996_DSP_TX_MIXER_SELECT 0x60A +#define WM8996_DAC_SOFTMUTE 0x610 +#define WM8996_OVERSAMPLING 0x620 +#define WM8996_SIDETONE 0x621 +#define WM8996_GPIO_1 0x700 +#define WM8996_GPIO_2 0x701 +#define WM8996_GPIO_3 0x702 +#define WM8996_GPIO_4 0x703 +#define WM8996_GPIO_5 0x704 +#define WM8996_PULL_CONTROL_1 0x720 +#define WM8996_PULL_CONTROL_2 0x721 +#define WM8996_INTERRUPT_STATUS_1 0x730 +#define WM8996_INTERRUPT_STATUS_2 0x731 +#define WM8996_INTERRUPT_RAW_STATUS_2 0x732 +#define WM8996_INTERRUPT_STATUS_1_MASK 0x738 +#define WM8996_INTERRUPT_STATUS_2_MASK 0x739 +#define WM8996_INTERRUPT_CONTROL 0x740 +#define WM8996_LEFT_PDM_SPEAKER 0x800 +#define WM8996_RIGHT_PDM_SPEAKER 0x801 +#define WM8996_PDM_SPEAKER_MUTE_SEQUENCE 0x802 +#define WM8996_PDM_SPEAKER_VOLUME 0x803 +#define WM8996_WRITE_SEQUENCER_0 0x3000 +#define WM8996_WRITE_SEQUENCER_1 0x3001 +#define WM8996_WRITE_SEQUENCER_2 0x3002 +#define WM8996_WRITE_SEQUENCER_3 0x3003 +#define WM8996_WRITE_SEQUENCER_4 0x3004 +#define WM8996_WRITE_SEQUENCER_5 0x3005 +#define WM8996_WRITE_SEQUENCER_6 0x3006 +#define WM8996_WRITE_SEQUENCER_7 0x3007 +#define WM8996_WRITE_SEQUENCER_8 0x3008 +#define WM8996_WRITE_SEQUENCER_9 0x3009 +#define WM8996_WRITE_SEQUENCER_10 0x300A +#define WM8996_WRITE_SEQUENCER_11 0x300B +#define WM8996_WRITE_SEQUENCER_12 0x300C +#define WM8996_WRITE_SEQUENCER_13 0x300D +#define WM8996_WRITE_SEQUENCER_14 0x300E +#define WM8996_WRITE_SEQUENCER_15 0x300F +#define WM8996_WRITE_SEQUENCER_16 0x3010 +#define WM8996_WRITE_SEQUENCER_17 0x3011 +#define WM8996_WRITE_SEQUENCER_18 0x3012 +#define WM8996_WRITE_SEQUENCER_19 0x3013 +#define WM8996_WRITE_SEQUENCER_20 0x3014 +#define WM8996_WRITE_SEQUENCER_21 0x3015 +#define WM8996_WRITE_SEQUENCER_22 0x3016 +#define WM8996_WRITE_SEQUENCER_23 0x3017 +#define WM8996_WRITE_SEQUENCER_24 0x3018 +#define WM8996_WRITE_SEQUENCER_25 0x3019 +#define WM8996_WRITE_SEQUENCER_26 0x301A +#define WM8996_WRITE_SEQUENCER_27 0x301B +#define WM8996_WRITE_SEQUENCER_28 0x301C +#define WM8996_WRITE_SEQUENCER_29 0x301D +#define WM8996_WRITE_SEQUENCER_30 0x301E +#define WM8996_WRITE_SEQUENCER_31 0x301F +#define WM8996_WRITE_SEQUENCER_32 0x3020 +#define WM8996_WRITE_SEQUENCER_33 0x3021 +#define WM8996_WRITE_SEQUENCER_34 0x3022 +#define WM8996_WRITE_SEQUENCER_35 0x3023 +#define WM8996_WRITE_SEQUENCER_36 0x3024 +#define WM8996_WRITE_SEQUENCER_37 0x3025 +#define WM8996_WRITE_SEQUENCER_38 0x3026 +#define WM8996_WRITE_SEQUENCER_39 0x3027 +#define WM8996_WRITE_SEQUENCER_40 0x3028 +#define WM8996_WRITE_SEQUENCER_41 0x3029 +#define WM8996_WRITE_SEQUENCER_42 0x302A +#define WM8996_WRITE_SEQUENCER_43 0x302B +#define WM8996_WRITE_SEQUENCER_44 0x302C +#define WM8996_WRITE_SEQUENCER_45 0x302D +#define WM8996_WRITE_SEQUENCER_46 0x302E +#define WM8996_WRITE_SEQUENCER_47 0x302F +#define WM8996_WRITE_SEQUENCER_48 0x3030 +#define WM8996_WRITE_SEQUENCER_49 0x3031 +#define WM8996_WRITE_SEQUENCER_50 0x3032 +#define WM8996_WRITE_SEQUENCER_51 0x3033 +#define WM8996_WRITE_SEQUENCER_52 0x3034 +#define WM8996_WRITE_SEQUENCER_53 0x3035 +#define WM8996_WRITE_SEQUENCER_54 0x3036 +#define WM8996_WRITE_SEQUENCER_55 0x3037 +#define WM8996_WRITE_SEQUENCER_56 0x3038 +#define WM8996_WRITE_SEQUENCER_57 0x3039 +#define WM8996_WRITE_SEQUENCER_58 0x303A +#define WM8996_WRITE_SEQUENCER_59 0x303B +#define WM8996_WRITE_SEQUENCER_60 0x303C +#define WM8996_WRITE_SEQUENCER_61 0x303D +#define WM8996_WRITE_SEQUENCER_62 0x303E +#define WM8996_WRITE_SEQUENCER_63 0x303F +#define WM8996_WRITE_SEQUENCER_64 0x3040 +#define WM8996_WRITE_SEQUENCER_65 0x3041 +#define WM8996_WRITE_SEQUENCER_66 0x3042 +#define WM8996_WRITE_SEQUENCER_67 0x3043 +#define WM8996_WRITE_SEQUENCER_68 0x3044 +#define WM8996_WRITE_SEQUENCER_69 0x3045 +#define WM8996_WRITE_SEQUENCER_70 0x3046 +#define WM8996_WRITE_SEQUENCER_71 0x3047 +#define WM8996_WRITE_SEQUENCER_72 0x3048 +#define WM8996_WRITE_SEQUENCER_73 0x3049 +#define WM8996_WRITE_SEQUENCER_74 0x304A +#define WM8996_WRITE_SEQUENCER_75 0x304B +#define WM8996_WRITE_SEQUENCER_76 0x304C +#define WM8996_WRITE_SEQUENCER_77 0x304D +#define WM8996_WRITE_SEQUENCER_78 0x304E +#define WM8996_WRITE_SEQUENCER_79 0x304F +#define WM8996_WRITE_SEQUENCER_80 0x3050 +#define WM8996_WRITE_SEQUENCER_81 0x3051 +#define WM8996_WRITE_SEQUENCER_82 0x3052 +#define WM8996_WRITE_SEQUENCER_83 0x3053 +#define WM8996_WRITE_SEQUENCER_84 0x3054 +#define WM8996_WRITE_SEQUENCER_85 0x3055 +#define WM8996_WRITE_SEQUENCER_86 0x3056 +#define WM8996_WRITE_SEQUENCER_87 0x3057 +#define WM8996_WRITE_SEQUENCER_88 0x3058 +#define WM8996_WRITE_SEQUENCER_89 0x3059 +#define WM8996_WRITE_SEQUENCER_90 0x305A +#define WM8996_WRITE_SEQUENCER_91 0x305B +#define WM8996_WRITE_SEQUENCER_92 0x305C +#define WM8996_WRITE_SEQUENCER_93 0x305D +#define WM8996_WRITE_SEQUENCER_94 0x305E +#define WM8996_WRITE_SEQUENCER_95 0x305F +#define WM8996_WRITE_SEQUENCER_96 0x3060 +#define WM8996_WRITE_SEQUENCER_97 0x3061 +#define WM8996_WRITE_SEQUENCER_98 0x3062 +#define WM8996_WRITE_SEQUENCER_99 0x3063 +#define WM8996_WRITE_SEQUENCER_100 0x3064 +#define WM8996_WRITE_SEQUENCER_101 0x3065 +#define WM8996_WRITE_SEQUENCER_102 0x3066 +#define WM8996_WRITE_SEQUENCER_103 0x3067 +#define WM8996_WRITE_SEQUENCER_104 0x3068 +#define WM8996_WRITE_SEQUENCER_105 0x3069 +#define WM8996_WRITE_SEQUENCER_106 0x306A +#define WM8996_WRITE_SEQUENCER_107 0x306B +#define WM8996_WRITE_SEQUENCER_108 0x306C +#define WM8996_WRITE_SEQUENCER_109 0x306D +#define WM8996_WRITE_SEQUENCER_110 0x306E +#define WM8996_WRITE_SEQUENCER_111 0x306F +#define WM8996_WRITE_SEQUENCER_112 0x3070 +#define WM8996_WRITE_SEQUENCER_113 0x3071 +#define WM8996_WRITE_SEQUENCER_114 0x3072 +#define WM8996_WRITE_SEQUENCER_115 0x3073 +#define WM8996_WRITE_SEQUENCER_116 0x3074 +#define WM8996_WRITE_SEQUENCER_117 0x3075 +#define WM8996_WRITE_SEQUENCER_118 0x3076 +#define WM8996_WRITE_SEQUENCER_119 0x3077 +#define WM8996_WRITE_SEQUENCER_120 0x3078 +#define WM8996_WRITE_SEQUENCER_121 0x3079 +#define WM8996_WRITE_SEQUENCER_122 0x307A +#define WM8996_WRITE_SEQUENCER_123 0x307B +#define WM8996_WRITE_SEQUENCER_124 0x307C +#define WM8996_WRITE_SEQUENCER_125 0x307D +#define WM8996_WRITE_SEQUENCER_126 0x307E +#define WM8996_WRITE_SEQUENCER_127 0x307F +#define WM8996_WRITE_SEQUENCER_128 0x3080 +#define WM8996_WRITE_SEQUENCER_129 0x3081 +#define WM8996_WRITE_SEQUENCER_130 0x3082 +#define WM8996_WRITE_SEQUENCER_131 0x3083 +#define WM8996_WRITE_SEQUENCER_132 0x3084 +#define WM8996_WRITE_SEQUENCER_133 0x3085 +#define WM8996_WRITE_SEQUENCER_134 0x3086 +#define WM8996_WRITE_SEQUENCER_135 0x3087 +#define WM8996_WRITE_SEQUENCER_136 0x3088 +#define WM8996_WRITE_SEQUENCER_137 0x3089 +#define WM8996_WRITE_SEQUENCER_138 0x308A +#define WM8996_WRITE_SEQUENCER_139 0x308B +#define WM8996_WRITE_SEQUENCER_140 0x308C +#define WM8996_WRITE_SEQUENCER_141 0x308D +#define WM8996_WRITE_SEQUENCER_142 0x308E +#define WM8996_WRITE_SEQUENCER_143 0x308F +#define WM8996_WRITE_SEQUENCER_144 0x3090 +#define WM8996_WRITE_SEQUENCER_145 0x3091 +#define WM8996_WRITE_SEQUENCER_146 0x3092 +#define WM8996_WRITE_SEQUENCER_147 0x3093 +#define WM8996_WRITE_SEQUENCER_148 0x3094 +#define WM8996_WRITE_SEQUENCER_149 0x3095 +#define WM8996_WRITE_SEQUENCER_150 0x3096 +#define WM8996_WRITE_SEQUENCER_151 0x3097 +#define WM8996_WRITE_SEQUENCER_152 0x3098 +#define WM8996_WRITE_SEQUENCER_153 0x3099 +#define WM8996_WRITE_SEQUENCER_154 0x309A +#define WM8996_WRITE_SEQUENCER_155 0x309B +#define WM8996_WRITE_SEQUENCER_156 0x309C +#define WM8996_WRITE_SEQUENCER_157 0x309D +#define WM8996_WRITE_SEQUENCER_158 0x309E +#define WM8996_WRITE_SEQUENCER_159 0x309F +#define WM8996_WRITE_SEQUENCER_160 0x30A0 +#define WM8996_WRITE_SEQUENCER_161 0x30A1 +#define WM8996_WRITE_SEQUENCER_162 0x30A2 +#define WM8996_WRITE_SEQUENCER_163 0x30A3 +#define WM8996_WRITE_SEQUENCER_164 0x30A4 +#define WM8996_WRITE_SEQUENCER_165 0x30A5 +#define WM8996_WRITE_SEQUENCER_166 0x30A6 +#define WM8996_WRITE_SEQUENCER_167 0x30A7 +#define WM8996_WRITE_SEQUENCER_168 0x30A8 +#define WM8996_WRITE_SEQUENCER_169 0x30A9 +#define WM8996_WRITE_SEQUENCER_170 0x30AA +#define WM8996_WRITE_SEQUENCER_171 0x30AB +#define WM8996_WRITE_SEQUENCER_172 0x30AC +#define WM8996_WRITE_SEQUENCER_173 0x30AD +#define WM8996_WRITE_SEQUENCER_174 0x30AE +#define WM8996_WRITE_SEQUENCER_175 0x30AF +#define WM8996_WRITE_SEQUENCER_176 0x30B0 +#define WM8996_WRITE_SEQUENCER_177 0x30B1 +#define WM8996_WRITE_SEQUENCER_178 0x30B2 +#define WM8996_WRITE_SEQUENCER_179 0x30B3 +#define WM8996_WRITE_SEQUENCER_180 0x30B4 +#define WM8996_WRITE_SEQUENCER_181 0x30B5 +#define WM8996_WRITE_SEQUENCER_182 0x30B6 +#define WM8996_WRITE_SEQUENCER_183 0x30B7 +#define WM8996_WRITE_SEQUENCER_184 0x30B8 +#define WM8996_WRITE_SEQUENCER_185 0x30B9 +#define WM8996_WRITE_SEQUENCER_186 0x30BA +#define WM8996_WRITE_SEQUENCER_187 0x30BB +#define WM8996_WRITE_SEQUENCER_188 0x30BC +#define WM8996_WRITE_SEQUENCER_189 0x30BD +#define WM8996_WRITE_SEQUENCER_190 0x30BE +#define WM8996_WRITE_SEQUENCER_191 0x30BF +#define WM8996_WRITE_SEQUENCER_192 0x30C0 +#define WM8996_WRITE_SEQUENCER_193 0x30C1 +#define WM8996_WRITE_SEQUENCER_194 0x30C2 +#define WM8996_WRITE_SEQUENCER_195 0x30C3 +#define WM8996_WRITE_SEQUENCER_196 0x30C4 +#define WM8996_WRITE_SEQUENCER_197 0x30C5 +#define WM8996_WRITE_SEQUENCER_198 0x30C6 +#define WM8996_WRITE_SEQUENCER_199 0x30C7 +#define WM8996_WRITE_SEQUENCER_200 0x30C8 +#define WM8996_WRITE_SEQUENCER_201 0x30C9 +#define WM8996_WRITE_SEQUENCER_202 0x30CA +#define WM8996_WRITE_SEQUENCER_203 0x30CB +#define WM8996_WRITE_SEQUENCER_204 0x30CC +#define WM8996_WRITE_SEQUENCER_205 0x30CD +#define WM8996_WRITE_SEQUENCER_206 0x30CE +#define WM8996_WRITE_SEQUENCER_207 0x30CF +#define WM8996_WRITE_SEQUENCER_208 0x30D0 +#define WM8996_WRITE_SEQUENCER_209 0x30D1 +#define WM8996_WRITE_SEQUENCER_210 0x30D2 +#define WM8996_WRITE_SEQUENCER_211 0x30D3 +#define WM8996_WRITE_SEQUENCER_212 0x30D4 +#define WM8996_WRITE_SEQUENCER_213 0x30D5 +#define WM8996_WRITE_SEQUENCER_214 0x30D6 +#define WM8996_WRITE_SEQUENCER_215 0x30D7 +#define WM8996_WRITE_SEQUENCER_216 0x30D8 +#define WM8996_WRITE_SEQUENCER_217 0x30D9 +#define WM8996_WRITE_SEQUENCER_218 0x30DA +#define WM8996_WRITE_SEQUENCER_219 0x30DB +#define WM8996_WRITE_SEQUENCER_220 0x30DC +#define WM8996_WRITE_SEQUENCER_221 0x30DD +#define WM8996_WRITE_SEQUENCER_222 0x30DE +#define WM8996_WRITE_SEQUENCER_223 0x30DF +#define WM8996_WRITE_SEQUENCER_224 0x30E0 +#define WM8996_WRITE_SEQUENCER_225 0x30E1 +#define WM8996_WRITE_SEQUENCER_226 0x30E2 +#define WM8996_WRITE_SEQUENCER_227 0x30E3 +#define WM8996_WRITE_SEQUENCER_228 0x30E4 +#define WM8996_WRITE_SEQUENCER_229 0x30E5 +#define WM8996_WRITE_SEQUENCER_230 0x30E6 +#define WM8996_WRITE_SEQUENCER_231 0x30E7 +#define WM8996_WRITE_SEQUENCER_232 0x30E8 +#define WM8996_WRITE_SEQUENCER_233 0x30E9 +#define WM8996_WRITE_SEQUENCER_234 0x30EA +#define WM8996_WRITE_SEQUENCER_235 0x30EB +#define WM8996_WRITE_SEQUENCER_236 0x30EC +#define WM8996_WRITE_SEQUENCER_237 0x30ED +#define WM8996_WRITE_SEQUENCER_238 0x30EE +#define WM8996_WRITE_SEQUENCER_239 0x30EF +#define WM8996_WRITE_SEQUENCER_240 0x30F0 +#define WM8996_WRITE_SEQUENCER_241 0x30F1 +#define WM8996_WRITE_SEQUENCER_242 0x30F2 +#define WM8996_WRITE_SEQUENCER_243 0x30F3 +#define WM8996_WRITE_SEQUENCER_244 0x30F4 +#define WM8996_WRITE_SEQUENCER_245 0x30F5 +#define WM8996_WRITE_SEQUENCER_246 0x30F6 +#define WM8996_WRITE_SEQUENCER_247 0x30F7 +#define WM8996_WRITE_SEQUENCER_248 0x30F8 +#define WM8996_WRITE_SEQUENCER_249 0x30F9 +#define WM8996_WRITE_SEQUENCER_250 0x30FA +#define WM8996_WRITE_SEQUENCER_251 0x30FB +#define WM8996_WRITE_SEQUENCER_252 0x30FC +#define WM8996_WRITE_SEQUENCER_253 0x30FD +#define WM8996_WRITE_SEQUENCER_254 0x30FE +#define WM8996_WRITE_SEQUENCER_255 0x30FF +#define WM8996_WRITE_SEQUENCER_256 0x3100 +#define WM8996_WRITE_SEQUENCER_257 0x3101 +#define WM8996_WRITE_SEQUENCER_258 0x3102 +#define WM8996_WRITE_SEQUENCER_259 0x3103 +#define WM8996_WRITE_SEQUENCER_260 0x3104 +#define WM8996_WRITE_SEQUENCER_261 0x3105 +#define WM8996_WRITE_SEQUENCER_262 0x3106 +#define WM8996_WRITE_SEQUENCER_263 0x3107 +#define WM8996_WRITE_SEQUENCER_264 0x3108 +#define WM8996_WRITE_SEQUENCER_265 0x3109 +#define WM8996_WRITE_SEQUENCER_266 0x310A +#define WM8996_WRITE_SEQUENCER_267 0x310B +#define WM8996_WRITE_SEQUENCER_268 0x310C +#define WM8996_WRITE_SEQUENCER_269 0x310D +#define WM8996_WRITE_SEQUENCER_270 0x310E +#define WM8996_WRITE_SEQUENCER_271 0x310F +#define WM8996_WRITE_SEQUENCER_272 0x3110 +#define WM8996_WRITE_SEQUENCER_273 0x3111 +#define WM8996_WRITE_SEQUENCER_274 0x3112 +#define WM8996_WRITE_SEQUENCER_275 0x3113 +#define WM8996_WRITE_SEQUENCER_276 0x3114 +#define WM8996_WRITE_SEQUENCER_277 0x3115 +#define WM8996_WRITE_SEQUENCER_278 0x3116 +#define WM8996_WRITE_SEQUENCER_279 0x3117 +#define WM8996_WRITE_SEQUENCER_280 0x3118 +#define WM8996_WRITE_SEQUENCER_281 0x3119 +#define WM8996_WRITE_SEQUENCER_282 0x311A +#define WM8996_WRITE_SEQUENCER_283 0x311B +#define WM8996_WRITE_SEQUENCER_284 0x311C +#define WM8996_WRITE_SEQUENCER_285 0x311D +#define WM8996_WRITE_SEQUENCER_286 0x311E +#define WM8996_WRITE_SEQUENCER_287 0x311F +#define WM8996_WRITE_SEQUENCER_288 0x3120 +#define WM8996_WRITE_SEQUENCER_289 0x3121 +#define WM8996_WRITE_SEQUENCER_290 0x3122 +#define WM8996_WRITE_SEQUENCER_291 0x3123 +#define WM8996_WRITE_SEQUENCER_292 0x3124 +#define WM8996_WRITE_SEQUENCER_293 0x3125 +#define WM8996_WRITE_SEQUENCER_294 0x3126 +#define WM8996_WRITE_SEQUENCER_295 0x3127 +#define WM8996_WRITE_SEQUENCER_296 0x3128 +#define WM8996_WRITE_SEQUENCER_297 0x3129 +#define WM8996_WRITE_SEQUENCER_298 0x312A +#define WM8996_WRITE_SEQUENCER_299 0x312B +#define WM8996_WRITE_SEQUENCER_300 0x312C +#define WM8996_WRITE_SEQUENCER_301 0x312D +#define WM8996_WRITE_SEQUENCER_302 0x312E +#define WM8996_WRITE_SEQUENCER_303 0x312F +#define WM8996_WRITE_SEQUENCER_304 0x3130 +#define WM8996_WRITE_SEQUENCER_305 0x3131 +#define WM8996_WRITE_SEQUENCER_306 0x3132 +#define WM8996_WRITE_SEQUENCER_307 0x3133 +#define WM8996_WRITE_SEQUENCER_308 0x3134 +#define WM8996_WRITE_SEQUENCER_309 0x3135 +#define WM8996_WRITE_SEQUENCER_310 0x3136 +#define WM8996_WRITE_SEQUENCER_311 0x3137 +#define WM8996_WRITE_SEQUENCER_312 0x3138 +#define WM8996_WRITE_SEQUENCER_313 0x3139 +#define WM8996_WRITE_SEQUENCER_314 0x313A +#define WM8996_WRITE_SEQUENCER_315 0x313B +#define WM8996_WRITE_SEQUENCER_316 0x313C +#define WM8996_WRITE_SEQUENCER_317 0x313D +#define WM8996_WRITE_SEQUENCER_318 0x313E +#define WM8996_WRITE_SEQUENCER_319 0x313F +#define WM8996_WRITE_SEQUENCER_320 0x3140 +#define WM8996_WRITE_SEQUENCER_321 0x3141 +#define WM8996_WRITE_SEQUENCER_322 0x3142 +#define WM8996_WRITE_SEQUENCER_323 0x3143 +#define WM8996_WRITE_SEQUENCER_324 0x3144 +#define WM8996_WRITE_SEQUENCER_325 0x3145 +#define WM8996_WRITE_SEQUENCER_326 0x3146 +#define WM8996_WRITE_SEQUENCER_327 0x3147 +#define WM8996_WRITE_SEQUENCER_328 0x3148 +#define WM8996_WRITE_SEQUENCER_329 0x3149 +#define WM8996_WRITE_SEQUENCER_330 0x314A +#define WM8996_WRITE_SEQUENCER_331 0x314B +#define WM8996_WRITE_SEQUENCER_332 0x314C +#define WM8996_WRITE_SEQUENCER_333 0x314D +#define WM8996_WRITE_SEQUENCER_334 0x314E +#define WM8996_WRITE_SEQUENCER_335 0x314F +#define WM8996_WRITE_SEQUENCER_336 0x3150 +#define WM8996_WRITE_SEQUENCER_337 0x3151 +#define WM8996_WRITE_SEQUENCER_338 0x3152 +#define WM8996_WRITE_SEQUENCER_339 0x3153 +#define WM8996_WRITE_SEQUENCER_340 0x3154 +#define WM8996_WRITE_SEQUENCER_341 0x3155 +#define WM8996_WRITE_SEQUENCER_342 0x3156 +#define WM8996_WRITE_SEQUENCER_343 0x3157 +#define WM8996_WRITE_SEQUENCER_344 0x3158 +#define WM8996_WRITE_SEQUENCER_345 0x3159 +#define WM8996_WRITE_SEQUENCER_346 0x315A +#define WM8996_WRITE_SEQUENCER_347 0x315B +#define WM8996_WRITE_SEQUENCER_348 0x315C +#define WM8996_WRITE_SEQUENCER_349 0x315D +#define WM8996_WRITE_SEQUENCER_350 0x315E +#define WM8996_WRITE_SEQUENCER_351 0x315F +#define WM8996_WRITE_SEQUENCER_352 0x3160 +#define WM8996_WRITE_SEQUENCER_353 0x3161 +#define WM8996_WRITE_SEQUENCER_354 0x3162 +#define WM8996_WRITE_SEQUENCER_355 0x3163 +#define WM8996_WRITE_SEQUENCER_356 0x3164 +#define WM8996_WRITE_SEQUENCER_357 0x3165 +#define WM8996_WRITE_SEQUENCER_358 0x3166 +#define WM8996_WRITE_SEQUENCER_359 0x3167 +#define WM8996_WRITE_SEQUENCER_360 0x3168 +#define WM8996_WRITE_SEQUENCER_361 0x3169 +#define WM8996_WRITE_SEQUENCER_362 0x316A +#define WM8996_WRITE_SEQUENCER_363 0x316B +#define WM8996_WRITE_SEQUENCER_364 0x316C +#define WM8996_WRITE_SEQUENCER_365 0x316D +#define WM8996_WRITE_SEQUENCER_366 0x316E +#define WM8996_WRITE_SEQUENCER_367 0x316F +#define WM8996_WRITE_SEQUENCER_368 0x3170 +#define WM8996_WRITE_SEQUENCER_369 0x3171 +#define WM8996_WRITE_SEQUENCER_370 0x3172 +#define WM8996_WRITE_SEQUENCER_371 0x3173 +#define WM8996_WRITE_SEQUENCER_372 0x3174 +#define WM8996_WRITE_SEQUENCER_373 0x3175 +#define WM8996_WRITE_SEQUENCER_374 0x3176 +#define WM8996_WRITE_SEQUENCER_375 0x3177 +#define WM8996_WRITE_SEQUENCER_376 0x3178 +#define WM8996_WRITE_SEQUENCER_377 0x3179 +#define WM8996_WRITE_SEQUENCER_378 0x317A +#define WM8996_WRITE_SEQUENCER_379 0x317B +#define WM8996_WRITE_SEQUENCER_380 0x317C +#define WM8996_WRITE_SEQUENCER_381 0x317D +#define WM8996_WRITE_SEQUENCER_382 0x317E +#define WM8996_WRITE_SEQUENCER_383 0x317F +#define WM8996_WRITE_SEQUENCER_384 0x3180 +#define WM8996_WRITE_SEQUENCER_385 0x3181 +#define WM8996_WRITE_SEQUENCER_386 0x3182 +#define WM8996_WRITE_SEQUENCER_387 0x3183 +#define WM8996_WRITE_SEQUENCER_388 0x3184 +#define WM8996_WRITE_SEQUENCER_389 0x3185 +#define WM8996_WRITE_SEQUENCER_390 0x3186 +#define WM8996_WRITE_SEQUENCER_391 0x3187 +#define WM8996_WRITE_SEQUENCER_392 0x3188 +#define WM8996_WRITE_SEQUENCER_393 0x3189 +#define WM8996_WRITE_SEQUENCER_394 0x318A +#define WM8996_WRITE_SEQUENCER_395 0x318B +#define WM8996_WRITE_SEQUENCER_396 0x318C +#define WM8996_WRITE_SEQUENCER_397 0x318D +#define WM8996_WRITE_SEQUENCER_398 0x318E +#define WM8996_WRITE_SEQUENCER_399 0x318F +#define WM8996_WRITE_SEQUENCER_400 0x3190 +#define WM8996_WRITE_SEQUENCER_401 0x3191 +#define WM8996_WRITE_SEQUENCER_402 0x3192 +#define WM8996_WRITE_SEQUENCER_403 0x3193 +#define WM8996_WRITE_SEQUENCER_404 0x3194 +#define WM8996_WRITE_SEQUENCER_405 0x3195 +#define WM8996_WRITE_SEQUENCER_406 0x3196 +#define WM8996_WRITE_SEQUENCER_407 0x3197 +#define WM8996_WRITE_SEQUENCER_408 0x3198 +#define WM8996_WRITE_SEQUENCER_409 0x3199 +#define WM8996_WRITE_SEQUENCER_410 0x319A +#define WM8996_WRITE_SEQUENCER_411 0x319B +#define WM8996_WRITE_SEQUENCER_412 0x319C +#define WM8996_WRITE_SEQUENCER_413 0x319D +#define WM8996_WRITE_SEQUENCER_414 0x319E +#define WM8996_WRITE_SEQUENCER_415 0x319F +#define WM8996_WRITE_SEQUENCER_416 0x31A0 +#define WM8996_WRITE_SEQUENCER_417 0x31A1 +#define WM8996_WRITE_SEQUENCER_418 0x31A2 +#define WM8996_WRITE_SEQUENCER_419 0x31A3 +#define WM8996_WRITE_SEQUENCER_420 0x31A4 +#define WM8996_WRITE_SEQUENCER_421 0x31A5 +#define WM8996_WRITE_SEQUENCER_422 0x31A6 +#define WM8996_WRITE_SEQUENCER_423 0x31A7 +#define WM8996_WRITE_SEQUENCER_424 0x31A8 +#define WM8996_WRITE_SEQUENCER_425 0x31A9 +#define WM8996_WRITE_SEQUENCER_426 0x31AA +#define WM8996_WRITE_SEQUENCER_427 0x31AB +#define WM8996_WRITE_SEQUENCER_428 0x31AC +#define WM8996_WRITE_SEQUENCER_429 0x31AD +#define WM8996_WRITE_SEQUENCER_430 0x31AE +#define WM8996_WRITE_SEQUENCER_431 0x31AF +#define WM8996_WRITE_SEQUENCER_432 0x31B0 +#define WM8996_WRITE_SEQUENCER_433 0x31B1 +#define WM8996_WRITE_SEQUENCER_434 0x31B2 +#define WM8996_WRITE_SEQUENCER_435 0x31B3 +#define WM8996_WRITE_SEQUENCER_436 0x31B4 +#define WM8996_WRITE_SEQUENCER_437 0x31B5 +#define WM8996_WRITE_SEQUENCER_438 0x31B6 +#define WM8996_WRITE_SEQUENCER_439 0x31B7 +#define WM8996_WRITE_SEQUENCER_440 0x31B8 +#define WM8996_WRITE_SEQUENCER_441 0x31B9 +#define WM8996_WRITE_SEQUENCER_442 0x31BA +#define WM8996_WRITE_SEQUENCER_443 0x31BB +#define WM8996_WRITE_SEQUENCER_444 0x31BC +#define WM8996_WRITE_SEQUENCER_445 0x31BD +#define WM8996_WRITE_SEQUENCER_446 0x31BE +#define WM8996_WRITE_SEQUENCER_447 0x31BF +#define WM8996_WRITE_SEQUENCER_448 0x31C0 +#define WM8996_WRITE_SEQUENCER_449 0x31C1 +#define WM8996_WRITE_SEQUENCER_450 0x31C2 +#define WM8996_WRITE_SEQUENCER_451 0x31C3 +#define WM8996_WRITE_SEQUENCER_452 0x31C4 +#define WM8996_WRITE_SEQUENCER_453 0x31C5 +#define WM8996_WRITE_SEQUENCER_454 0x31C6 +#define WM8996_WRITE_SEQUENCER_455 0x31C7 +#define WM8996_WRITE_SEQUENCER_456 0x31C8 +#define WM8996_WRITE_SEQUENCER_457 0x31C9 +#define WM8996_WRITE_SEQUENCER_458 0x31CA +#define WM8996_WRITE_SEQUENCER_459 0x31CB +#define WM8996_WRITE_SEQUENCER_460 0x31CC +#define WM8996_WRITE_SEQUENCER_461 0x31CD +#define WM8996_WRITE_SEQUENCER_462 0x31CE +#define WM8996_WRITE_SEQUENCER_463 0x31CF +#define WM8996_WRITE_SEQUENCER_464 0x31D0 +#define WM8996_WRITE_SEQUENCER_465 0x31D1 +#define WM8996_WRITE_SEQUENCER_466 0x31D2 +#define WM8996_WRITE_SEQUENCER_467 0x31D3 +#define WM8996_WRITE_SEQUENCER_468 0x31D4 +#define WM8996_WRITE_SEQUENCER_469 0x31D5 +#define WM8996_WRITE_SEQUENCER_470 0x31D6 +#define WM8996_WRITE_SEQUENCER_471 0x31D7 +#define WM8996_WRITE_SEQUENCER_472 0x31D8 +#define WM8996_WRITE_SEQUENCER_473 0x31D9 +#define WM8996_WRITE_SEQUENCER_474 0x31DA +#define WM8996_WRITE_SEQUENCER_475 0x31DB +#define WM8996_WRITE_SEQUENCER_476 0x31DC +#define WM8996_WRITE_SEQUENCER_477 0x31DD +#define WM8996_WRITE_SEQUENCER_478 0x31DE +#define WM8996_WRITE_SEQUENCER_479 0x31DF +#define WM8996_WRITE_SEQUENCER_480 0x31E0 +#define WM8996_WRITE_SEQUENCER_481 0x31E1 +#define WM8996_WRITE_SEQUENCER_482 0x31E2 +#define WM8996_WRITE_SEQUENCER_483 0x31E3 +#define WM8996_WRITE_SEQUENCER_484 0x31E4 +#define WM8996_WRITE_SEQUENCER_485 0x31E5 +#define WM8996_WRITE_SEQUENCER_486 0x31E6 +#define WM8996_WRITE_SEQUENCER_487 0x31E7 +#define WM8996_WRITE_SEQUENCER_488 0x31E8 +#define WM8996_WRITE_SEQUENCER_489 0x31E9 +#define WM8996_WRITE_SEQUENCER_490 0x31EA +#define WM8996_WRITE_SEQUENCER_491 0x31EB +#define WM8996_WRITE_SEQUENCER_492 0x31EC +#define WM8996_WRITE_SEQUENCER_493 0x31ED +#define WM8996_WRITE_SEQUENCER_494 0x31EE +#define WM8996_WRITE_SEQUENCER_495 0x31EF +#define WM8996_WRITE_SEQUENCER_496 0x31F0 +#define WM8996_WRITE_SEQUENCER_497 0x31F1 +#define WM8996_WRITE_SEQUENCER_498 0x31F2 +#define WM8996_WRITE_SEQUENCER_499 0x31F3 +#define WM8996_WRITE_SEQUENCER_500 0x31F4 +#define WM8996_WRITE_SEQUENCER_501 0x31F5 +#define WM8996_WRITE_SEQUENCER_502 0x31F6 +#define WM8996_WRITE_SEQUENCER_503 0x31F7 +#define WM8996_WRITE_SEQUENCER_504 0x31F8 +#define WM8996_WRITE_SEQUENCER_505 0x31F9 +#define WM8996_WRITE_SEQUENCER_506 0x31FA +#define WM8996_WRITE_SEQUENCER_507 0x31FB +#define WM8996_WRITE_SEQUENCER_508 0x31FC +#define WM8996_WRITE_SEQUENCER_509 0x31FD +#define WM8996_WRITE_SEQUENCER_510 0x31FE +#define WM8996_WRITE_SEQUENCER_511 0x31FF + +#define WM8996_REGISTER_COUNT 706 +#define WM8996_MAX_REGISTER 0x31FF + +/* + * Field Definitions. + */ + +/* + * R0 (0x00) - Software Reset + */ +#define WM8996_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ +#define WM8996_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ +#define WM8996_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ + +/* + * R1 (0x01) - Power Management (1) + */ +#define WM8996_MICB2_ENA 0x0200 /* MICB2_ENA */ +#define WM8996_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ +#define WM8996_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ +#define WM8996_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ +#define WM8996_MICB1_ENA 0x0100 /* MICB1_ENA */ +#define WM8996_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ +#define WM8996_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ +#define WM8996_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ +#define WM8996_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ +#define WM8996_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ +#define WM8996_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ +#define WM8996_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ +#define WM8996_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ +#define WM8996_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ +#define WM8996_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ +#define WM8996_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ +#define WM8996_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ +#define WM8996_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ +#define WM8996_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ +#define WM8996_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ +#define WM8996_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ +#define WM8996_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ +#define WM8996_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ +#define WM8996_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ +#define WM8996_BG_ENA 0x0001 /* BG_ENA */ +#define WM8996_BG_ENA_MASK 0x0001 /* BG_ENA */ +#define WM8996_BG_ENA_SHIFT 0 /* BG_ENA */ +#define WM8996_BG_ENA_WIDTH 1 /* BG_ENA */ + +/* + * R2 (0x02) - Power Management (2) + */ +#define WM8996_OPCLK_ENA 0x0800 /* OPCLK_ENA */ +#define WM8996_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ +#define WM8996_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ +#define WM8996_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ +#define WM8996_INL_ENA 0x0020 /* INL_ENA */ +#define WM8996_INL_ENA_MASK 0x0020 /* INL_ENA */ +#define WM8996_INL_ENA_SHIFT 5 /* INL_ENA */ +#define WM8996_INL_ENA_WIDTH 1 /* INL_ENA */ +#define WM8996_INR_ENA 0x0010 /* INR_ENA */ +#define WM8996_INR_ENA_MASK 0x0010 /* INR_ENA */ +#define WM8996_INR_ENA_SHIFT 4 /* INR_ENA */ +#define WM8996_INR_ENA_WIDTH 1 /* INR_ENA */ +#define WM8996_LDO2_ENA 0x0002 /* LDO2_ENA */ +#define WM8996_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ +#define WM8996_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ +#define WM8996_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ + +/* + * R3 (0x03) - Power Management (3) + */ +#define WM8996_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */ +#define WM8996_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */ +#define WM8996_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */ +#define WM8996_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */ +#define WM8996_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */ +#define WM8996_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */ +#define WM8996_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */ +#define WM8996_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */ +#define WM8996_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */ +#define WM8996_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */ +#define WM8996_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */ +#define WM8996_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */ +#define WM8996_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */ +#define WM8996_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */ +#define WM8996_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */ +#define WM8996_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */ +#define WM8996_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ +#define WM8996_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ +#define WM8996_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ +#define WM8996_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ +#define WM8996_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ +#define WM8996_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ +#define WM8996_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ +#define WM8996_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ +#define WM8996_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ +#define WM8996_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ +#define WM8996_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ +#define WM8996_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ +#define WM8996_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ +#define WM8996_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ +#define WM8996_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ +#define WM8996_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ +#define WM8996_ADCL_ENA 0x0002 /* ADCL_ENA */ +#define WM8996_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ +#define WM8996_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ +#define WM8996_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ +#define WM8996_ADCR_ENA 0x0001 /* ADCR_ENA */ +#define WM8996_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ +#define WM8996_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ +#define WM8996_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ + +/* + * R4 (0x04) - Power Management (4) + */ +#define WM8996_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */ +#define WM8996_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */ +#define WM8996_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */ +#define WM8996_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */ +#define WM8996_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */ +#define WM8996_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */ +#define WM8996_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */ +#define WM8996_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */ +#define WM8996_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */ +#define WM8996_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */ +#define WM8996_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */ +#define WM8996_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */ +#define WM8996_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */ +#define WM8996_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */ +#define WM8996_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */ +#define WM8996_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */ +#define WM8996_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */ +#define WM8996_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */ +#define WM8996_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */ +#define WM8996_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */ +#define WM8996_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */ +#define WM8996_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */ +#define WM8996_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */ +#define WM8996_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */ +#define WM8996_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */ +#define WM8996_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */ +#define WM8996_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */ +#define WM8996_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */ +#define WM8996_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */ +#define WM8996_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */ +#define WM8996_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */ +#define WM8996_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */ + +/* + * R5 (0x05) - Power Management (5) + */ +#define WM8996_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */ +#define WM8996_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */ +#define WM8996_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */ +#define WM8996_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */ +#define WM8996_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */ +#define WM8996_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */ +#define WM8996_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */ +#define WM8996_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */ +#define WM8996_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */ +#define WM8996_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */ +#define WM8996_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */ +#define WM8996_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */ +#define WM8996_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */ +#define WM8996_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */ +#define WM8996_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */ +#define WM8996_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */ +#define WM8996_DAC2L_ENA 0x0008 /* DAC2L_ENA */ +#define WM8996_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ +#define WM8996_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ +#define WM8996_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ +#define WM8996_DAC2R_ENA 0x0004 /* DAC2R_ENA */ +#define WM8996_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ +#define WM8996_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ +#define WM8996_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ +#define WM8996_DAC1L_ENA 0x0002 /* DAC1L_ENA */ +#define WM8996_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ +#define WM8996_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ +#define WM8996_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ +#define WM8996_DAC1R_ENA 0x0001 /* DAC1R_ENA */ +#define WM8996_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ +#define WM8996_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ +#define WM8996_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ + +/* + * R6 (0x06) - Power Management (6) + */ +#define WM8996_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */ +#define WM8996_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */ +#define WM8996_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */ +#define WM8996_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */ +#define WM8996_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */ +#define WM8996_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */ +#define WM8996_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */ +#define WM8996_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */ +#define WM8996_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */ +#define WM8996_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */ +#define WM8996_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */ +#define WM8996_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */ +#define WM8996_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */ +#define WM8996_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */ +#define WM8996_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */ +#define WM8996_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */ +#define WM8996_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */ +#define WM8996_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */ +#define WM8996_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */ +#define WM8996_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */ +#define WM8996_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */ +#define WM8996_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */ +#define WM8996_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */ +#define WM8996_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */ +#define WM8996_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */ +#define WM8996_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */ +#define WM8996_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */ +#define WM8996_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */ +#define WM8996_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */ +#define WM8996_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */ +#define WM8996_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */ +#define WM8996_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */ + +/* + * R7 (0x07) - Power Management (7) + */ +#define WM8996_DMIC2_FN 0x0200 /* DMIC2_FN */ +#define WM8996_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */ +#define WM8996_DMIC2_FN_SHIFT 9 /* DMIC2_FN */ +#define WM8996_DMIC2_FN_WIDTH 1 /* DMIC2_FN */ +#define WM8996_DMIC1_FN 0x0100 /* DMIC1_FN */ +#define WM8996_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */ +#define WM8996_DMIC1_FN_SHIFT 8 /* DMIC1_FN */ +#define WM8996_DMIC1_FN_WIDTH 1 /* DMIC1_FN */ +#define WM8996_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */ +#define WM8996_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */ +#define WM8996_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */ +#define WM8996_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */ +#define WM8996_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */ +#define WM8996_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */ +#define WM8996_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */ +#define WM8996_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */ +#define WM8996_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */ +#define WM8996_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */ +#define WM8996_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */ +#define WM8996_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */ +#define WM8996_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */ +#define WM8996_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */ +#define WM8996_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */ +#define WM8996_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */ +#define WM8996_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */ +#define WM8996_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */ +#define WM8996_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */ +#define WM8996_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */ +#define WM8996_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */ +#define WM8996_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */ + +/* + * R8 (0x08) - Power Management (8) + */ +#define WM8996_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */ +#define WM8996_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */ +#define WM8996_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */ +#define WM8996_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */ +#define WM8996_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */ +#define WM8996_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */ +#define WM8996_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */ +#define WM8996_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */ +#define WM8996_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */ +#define WM8996_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */ +#define WM8996_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */ + +/* + * R16 (0x10) - Left Line Input Volume + */ +#define WM8996_IN1_VU 0x0080 /* IN1_VU */ +#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */ +#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */ +#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */ +#define WM8996_IN1L_ZC 0x0020 /* IN1L_ZC */ +#define WM8996_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ +#define WM8996_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ +#define WM8996_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ +#define WM8996_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ +#define WM8996_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ +#define WM8996_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ + +/* + * R17 (0x11) - Right Line Input Volume + */ +#define WM8996_IN1_VU 0x0080 /* IN1_VU */ +#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */ +#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */ +#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */ +#define WM8996_IN1R_ZC 0x0020 /* IN1R_ZC */ +#define WM8996_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ +#define WM8996_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ +#define WM8996_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ +#define WM8996_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ +#define WM8996_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ +#define WM8996_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ + +/* + * R18 (0x12) - Line Input Control + */ +#define WM8996_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */ +#define WM8996_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */ +#define WM8996_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */ +#define WM8996_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */ +#define WM8996_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */ +#define WM8996_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */ + +/* + * R21 (0x15) - DAC1 HPOUT1 Volume + */ +#define WM8996_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */ +#define WM8996_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ +#define WM8996_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ +#define WM8996_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */ +#define WM8996_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */ +#define WM8996_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */ + +/* + * R22 (0x16) - DAC2 HPOUT2 Volume + */ +#define WM8996_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */ +#define WM8996_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ +#define WM8996_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ +#define WM8996_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */ +#define WM8996_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */ +#define WM8996_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */ + +/* + * R24 (0x18) - DAC1 Left Volume + */ +#define WM8996_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ +#define WM8996_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ +#define WM8996_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ +#define WM8996_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ +#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ +#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ +#define WM8996_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ +#define WM8996_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ +#define WM8996_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ + +/* + * R25 (0x19) - DAC1 Right Volume + */ +#define WM8996_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ +#define WM8996_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ +#define WM8996_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ +#define WM8996_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ +#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ +#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ +#define WM8996_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ +#define WM8996_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ +#define WM8996_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ + +/* + * R26 (0x1A) - DAC2 Left Volume + */ +#define WM8996_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ +#define WM8996_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ +#define WM8996_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ +#define WM8996_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ +#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ +#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ +#define WM8996_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ +#define WM8996_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ +#define WM8996_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ + +/* + * R27 (0x1B) - DAC2 Right Volume + */ +#define WM8996_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ +#define WM8996_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ +#define WM8996_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ +#define WM8996_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ +#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ +#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ +#define WM8996_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ +#define WM8996_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ +#define WM8996_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ + +/* + * R28 (0x1C) - Output1 Left Volume + */ +#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ +#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ +#define WM8996_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ +#define WM8996_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ +#define WM8996_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ +#define WM8996_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ +#define WM8996_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */ +#define WM8996_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */ +#define WM8996_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */ + +/* + * R29 (0x1D) - Output1 Right Volume + */ +#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ +#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ +#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ +#define WM8996_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ +#define WM8996_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ +#define WM8996_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ +#define WM8996_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ +#define WM8996_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */ +#define WM8996_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */ +#define WM8996_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */ + +/* + * R30 (0x1E) - Output2 Left Volume + */ +#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ +#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ +#define WM8996_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */ +#define WM8996_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */ +#define WM8996_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */ +#define WM8996_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ +#define WM8996_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */ +#define WM8996_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */ +#define WM8996_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */ + +/* + * R31 (0x1F) - Output2 Right Volume + */ +#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ +#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ +#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ +#define WM8996_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */ +#define WM8996_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */ +#define WM8996_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */ +#define WM8996_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ +#define WM8996_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */ +#define WM8996_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */ +#define WM8996_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */ + +/* + * R32 (0x20) - MICBIAS (1) + */ +#define WM8996_MICB1_RATE 0x0020 /* MICB1_RATE */ +#define WM8996_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ +#define WM8996_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ +#define WM8996_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ +#define WM8996_MICB1_MODE 0x0010 /* MICB1_MODE */ +#define WM8996_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */ +#define WM8996_MICB1_MODE_SHIFT 4 /* MICB1_MODE */ +#define WM8996_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ +#define WM8996_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */ +#define WM8996_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */ +#define WM8996_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */ +#define WM8996_MICB1_DISCH 0x0001 /* MICB1_DISCH */ +#define WM8996_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ +#define WM8996_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ +#define WM8996_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ + +/* + * R33 (0x21) - MICBIAS (2) + */ +#define WM8996_MICB2_RATE 0x0020 /* MICB2_RATE */ +#define WM8996_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ +#define WM8996_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ +#define WM8996_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ +#define WM8996_MICB2_MODE 0x0010 /* MICB2_MODE */ +#define WM8996_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */ +#define WM8996_MICB2_MODE_SHIFT 4 /* MICB2_MODE */ +#define WM8996_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ +#define WM8996_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */ +#define WM8996_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */ +#define WM8996_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */ +#define WM8996_MICB2_DISCH 0x0001 /* MICB2_DISCH */ +#define WM8996_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ +#define WM8996_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ +#define WM8996_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ + +/* + * R40 (0x28) - LDO 1 + */ +#define WM8996_LDO1_MODE 0x0020 /* LDO1_MODE */ +#define WM8996_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ +#define WM8996_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ +#define WM8996_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ +#define WM8996_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ +#define WM8996_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ +#define WM8996_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ +#define WM8996_LDO1_DISCH 0x0001 /* LDO1_DISCH */ +#define WM8996_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ +#define WM8996_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ +#define WM8996_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ + +/* + * R41 (0x29) - LDO 2 + */ +#define WM8996_LDO2_MODE 0x0020 /* LDO2_MODE */ +#define WM8996_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ +#define WM8996_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ +#define WM8996_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ +#define WM8996_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ +#define WM8996_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ +#define WM8996_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ +#define WM8996_LDO2_DISCH 0x0001 /* LDO2_DISCH */ +#define WM8996_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ +#define WM8996_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ +#define WM8996_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ + +/* + * R48 (0x30) - Accessory Detect Mode 1 + */ +#define WM8996_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ +#define WM8996_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ +#define WM8996_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ + +/* + * R49 (0x31) - Accessory Detect Mode 2 + */ +#define WM8996_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */ +#define WM8996_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */ +#define WM8996_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */ +#define WM8996_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */ +#define WM8996_MICD_SRC 0x0002 /* MICD_SRC */ +#define WM8996_MICD_SRC_MASK 0x0002 /* MICD_SRC */ +#define WM8996_MICD_SRC_SHIFT 1 /* MICD_SRC */ +#define WM8996_MICD_SRC_WIDTH 1 /* MICD_SRC */ +#define WM8996_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */ +#define WM8996_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */ +#define WM8996_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */ +#define WM8996_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */ + +/* + * R52 (0x34) - Headphone Detect 1 + */ +#define WM8996_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ +#define WM8996_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ +#define WM8996_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ +#define WM8996_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ +#define WM8996_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ +#define WM8996_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ +#define WM8996_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ +#define WM8996_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ +#define WM8996_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ +#define WM8996_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ +#define WM8996_HP_POLL 0x0001 /* HP_POLL */ +#define WM8996_HP_POLL_MASK 0x0001 /* HP_POLL */ +#define WM8996_HP_POLL_SHIFT 0 /* HP_POLL */ +#define WM8996_HP_POLL_WIDTH 1 /* HP_POLL */ + +/* + * R53 (0x35) - Headphone Detect 2 + */ +#define WM8996_HP_DONE 0x0080 /* HP_DONE */ +#define WM8996_HP_DONE_MASK 0x0080 /* HP_DONE */ +#define WM8996_HP_DONE_SHIFT 7 /* HP_DONE */ +#define WM8996_HP_DONE_WIDTH 1 /* HP_DONE */ +#define WM8996_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ +#define WM8996_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ +#define WM8996_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ + +/* + * R56 (0x38) - Mic Detect 1 + */ +#define WM8996_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ +#define WM8996_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ +#define WM8996_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ +#define WM8996_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ +#define WM8996_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ +#define WM8996_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ +#define WM8996_MICD_DBTIME 0x0002 /* MICD_DBTIME */ +#define WM8996_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ +#define WM8996_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ +#define WM8996_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ +#define WM8996_MICD_ENA 0x0001 /* MICD_ENA */ +#define WM8996_MICD_ENA_MASK 0x0001 /* MICD_ENA */ +#define WM8996_MICD_ENA_SHIFT 0 /* MICD_ENA */ +#define WM8996_MICD_ENA_WIDTH 1 /* MICD_ENA */ + +/* + * R57 (0x39) - Mic Detect 2 + */ +#define WM8996_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ +#define WM8996_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ +#define WM8996_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ + +/* + * R58 (0x3A) - Mic Detect 3 + */ +#define WM8996_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ +#define WM8996_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ +#define WM8996_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ +#define WM8996_MICD_VALID 0x0002 /* MICD_VALID */ +#define WM8996_MICD_VALID_MASK 0x0002 /* MICD_VALID */ +#define WM8996_MICD_VALID_SHIFT 1 /* MICD_VALID */ +#define WM8996_MICD_VALID_WIDTH 1 /* MICD_VALID */ +#define WM8996_MICD_STS 0x0001 /* MICD_STS */ +#define WM8996_MICD_STS_MASK 0x0001 /* MICD_STS */ +#define WM8996_MICD_STS_SHIFT 0 /* MICD_STS */ +#define WM8996_MICD_STS_WIDTH 1 /* MICD_STS */ + +/* + * R64 (0x40) - Charge Pump (1) + */ +#define WM8996_CP_ENA 0x8000 /* CP_ENA */ +#define WM8996_CP_ENA_MASK 0x8000 /* CP_ENA */ +#define WM8996_CP_ENA_SHIFT 15 /* CP_ENA */ +#define WM8996_CP_ENA_WIDTH 1 /* CP_ENA */ + +/* + * R65 (0x41) - Charge Pump (2) + */ +#define WM8996_CP_DISCH 0x8000 /* CP_DISCH */ +#define WM8996_CP_DISCH_MASK 0x8000 /* CP_DISCH */ +#define WM8996_CP_DISCH_SHIFT 15 /* CP_DISCH */ +#define WM8996_CP_DISCH_WIDTH 1 /* CP_DISCH */ + +/* + * R80 (0x50) - DC Servo (1) + */ +#define WM8996_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ +#define WM8996_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ +#define WM8996_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ +#define WM8996_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ +#define WM8996_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ +#define WM8996_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ +#define WM8996_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ +#define WM8996_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ +#define WM8996_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ +#define WM8996_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ +#define WM8996_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ +#define WM8996_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ +#define WM8996_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ +#define WM8996_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ +#define WM8996_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ +#define WM8996_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ + +/* + * R81 (0x51) - DC Servo (2) + */ +#define WM8996_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ +#define WM8996_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ +#define WM8996_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ +#define WM8996_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ +#define WM8996_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ +#define WM8996_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ +#define WM8996_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ +#define WM8996_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ +#define WM8996_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ +#define WM8996_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ +#define WM8996_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ +#define WM8996_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ +#define WM8996_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ +#define WM8996_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ +#define WM8996_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ +#define WM8996_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ +#define WM8996_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ +#define WM8996_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ +#define WM8996_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ +#define WM8996_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ +#define WM8996_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ +#define WM8996_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ +#define WM8996_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ +#define WM8996_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ +#define WM8996_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ +#define WM8996_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ +#define WM8996_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ +#define WM8996_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ +#define WM8996_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ +#define WM8996_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ +#define WM8996_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ +#define WM8996_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ +#define WM8996_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ +#define WM8996_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ +#define WM8996_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ +#define WM8996_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ +#define WM8996_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ +#define WM8996_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ +#define WM8996_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ +#define WM8996_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ +#define WM8996_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ +#define WM8996_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ +#define WM8996_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ +#define WM8996_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ +#define WM8996_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ +#define WM8996_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ +#define WM8996_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ +#define WM8996_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ +#define WM8996_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ +#define WM8996_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ +#define WM8996_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ +#define WM8996_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ +#define WM8996_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ +#define WM8996_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ +#define WM8996_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ +#define WM8996_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ +#define WM8996_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ +#define WM8996_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ +#define WM8996_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ +#define WM8996_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ +#define WM8996_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ +#define WM8996_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ +#define WM8996_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ +#define WM8996_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ + +/* + * R82 (0x52) - DC Servo (3) + */ +#define WM8996_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ +#define WM8996_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ +#define WM8996_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ +#define WM8996_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ +#define WM8996_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ +#define WM8996_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ + +/* + * R84 (0x54) - DC Servo (5) + */ +#define WM8996_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ +#define WM8996_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ +#define WM8996_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ +#define WM8996_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ +#define WM8996_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ +#define WM8996_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ + +/* + * R85 (0x55) - DC Servo (6) + */ +#define WM8996_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ +#define WM8996_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ +#define WM8996_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ +#define WM8996_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ +#define WM8996_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ +#define WM8996_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ + +/* + * R86 (0x56) - DC Servo (7) + */ +#define WM8996_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ +#define WM8996_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ +#define WM8996_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ +#define WM8996_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ +#define WM8996_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ +#define WM8996_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ + +/* + * R87 (0x57) - DC Servo Readback 0 + */ +#define WM8996_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ +#define WM8996_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ +#define WM8996_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ +#define WM8996_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ +#define WM8996_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ +#define WM8996_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ +#define WM8996_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ +#define WM8996_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ +#define WM8996_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ + +/* + * R96 (0x60) - Analogue HP (1) + */ +#define WM8996_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ +#define WM8996_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ +#define WM8996_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ +#define WM8996_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ +#define WM8996_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ +#define WM8996_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ +#define WM8996_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ +#define WM8996_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ +#define WM8996_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ +#define WM8996_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ +#define WM8996_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ +#define WM8996_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ +#define WM8996_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ +#define WM8996_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ +#define WM8996_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ +#define WM8996_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ +#define WM8996_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ +#define WM8996_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ +#define WM8996_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ +#define WM8996_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ +#define WM8996_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ +#define WM8996_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ +#define WM8996_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ +#define WM8996_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ + +/* + * R97 (0x61) - Analogue HP (2) + */ +#define WM8996_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ +#define WM8996_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ +#define WM8996_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ +#define WM8996_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ +#define WM8996_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ +#define WM8996_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ +#define WM8996_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ +#define WM8996_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ +#define WM8996_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ +#define WM8996_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ +#define WM8996_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ +#define WM8996_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ +#define WM8996_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ +#define WM8996_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ +#define WM8996_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ +#define WM8996_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ +#define WM8996_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ +#define WM8996_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ +#define WM8996_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ +#define WM8996_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ +#define WM8996_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ +#define WM8996_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ +#define WM8996_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ +#define WM8996_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ + +/* + * R256 (0x100) - Chip Revision + */ +#define WM8996_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ +#define WM8996_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ +#define WM8996_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ + +/* + * R257 (0x101) - Control Interface (1) + */ +#define WM8996_AUTO_INC 0x0004 /* AUTO_INC */ +#define WM8996_AUTO_INC_MASK 0x0004 /* AUTO_INC */ +#define WM8996_AUTO_INC_SHIFT 2 /* AUTO_INC */ +#define WM8996_AUTO_INC_WIDTH 1 /* AUTO_INC */ + +/* + * R272 (0x110) - Write Sequencer Ctrl (1) + */ +#define WM8996_WSEQ_ENA 0x8000 /* WSEQ_ENA */ +#define WM8996_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ +#define WM8996_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ +#define WM8996_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ +#define WM8996_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ +#define WM8996_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ +#define WM8996_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ +#define WM8996_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ +#define WM8996_WSEQ_START 0x0100 /* WSEQ_START */ +#define WM8996_WSEQ_START_MASK 0x0100 /* WSEQ_START */ +#define WM8996_WSEQ_START_SHIFT 8 /* WSEQ_START */ +#define WM8996_WSEQ_START_WIDTH 1 /* WSEQ_START */ +#define WM8996_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ +#define WM8996_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ +#define WM8996_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ + +/* + * R273 (0x111) - Write Sequencer Ctrl (2) + */ +#define WM8996_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ +#define WM8996_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ +#define WM8996_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ +#define WM8996_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ +#define WM8996_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ +#define WM8996_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ +#define WM8996_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ + +/* + * R512 (0x200) - AIF Clocking (1) + */ +#define WM8996_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */ +#define WM8996_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */ +#define WM8996_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */ +#define WM8996_SYSCLK_INV 0x0004 /* SYSCLK_INV */ +#define WM8996_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */ +#define WM8996_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */ +#define WM8996_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */ +#define WM8996_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */ +#define WM8996_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */ +#define WM8996_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */ +#define WM8996_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */ +#define WM8996_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */ +#define WM8996_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */ +#define WM8996_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */ +#define WM8996_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ + +/* + * R513 (0x201) - AIF Clocking (2) + */ +#define WM8996_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */ +#define WM8996_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */ +#define WM8996_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */ +#define WM8996_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */ +#define WM8996_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */ +#define WM8996_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */ + +/* + * R520 (0x208) - Clocking (1) + */ +#define WM8996_LFCLK_ENA 0x0020 /* LFCLK_ENA */ +#define WM8996_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ +#define WM8996_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ +#define WM8996_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ +#define WM8996_TOCLK_ENA 0x0010 /* TOCLK_ENA */ +#define WM8996_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ +#define WM8996_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ +#define WM8996_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ +#define WM8996_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */ +#define WM8996_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */ +#define WM8996_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */ +#define WM8996_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */ +#define WM8996_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ +#define WM8996_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ +#define WM8996_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ +#define WM8996_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ + +/* + * R521 (0x209) - Clocking (2) + */ +#define WM8996_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ +#define WM8996_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ +#define WM8996_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ +#define WM8996_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ +#define WM8996_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ +#define WM8996_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ +#define WM8996_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ +#define WM8996_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ +#define WM8996_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ + +/* + * R528 (0x210) - AIF Rate + */ +#define WM8996_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */ +#define WM8996_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */ +#define WM8996_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */ +#define WM8996_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */ + +/* + * R544 (0x220) - FLL Control (1) + */ +#define WM8996_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ +#define WM8996_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ +#define WM8996_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ +#define WM8996_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ +#define WM8996_FLL_ENA 0x0001 /* FLL_ENA */ +#define WM8996_FLL_ENA_MASK 0x0001 /* FLL_ENA */ +#define WM8996_FLL_ENA_SHIFT 0 /* FLL_ENA */ +#define WM8996_FLL_ENA_WIDTH 1 /* FLL_ENA */ + +/* + * R545 (0x221) - FLL Control (2) + */ +#define WM8996_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ +#define WM8996_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ +#define WM8996_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ +#define WM8996_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ +#define WM8996_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ +#define WM8996_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ + +/* + * R546 (0x222) - FLL Control (3) + */ +#define WM8996_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ +#define WM8996_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ +#define WM8996_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ + +/* + * R547 (0x223) - FLL Control (4) + */ +#define WM8996_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ +#define WM8996_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ +#define WM8996_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ +#define WM8996_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */ +#define WM8996_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */ +#define WM8996_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */ + +/* + * R548 (0x224) - FLL Control (5) + */ +#define WM8996_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */ +#define WM8996_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */ +#define WM8996_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */ +#define WM8996_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */ +#define WM8996_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */ +#define WM8996_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */ +#define WM8996_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ +#define WM8996_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */ +#define WM8996_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */ +#define WM8996_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */ +#define WM8996_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */ +#define WM8996_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */ +#define WM8996_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */ +#define WM8996_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */ +#define WM8996_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */ +#define WM8996_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */ +#define WM8996_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */ + +/* + * R549 (0x225) - FLL Control (6) + */ +#define WM8996_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */ +#define WM8996_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */ +#define WM8996_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */ +#define WM8996_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */ +#define WM8996_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */ +#define WM8996_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */ +#define WM8996_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */ + +/* + * R550 (0x226) - FLL EFS 1 + */ +#define WM8996_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ +#define WM8996_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ +#define WM8996_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ + +/* + * R551 (0x227) - FLL EFS 2 + */ +#define WM8996_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */ +#define WM8996_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */ +#define WM8996_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */ +#define WM8996_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ +#define WM8996_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ +#define WM8996_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ +#define WM8996_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ + +/* + * R768 (0x300) - AIF1 Control + */ +#define WM8996_AIF1_TRI 0x0004 /* AIF1_TRI */ +#define WM8996_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */ +#define WM8996_AIF1_TRI_SHIFT 2 /* AIF1_TRI */ +#define WM8996_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ +#define WM8996_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */ +#define WM8996_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */ +#define WM8996_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */ + +/* + * R769 (0x301) - AIF1 BCLK + */ +#define WM8996_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */ +#define WM8996_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */ +#define WM8996_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */ +#define WM8996_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ +#define WM8996_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */ +#define WM8996_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */ +#define WM8996_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */ +#define WM8996_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ +#define WM8996_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */ +#define WM8996_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */ +#define WM8996_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */ +#define WM8996_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ +#define WM8996_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ +#define WM8996_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ +#define WM8996_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ + +/* + * R770 (0x302) - AIF1 TX LRCLK(1) + */ +#define WM8996_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */ +#define WM8996_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */ +#define WM8996_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */ + +/* + * R771 (0x303) - AIF1 TX LRCLK(2) + */ +#define WM8996_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */ +#define WM8996_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */ +#define WM8996_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */ +#define WM8996_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */ +#define WM8996_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ +#define WM8996_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ +#define WM8996_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ +#define WM8996_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ +#define WM8996_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ +#define WM8996_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ +#define WM8996_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ +#define WM8996_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ +#define WM8996_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ +#define WM8996_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ +#define WM8996_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ +#define WM8996_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ + +/* + * R772 (0x304) - AIF1 RX LRCLK(1) + */ +#define WM8996_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */ +#define WM8996_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */ +#define WM8996_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */ + +/* + * R773 (0x305) - AIF1 RX LRCLK(2) + */ +#define WM8996_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ +#define WM8996_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ +#define WM8996_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ +#define WM8996_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ +#define WM8996_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ +#define WM8996_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ +#define WM8996_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ +#define WM8996_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ +#define WM8996_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ +#define WM8996_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ +#define WM8996_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ +#define WM8996_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ + +/* + * R774 (0x306) - AIF1TX Data Configuration (1) + */ +#define WM8996_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */ +#define WM8996_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */ +#define WM8996_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */ +#define WM8996_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ +#define WM8996_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ +#define WM8996_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ + +/* + * R775 (0x307) - AIF1TX Data Configuration (2) + */ +#define WM8996_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */ +#define WM8996_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */ +#define WM8996_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */ +#define WM8996_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ + +/* + * R776 (0x308) - AIF1RX Data Configuration + */ +#define WM8996_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */ +#define WM8996_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */ +#define WM8996_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */ +#define WM8996_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ +#define WM8996_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ +#define WM8996_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ + +/* + * R777 (0x309) - AIF1TX Channel 0 Configuration + */ +#define WM8996_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */ +#define WM8996_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */ +#define WM8996_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */ +#define WM8996_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */ +#define WM8996_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ + +/* + * R778 (0x30A) - AIF1TX Channel 1 Configuration + */ +#define WM8996_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */ +#define WM8996_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */ +#define WM8996_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */ +#define WM8996_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */ +#define WM8996_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ + +/* + * R779 (0x30B) - AIF1TX Channel 2 Configuration + */ +#define WM8996_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */ +#define WM8996_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */ +#define WM8996_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */ +#define WM8996_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */ +#define WM8996_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ + +/* + * R780 (0x30C) - AIF1TX Channel 3 Configuration + */ +#define WM8996_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */ +#define WM8996_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */ +#define WM8996_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */ +#define WM8996_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */ +#define WM8996_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ + +/* + * R781 (0x30D) - AIF1TX Channel 4 Configuration + */ +#define WM8996_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */ +#define WM8996_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */ +#define WM8996_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */ +#define WM8996_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */ +#define WM8996_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ + +/* + * R782 (0x30E) - AIF1TX Channel 5 Configuration + */ +#define WM8996_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */ +#define WM8996_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */ +#define WM8996_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */ +#define WM8996_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */ +#define WM8996_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */ +#define WM8996_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */ +#define WM8996_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ +#define WM8996_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ + +/* + * R783 (0x30F) - AIF1RX Channel 0 Configuration + */ +#define WM8996_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */ +#define WM8996_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */ +#define WM8996_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */ +#define WM8996_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */ +#define WM8996_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ + +/* + * R784 (0x310) - AIF1RX Channel 1 Configuration + */ +#define WM8996_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */ +#define WM8996_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */ +#define WM8996_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */ +#define WM8996_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */ +#define WM8996_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ + +/* + * R785 (0x311) - AIF1RX Channel 2 Configuration + */ +#define WM8996_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */ +#define WM8996_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */ +#define WM8996_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */ +#define WM8996_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */ +#define WM8996_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ + +/* + * R786 (0x312) - AIF1RX Channel 3 Configuration + */ +#define WM8996_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */ +#define WM8996_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */ +#define WM8996_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */ +#define WM8996_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */ +#define WM8996_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ + +/* + * R787 (0x313) - AIF1RX Channel 4 Configuration + */ +#define WM8996_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */ +#define WM8996_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */ +#define WM8996_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */ +#define WM8996_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */ +#define WM8996_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ + +/* + * R788 (0x314) - AIF1RX Channel 5 Configuration + */ +#define WM8996_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */ +#define WM8996_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */ +#define WM8996_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */ +#define WM8996_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */ +#define WM8996_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */ +#define WM8996_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */ +#define WM8996_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ +#define WM8996_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ + +/* + * R789 (0x315) - AIF1RX Mono Configuration + */ +#define WM8996_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ +#define WM8996_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ +#define WM8996_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */ +#define WM8996_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */ +#define WM8996_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ +#define WM8996_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ +#define WM8996_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */ +#define WM8996_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */ +#define WM8996_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ +#define WM8996_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ +#define WM8996_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */ +#define WM8996_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */ + +/* + * R794 (0x31A) - AIF1TX Test + */ +#define WM8996_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */ +#define WM8996_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */ +#define WM8996_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */ +#define WM8996_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */ +#define WM8996_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */ +#define WM8996_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */ +#define WM8996_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */ +#define WM8996_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */ +#define WM8996_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */ +#define WM8996_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */ +#define WM8996_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */ +#define WM8996_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */ + +/* + * R800 (0x320) - AIF2 Control + */ +#define WM8996_AIF2_TRI 0x0004 /* AIF2_TRI */ +#define WM8996_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */ +#define WM8996_AIF2_TRI_SHIFT 2 /* AIF2_TRI */ +#define WM8996_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ +#define WM8996_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */ +#define WM8996_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */ +#define WM8996_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */ + +/* + * R801 (0x321) - AIF2 BCLK + */ +#define WM8996_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */ +#define WM8996_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */ +#define WM8996_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */ +#define WM8996_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ +#define WM8996_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */ +#define WM8996_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */ +#define WM8996_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */ +#define WM8996_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ +#define WM8996_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */ +#define WM8996_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */ +#define WM8996_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */ +#define WM8996_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ +#define WM8996_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */ +#define WM8996_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */ +#define WM8996_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */ + +/* + * R802 (0x322) - AIF2 TX LRCLK(1) + */ +#define WM8996_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */ +#define WM8996_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */ +#define WM8996_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */ + +/* + * R803 (0x323) - AIF2 TX LRCLK(2) + */ +#define WM8996_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */ +#define WM8996_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */ +#define WM8996_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */ +#define WM8996_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */ +#define WM8996_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ +#define WM8996_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ +#define WM8996_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ +#define WM8996_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ +#define WM8996_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ +#define WM8996_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ +#define WM8996_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ +#define WM8996_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ +#define WM8996_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ +#define WM8996_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ +#define WM8996_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ +#define WM8996_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ + +/* + * R804 (0x324) - AIF2 RX LRCLK(1) + */ +#define WM8996_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */ +#define WM8996_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */ +#define WM8996_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */ + +/* + * R805 (0x325) - AIF2 RX LRCLK(2) + */ +#define WM8996_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ +#define WM8996_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ +#define WM8996_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ +#define WM8996_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ +#define WM8996_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ +#define WM8996_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ +#define WM8996_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ +#define WM8996_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ +#define WM8996_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ +#define WM8996_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ +#define WM8996_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ +#define WM8996_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ + +/* + * R806 (0x326) - AIF2TX Data Configuration (1) + */ +#define WM8996_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */ +#define WM8996_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */ +#define WM8996_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */ +#define WM8996_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ +#define WM8996_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ +#define WM8996_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ + +/* + * R807 (0x327) - AIF2TX Data Configuration (2) + */ +#define WM8996_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */ +#define WM8996_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */ +#define WM8996_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */ +#define WM8996_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ + +/* + * R808 (0x328) - AIF2RX Data Configuration + */ +#define WM8996_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */ +#define WM8996_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */ +#define WM8996_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */ +#define WM8996_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ +#define WM8996_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ +#define WM8996_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ + +/* + * R809 (0x329) - AIF2TX Channel 0 Configuration + */ +#define WM8996_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */ +#define WM8996_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */ +#define WM8996_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */ +#define WM8996_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */ +#define WM8996_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ + +/* + * R810 (0x32A) - AIF2TX Channel 1 Configuration + */ +#define WM8996_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */ +#define WM8996_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */ +#define WM8996_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */ +#define WM8996_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */ +#define WM8996_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ + +/* + * R811 (0x32B) - AIF2RX Channel 0 Configuration + */ +#define WM8996_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */ +#define WM8996_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */ +#define WM8996_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */ +#define WM8996_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */ +#define WM8996_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */ +#define WM8996_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */ +#define WM8996_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ +#define WM8996_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ + +/* + * R812 (0x32C) - AIF2RX Channel 1 Configuration + */ +#define WM8996_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */ +#define WM8996_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */ +#define WM8996_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */ +#define WM8996_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */ +#define WM8996_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */ +#define WM8996_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */ +#define WM8996_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ +#define WM8996_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ + +/* + * R813 (0x32D) - AIF2RX Mono Configuration + */ +#define WM8996_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ +#define WM8996_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ +#define WM8996_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */ +#define WM8996_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */ + +/* + * R815 (0x32F) - AIF2TX Test + */ +#define WM8996_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */ +#define WM8996_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */ +#define WM8996_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */ +#define WM8996_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */ + +/* + * R1024 (0x400) - DSP1 TX Left Volume + */ +#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */ +#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ +#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ +#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ +#define WM8996_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */ +#define WM8996_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */ +#define WM8996_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */ + +/* + * R1025 (0x401) - DSP1 TX Right Volume + */ +#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */ +#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ +#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ +#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ +#define WM8996_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */ +#define WM8996_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */ +#define WM8996_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */ + +/* + * R1026 (0x402) - DSP1 RX Left Volume + */ +#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */ +#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ +#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ +#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ +#define WM8996_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */ +#define WM8996_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */ +#define WM8996_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */ + +/* + * R1027 (0x403) - DSP1 RX Right Volume + */ +#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */ +#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ +#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ +#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ +#define WM8996_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */ +#define WM8996_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */ +#define WM8996_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */ + +/* + * R1040 (0x410) - DSP1 TX Filters + */ +#define WM8996_DSP1TX_NF 0x2000 /* DSP1TX_NF */ +#define WM8996_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */ +#define WM8996_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */ +#define WM8996_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */ +#define WM8996_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */ +#define WM8996_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */ +#define WM8996_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */ +#define WM8996_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */ +#define WM8996_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */ +#define WM8996_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */ +#define WM8996_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */ +#define WM8996_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */ +#define WM8996_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */ +#define WM8996_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */ +#define WM8996_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */ +#define WM8996_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */ +#define WM8996_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */ +#define WM8996_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */ + +/* + * R1056 (0x420) - DSP1 RX Filters (1) + */ +#define WM8996_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */ +#define WM8996_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */ +#define WM8996_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */ +#define WM8996_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */ +#define WM8996_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */ +#define WM8996_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */ +#define WM8996_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */ +#define WM8996_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */ +#define WM8996_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */ +#define WM8996_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */ +#define WM8996_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */ +#define WM8996_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */ +#define WM8996_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */ +#define WM8996_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */ +#define WM8996_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */ +#define WM8996_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */ + +/* + * R1057 (0x421) - DSP1 RX Filters (2) + */ +#define WM8996_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */ +#define WM8996_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */ +#define WM8996_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */ +#define WM8996_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */ +#define WM8996_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */ +#define WM8996_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */ +#define WM8996_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */ + +/* + * R1088 (0x440) - DSP1 DRC (1) + */ +#define WM8996_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */ +#define WM8996_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */ +#define WM8996_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */ +#define WM8996_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */ +#define WM8996_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */ +#define WM8996_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */ +#define WM8996_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */ +#define WM8996_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */ +#define WM8996_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */ +#define WM8996_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */ +#define WM8996_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */ +#define WM8996_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */ +#define WM8996_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */ +#define WM8996_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */ +#define WM8996_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */ +#define WM8996_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */ +#define WM8996_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */ +#define WM8996_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */ +#define WM8996_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ +#define WM8996_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ +#define WM8996_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */ +#define WM8996_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */ +#define WM8996_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */ +#define WM8996_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */ +#define WM8996_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */ +#define WM8996_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */ +#define WM8996_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */ +#define WM8996_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */ +#define WM8996_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */ +#define WM8996_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */ +#define WM8996_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */ +#define WM8996_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */ +#define WM8996_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */ +#define WM8996_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */ +#define WM8996_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */ +#define WM8996_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */ +#define WM8996_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */ +#define WM8996_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */ +#define WM8996_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */ +#define WM8996_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */ +#define WM8996_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */ +#define WM8996_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */ + +/* + * R1089 (0x441) - DSP1 DRC (2) + */ +#define WM8996_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */ +#define WM8996_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */ +#define WM8996_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */ +#define WM8996_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */ +#define WM8996_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */ +#define WM8996_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */ +#define WM8996_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */ +#define WM8996_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */ +#define WM8996_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */ +#define WM8996_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */ +#define WM8996_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */ +#define WM8996_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */ + +/* + * R1090 (0x442) - DSP1 DRC (3) + */ +#define WM8996_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */ +#define WM8996_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */ +#define WM8996_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */ +#define WM8996_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */ +#define WM8996_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */ +#define WM8996_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */ +#define WM8996_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */ +#define WM8996_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */ +#define WM8996_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */ +#define WM8996_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */ +#define WM8996_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */ +#define WM8996_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */ +#define WM8996_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */ +#define WM8996_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */ +#define WM8996_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */ +#define WM8996_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */ +#define WM8996_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */ +#define WM8996_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */ + +/* + * R1091 (0x443) - DSP1 DRC (4) + */ +#define WM8996_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */ +#define WM8996_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */ +#define WM8996_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */ +#define WM8996_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */ +#define WM8996_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */ +#define WM8996_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */ + +/* + * R1092 (0x444) - DSP1 DRC (5) + */ +#define WM8996_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */ +#define WM8996_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */ +#define WM8996_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */ +#define WM8996_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */ +#define WM8996_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */ +#define WM8996_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */ + +/* + * R1152 (0x480) - DSP1 RX EQ Gains (1) + */ +#define WM8996_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */ +#define WM8996_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */ +#define WM8996_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */ +#define WM8996_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */ +#define WM8996_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */ +#define WM8996_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */ +#define WM8996_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */ +#define WM8996_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */ +#define WM8996_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */ +#define WM8996_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */ +#define WM8996_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */ +#define WM8996_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */ +#define WM8996_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */ + +/* + * R1153 (0x481) - DSP1 RX EQ Gains (2) + */ +#define WM8996_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */ +#define WM8996_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */ +#define WM8996_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */ +#define WM8996_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */ +#define WM8996_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */ +#define WM8996_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */ + +/* + * R1154 (0x482) - DSP1 RX EQ Band 1 A + */ +#define WM8996_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */ + +/* + * R1155 (0x483) - DSP1 RX EQ Band 1 B + */ +#define WM8996_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */ + +/* + * R1156 (0x484) - DSP1 RX EQ Band 1 PG + */ +#define WM8996_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */ + +/* + * R1157 (0x485) - DSP1 RX EQ Band 2 A + */ +#define WM8996_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */ + +/* + * R1158 (0x486) - DSP1 RX EQ Band 2 B + */ +#define WM8996_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */ + +/* + * R1159 (0x487) - DSP1 RX EQ Band 2 C + */ +#define WM8996_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */ + +/* + * R1160 (0x488) - DSP1 RX EQ Band 2 PG + */ +#define WM8996_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */ + +/* + * R1161 (0x489) - DSP1 RX EQ Band 3 A + */ +#define WM8996_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */ + +/* + * R1162 (0x48A) - DSP1 RX EQ Band 3 B + */ +#define WM8996_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */ + +/* + * R1163 (0x48B) - DSP1 RX EQ Band 3 C + */ +#define WM8996_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */ + +/* + * R1164 (0x48C) - DSP1 RX EQ Band 3 PG + */ +#define WM8996_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */ + +/* + * R1165 (0x48D) - DSP1 RX EQ Band 4 A + */ +#define WM8996_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */ + +/* + * R1166 (0x48E) - DSP1 RX EQ Band 4 B + */ +#define WM8996_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */ + +/* + * R1167 (0x48F) - DSP1 RX EQ Band 4 C + */ +#define WM8996_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */ + +/* + * R1168 (0x490) - DSP1 RX EQ Band 4 PG + */ +#define WM8996_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */ + +/* + * R1169 (0x491) - DSP1 RX EQ Band 5 A + */ +#define WM8996_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */ +#define WM8996_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */ + +/* + * R1170 (0x492) - DSP1 RX EQ Band 5 B + */ +#define WM8996_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */ +#define WM8996_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */ + +/* + * R1171 (0x493) - DSP1 RX EQ Band 5 PG + */ +#define WM8996_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */ +#define WM8996_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */ + +/* + * R1280 (0x500) - DSP2 TX Left Volume + */ +#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */ +#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ +#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ +#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ +#define WM8996_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */ +#define WM8996_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */ +#define WM8996_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */ + +/* + * R1281 (0x501) - DSP2 TX Right Volume + */ +#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */ +#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ +#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ +#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ +#define WM8996_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */ +#define WM8996_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */ +#define WM8996_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */ + +/* + * R1282 (0x502) - DSP2 RX Left Volume + */ +#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */ +#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ +#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ +#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ +#define WM8996_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */ +#define WM8996_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */ +#define WM8996_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */ + +/* + * R1283 (0x503) - DSP2 RX Right Volume + */ +#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */ +#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ +#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ +#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ +#define WM8996_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */ +#define WM8996_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */ +#define WM8996_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */ + +/* + * R1296 (0x510) - DSP2 TX Filters + */ +#define WM8996_DSP2TX_NF 0x2000 /* DSP2TX_NF */ +#define WM8996_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */ +#define WM8996_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */ +#define WM8996_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */ +#define WM8996_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */ +#define WM8996_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */ +#define WM8996_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */ +#define WM8996_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */ +#define WM8996_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */ +#define WM8996_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */ +#define WM8996_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */ +#define WM8996_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */ +#define WM8996_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */ +#define WM8996_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */ +#define WM8996_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */ +#define WM8996_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */ +#define WM8996_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */ +#define WM8996_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */ + +/* + * R1312 (0x520) - DSP2 RX Filters (1) + */ +#define WM8996_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */ +#define WM8996_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */ +#define WM8996_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */ +#define WM8996_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */ +#define WM8996_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */ +#define WM8996_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */ +#define WM8996_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */ +#define WM8996_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */ +#define WM8996_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */ +#define WM8996_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */ +#define WM8996_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */ +#define WM8996_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */ +#define WM8996_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */ +#define WM8996_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */ +#define WM8996_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */ +#define WM8996_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */ + +/* + * R1313 (0x521) - DSP2 RX Filters (2) + */ +#define WM8996_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */ +#define WM8996_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */ +#define WM8996_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */ +#define WM8996_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */ +#define WM8996_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */ +#define WM8996_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */ +#define WM8996_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */ + +/* + * R1344 (0x540) - DSP2 DRC (1) + */ +#define WM8996_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */ +#define WM8996_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */ +#define WM8996_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */ +#define WM8996_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */ +#define WM8996_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */ +#define WM8996_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */ +#define WM8996_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */ +#define WM8996_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */ +#define WM8996_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */ +#define WM8996_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */ +#define WM8996_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */ +#define WM8996_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */ +#define WM8996_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */ +#define WM8996_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */ +#define WM8996_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */ +#define WM8996_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */ +#define WM8996_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */ +#define WM8996_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */ +#define WM8996_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ +#define WM8996_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ +#define WM8996_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */ +#define WM8996_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */ +#define WM8996_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */ +#define WM8996_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */ +#define WM8996_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */ +#define WM8996_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */ +#define WM8996_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */ +#define WM8996_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */ +#define WM8996_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */ +#define WM8996_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */ +#define WM8996_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */ +#define WM8996_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */ +#define WM8996_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */ +#define WM8996_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */ +#define WM8996_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */ +#define WM8996_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */ +#define WM8996_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */ +#define WM8996_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */ +#define WM8996_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */ +#define WM8996_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */ +#define WM8996_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */ +#define WM8996_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */ + +/* + * R1345 (0x541) - DSP2 DRC (2) + */ +#define WM8996_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */ +#define WM8996_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */ +#define WM8996_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */ +#define WM8996_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */ +#define WM8996_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */ +#define WM8996_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */ +#define WM8996_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */ +#define WM8996_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */ +#define WM8996_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */ +#define WM8996_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */ +#define WM8996_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */ +#define WM8996_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */ + +/* + * R1346 (0x542) - DSP2 DRC (3) + */ +#define WM8996_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */ +#define WM8996_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */ +#define WM8996_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */ +#define WM8996_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */ +#define WM8996_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */ +#define WM8996_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */ +#define WM8996_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */ +#define WM8996_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */ +#define WM8996_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */ +#define WM8996_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */ +#define WM8996_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */ +#define WM8996_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */ +#define WM8996_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */ +#define WM8996_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */ +#define WM8996_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */ +#define WM8996_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */ +#define WM8996_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */ +#define WM8996_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */ + +/* + * R1347 (0x543) - DSP2 DRC (4) + */ +#define WM8996_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */ +#define WM8996_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */ +#define WM8996_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */ +#define WM8996_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */ +#define WM8996_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */ +#define WM8996_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */ + +/* + * R1348 (0x544) - DSP2 DRC (5) + */ +#define WM8996_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */ +#define WM8996_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */ +#define WM8996_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */ +#define WM8996_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */ +#define WM8996_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */ +#define WM8996_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */ + +/* + * R1408 (0x580) - DSP2 RX EQ Gains (1) + */ +#define WM8996_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */ +#define WM8996_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */ +#define WM8996_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */ +#define WM8996_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */ +#define WM8996_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */ +#define WM8996_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */ +#define WM8996_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */ +#define WM8996_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */ +#define WM8996_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */ +#define WM8996_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */ +#define WM8996_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */ +#define WM8996_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */ +#define WM8996_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */ + +/* + * R1409 (0x581) - DSP2 RX EQ Gains (2) + */ +#define WM8996_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */ +#define WM8996_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */ +#define WM8996_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */ +#define WM8996_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */ +#define WM8996_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */ +#define WM8996_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */ + +/* + * R1410 (0x582) - DSP2 RX EQ Band 1 A + */ +#define WM8996_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */ + +/* + * R1411 (0x583) - DSP2 RX EQ Band 1 B + */ +#define WM8996_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */ + +/* + * R1412 (0x584) - DSP2 RX EQ Band 1 PG + */ +#define WM8996_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */ + +/* + * R1413 (0x585) - DSP2 RX EQ Band 2 A + */ +#define WM8996_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */ + +/* + * R1414 (0x586) - DSP2 RX EQ Band 2 B + */ +#define WM8996_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */ + +/* + * R1415 (0x587) - DSP2 RX EQ Band 2 C + */ +#define WM8996_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */ + +/* + * R1416 (0x588) - DSP2 RX EQ Band 2 PG + */ +#define WM8996_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */ + +/* + * R1417 (0x589) - DSP2 RX EQ Band 3 A + */ +#define WM8996_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */ + +/* + * R1418 (0x58A) - DSP2 RX EQ Band 3 B + */ +#define WM8996_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */ + +/* + * R1419 (0x58B) - DSP2 RX EQ Band 3 C + */ +#define WM8996_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */ + +/* + * R1420 (0x58C) - DSP2 RX EQ Band 3 PG + */ +#define WM8996_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */ + +/* + * R1421 (0x58D) - DSP2 RX EQ Band 4 A + */ +#define WM8996_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */ + +/* + * R1422 (0x58E) - DSP2 RX EQ Band 4 B + */ +#define WM8996_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */ + +/* + * R1423 (0x58F) - DSP2 RX EQ Band 4 C + */ +#define WM8996_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */ + +/* + * R1424 (0x590) - DSP2 RX EQ Band 4 PG + */ +#define WM8996_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */ + +/* + * R1425 (0x591) - DSP2 RX EQ Band 5 A + */ +#define WM8996_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */ +#define WM8996_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */ + +/* + * R1426 (0x592) - DSP2 RX EQ Band 5 B + */ +#define WM8996_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */ +#define WM8996_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */ + +/* + * R1427 (0x593) - DSP2 RX EQ Band 5 PG + */ +#define WM8996_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */ +#define WM8996_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */ + +/* + * R1536 (0x600) - DAC1 Mixer Volumes + */ +#define WM8996_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ +#define WM8996_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ +#define WM8996_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ +#define WM8996_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ +#define WM8996_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ +#define WM8996_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ + +/* + * R1537 (0x601) - DAC1 Left Mixer Routing + */ +#define WM8996_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ +#define WM8996_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ +#define WM8996_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ +#define WM8996_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ +#define WM8996_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ +#define WM8996_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ +#define WM8996_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ +#define WM8996_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ +#define WM8996_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */ +#define WM8996_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */ +#define WM8996_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */ +#define WM8996_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */ +#define WM8996_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */ +#define WM8996_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */ +#define WM8996_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */ +#define WM8996_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */ + +/* + * R1538 (0x602) - DAC1 Right Mixer Routing + */ +#define WM8996_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ +#define WM8996_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ +#define WM8996_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ +#define WM8996_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ +#define WM8996_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ +#define WM8996_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ +#define WM8996_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ +#define WM8996_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ +#define WM8996_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */ +#define WM8996_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */ +#define WM8996_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */ +#define WM8996_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */ +#define WM8996_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */ +#define WM8996_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */ +#define WM8996_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */ +#define WM8996_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */ + +/* + * R1539 (0x603) - DAC2 Mixer Volumes + */ +#define WM8996_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ +#define WM8996_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ +#define WM8996_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ +#define WM8996_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ +#define WM8996_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ +#define WM8996_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ + +/* + * R1540 (0x604) - DAC2 Left Mixer Routing + */ +#define WM8996_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ +#define WM8996_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ +#define WM8996_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ +#define WM8996_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ +#define WM8996_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ +#define WM8996_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ +#define WM8996_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ +#define WM8996_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ +#define WM8996_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */ +#define WM8996_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */ +#define WM8996_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */ +#define WM8996_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */ +#define WM8996_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */ +#define WM8996_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */ +#define WM8996_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */ +#define WM8996_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */ + +/* + * R1541 (0x605) - DAC2 Right Mixer Routing + */ +#define WM8996_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ +#define WM8996_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ +#define WM8996_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ +#define WM8996_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ +#define WM8996_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ +#define WM8996_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ +#define WM8996_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ +#define WM8996_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ +#define WM8996_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */ +#define WM8996_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */ +#define WM8996_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */ +#define WM8996_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */ +#define WM8996_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */ +#define WM8996_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */ +#define WM8996_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */ +#define WM8996_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */ + +/* + * R1542 (0x606) - DSP1 TX Left Mixer Routing + */ +#define WM8996_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */ +#define WM8996_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */ +#define WM8996_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */ +#define WM8996_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */ +#define WM8996_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */ +#define WM8996_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */ +#define WM8996_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */ +#define WM8996_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */ + +/* + * R1543 (0x607) - DSP1 TX Right Mixer Routing + */ +#define WM8996_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */ +#define WM8996_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */ +#define WM8996_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */ +#define WM8996_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */ +#define WM8996_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */ +#define WM8996_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */ +#define WM8996_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */ +#define WM8996_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */ + +/* + * R1544 (0x608) - DSP2 TX Left Mixer Routing + */ +#define WM8996_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */ +#define WM8996_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */ +#define WM8996_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */ +#define WM8996_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */ +#define WM8996_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */ +#define WM8996_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */ +#define WM8996_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */ +#define WM8996_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */ + +/* + * R1545 (0x609) - DSP2 TX Right Mixer Routing + */ +#define WM8996_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */ +#define WM8996_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */ +#define WM8996_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */ +#define WM8996_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */ +#define WM8996_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */ +#define WM8996_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */ +#define WM8996_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */ +#define WM8996_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */ + +/* + * R1546 (0x60A) - DSP TX Mixer Select + */ +#define WM8996_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */ +#define WM8996_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */ +#define WM8996_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */ +#define WM8996_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */ + +/* + * R1552 (0x610) - DAC Softmute + */ +#define WM8996_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ +#define WM8996_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ +#define WM8996_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ +#define WM8996_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ +#define WM8996_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ +#define WM8996_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ +#define WM8996_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ +#define WM8996_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ + +/* + * R1568 (0x620) - Oversampling + */ +#define WM8996_SPK_OSR128 0x0008 /* SPK_OSR128 */ +#define WM8996_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */ +#define WM8996_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */ +#define WM8996_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */ +#define WM8996_DMIC_OSR64 0x0004 /* DMIC_OSR64 */ +#define WM8996_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */ +#define WM8996_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */ +#define WM8996_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */ +#define WM8996_ADC_OSR128 0x0002 /* ADC_OSR128 */ +#define WM8996_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ +#define WM8996_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ +#define WM8996_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ +#define WM8996_DAC_OSR128 0x0001 /* DAC_OSR128 */ +#define WM8996_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ +#define WM8996_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ +#define WM8996_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ + +/* + * R1569 (0x621) - Sidetone + */ +#define WM8996_ST_LPF 0x1000 /* ST_LPF */ +#define WM8996_ST_LPF_MASK 0x1000 /* ST_LPF */ +#define WM8996_ST_LPF_SHIFT 12 /* ST_LPF */ +#define WM8996_ST_LPF_WIDTH 1 /* ST_LPF */ +#define WM8996_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ +#define WM8996_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ +#define WM8996_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ +#define WM8996_ST_HPF 0x0040 /* ST_HPF */ +#define WM8996_ST_HPF_MASK 0x0040 /* ST_HPF */ +#define WM8996_ST_HPF_SHIFT 6 /* ST_HPF */ +#define WM8996_ST_HPF_WIDTH 1 /* ST_HPF */ +#define WM8996_STR_SEL 0x0002 /* STR_SEL */ +#define WM8996_STR_SEL_MASK 0x0002 /* STR_SEL */ +#define WM8996_STR_SEL_SHIFT 1 /* STR_SEL */ +#define WM8996_STR_SEL_WIDTH 1 /* STR_SEL */ +#define WM8996_STL_SEL 0x0001 /* STL_SEL */ +#define WM8996_STL_SEL_MASK 0x0001 /* STL_SEL */ +#define WM8996_STL_SEL_SHIFT 0 /* STL_SEL */ +#define WM8996_STL_SEL_WIDTH 1 /* STL_SEL */ + +/* + * R1792 (0x700) - GPIO 1 + */ +#define WM8996_GP1_DIR 0x8000 /* GP1_DIR */ +#define WM8996_GP1_DIR_MASK 0x8000 /* GP1_DIR */ +#define WM8996_GP1_DIR_SHIFT 15 /* GP1_DIR */ +#define WM8996_GP1_DIR_WIDTH 1 /* GP1_DIR */ +#define WM8996_GP1_PU 0x4000 /* GP1_PU */ +#define WM8996_GP1_PU_MASK 0x4000 /* GP1_PU */ +#define WM8996_GP1_PU_SHIFT 14 /* GP1_PU */ +#define WM8996_GP1_PU_WIDTH 1 /* GP1_PU */ +#define WM8996_GP1_PD 0x2000 /* GP1_PD */ +#define WM8996_GP1_PD_MASK 0x2000 /* GP1_PD */ +#define WM8996_GP1_PD_SHIFT 13 /* GP1_PD */ +#define WM8996_GP1_PD_WIDTH 1 /* GP1_PD */ +#define WM8996_GP1_POL 0x0400 /* GP1_POL */ +#define WM8996_GP1_POL_MASK 0x0400 /* GP1_POL */ +#define WM8996_GP1_POL_SHIFT 10 /* GP1_POL */ +#define WM8996_GP1_POL_WIDTH 1 /* GP1_POL */ +#define WM8996_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ +#define WM8996_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ +#define WM8996_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ +#define WM8996_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ +#define WM8996_GP1_DB 0x0100 /* GP1_DB */ +#define WM8996_GP1_DB_MASK 0x0100 /* GP1_DB */ +#define WM8996_GP1_DB_SHIFT 8 /* GP1_DB */ +#define WM8996_GP1_DB_WIDTH 1 /* GP1_DB */ +#define WM8996_GP1_LVL 0x0040 /* GP1_LVL */ +#define WM8996_GP1_LVL_MASK 0x0040 /* GP1_LVL */ +#define WM8996_GP1_LVL_SHIFT 6 /* GP1_LVL */ +#define WM8996_GP1_LVL_WIDTH 1 /* GP1_LVL */ +#define WM8996_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */ +#define WM8996_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */ +#define WM8996_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */ + +/* + * R1793 (0x701) - GPIO 2 + */ +#define WM8996_GP2_DIR 0x8000 /* GP2_DIR */ +#define WM8996_GP2_DIR_MASK 0x8000 /* GP2_DIR */ +#define WM8996_GP2_DIR_SHIFT 15 /* GP2_DIR */ +#define WM8996_GP2_DIR_WIDTH 1 /* GP2_DIR */ +#define WM8996_GP2_PU 0x4000 /* GP2_PU */ +#define WM8996_GP2_PU_MASK 0x4000 /* GP2_PU */ +#define WM8996_GP2_PU_SHIFT 14 /* GP2_PU */ +#define WM8996_GP2_PU_WIDTH 1 /* GP2_PU */ +#define WM8996_GP2_PD 0x2000 /* GP2_PD */ +#define WM8996_GP2_PD_MASK 0x2000 /* GP2_PD */ +#define WM8996_GP2_PD_SHIFT 13 /* GP2_PD */ +#define WM8996_GP2_PD_WIDTH 1 /* GP2_PD */ +#define WM8996_GP2_POL 0x0400 /* GP2_POL */ +#define WM8996_GP2_POL_MASK 0x0400 /* GP2_POL */ +#define WM8996_GP2_POL_SHIFT 10 /* GP2_POL */ +#define WM8996_GP2_POL_WIDTH 1 /* GP2_POL */ +#define WM8996_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ +#define WM8996_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ +#define WM8996_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ +#define WM8996_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ +#define WM8996_GP2_DB 0x0100 /* GP2_DB */ +#define WM8996_GP2_DB_MASK 0x0100 /* GP2_DB */ +#define WM8996_GP2_DB_SHIFT 8 /* GP2_DB */ +#define WM8996_GP2_DB_WIDTH 1 /* GP2_DB */ +#define WM8996_GP2_LVL 0x0040 /* GP2_LVL */ +#define WM8996_GP2_LVL_MASK 0x0040 /* GP2_LVL */ +#define WM8996_GP2_LVL_SHIFT 6 /* GP2_LVL */ +#define WM8996_GP2_LVL_WIDTH 1 /* GP2_LVL */ +#define WM8996_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */ +#define WM8996_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */ +#define WM8996_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */ + +/* + * R1794 (0x702) - GPIO 3 + */ +#define WM8996_GP3_DIR 0x8000 /* GP3_DIR */ +#define WM8996_GP3_DIR_MASK 0x8000 /* GP3_DIR */ +#define WM8996_GP3_DIR_SHIFT 15 /* GP3_DIR */ +#define WM8996_GP3_DIR_WIDTH 1 /* GP3_DIR */ +#define WM8996_GP3_PU 0x4000 /* GP3_PU */ +#define WM8996_GP3_PU_MASK 0x4000 /* GP3_PU */ +#define WM8996_GP3_PU_SHIFT 14 /* GP3_PU */ +#define WM8996_GP3_PU_WIDTH 1 /* GP3_PU */ +#define WM8996_GP3_PD 0x2000 /* GP3_PD */ +#define WM8996_GP3_PD_MASK 0x2000 /* GP3_PD */ +#define WM8996_GP3_PD_SHIFT 13 /* GP3_PD */ +#define WM8996_GP3_PD_WIDTH 1 /* GP3_PD */ +#define WM8996_GP3_POL 0x0400 /* GP3_POL */ +#define WM8996_GP3_POL_MASK 0x0400 /* GP3_POL */ +#define WM8996_GP3_POL_SHIFT 10 /* GP3_POL */ +#define WM8996_GP3_POL_WIDTH 1 /* GP3_POL */ +#define WM8996_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ +#define WM8996_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ +#define WM8996_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ +#define WM8996_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ +#define WM8996_GP3_DB 0x0100 /* GP3_DB */ +#define WM8996_GP3_DB_MASK 0x0100 /* GP3_DB */ +#define WM8996_GP3_DB_SHIFT 8 /* GP3_DB */ +#define WM8996_GP3_DB_WIDTH 1 /* GP3_DB */ +#define WM8996_GP3_LVL 0x0040 /* GP3_LVL */ +#define WM8996_GP3_LVL_MASK 0x0040 /* GP3_LVL */ +#define WM8996_GP3_LVL_SHIFT 6 /* GP3_LVL */ +#define WM8996_GP3_LVL_WIDTH 1 /* GP3_LVL */ +#define WM8996_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */ +#define WM8996_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */ +#define WM8996_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */ + +/* + * R1795 (0x703) - GPIO 4 + */ +#define WM8996_GP4_DIR 0x8000 /* GP4_DIR */ +#define WM8996_GP4_DIR_MASK 0x8000 /* GP4_DIR */ +#define WM8996_GP4_DIR_SHIFT 15 /* GP4_DIR */ +#define WM8996_GP4_DIR_WIDTH 1 /* GP4_DIR */ +#define WM8996_GP4_PU 0x4000 /* GP4_PU */ +#define WM8996_GP4_PU_MASK 0x4000 /* GP4_PU */ +#define WM8996_GP4_PU_SHIFT 14 /* GP4_PU */ +#define WM8996_GP4_PU_WIDTH 1 /* GP4_PU */ +#define WM8996_GP4_PD 0x2000 /* GP4_PD */ +#define WM8996_GP4_PD_MASK 0x2000 /* GP4_PD */ +#define WM8996_GP4_PD_SHIFT 13 /* GP4_PD */ +#define WM8996_GP4_PD_WIDTH 1 /* GP4_PD */ +#define WM8996_GP4_POL 0x0400 /* GP4_POL */ +#define WM8996_GP4_POL_MASK 0x0400 /* GP4_POL */ +#define WM8996_GP4_POL_SHIFT 10 /* GP4_POL */ +#define WM8996_GP4_POL_WIDTH 1 /* GP4_POL */ +#define WM8996_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ +#define WM8996_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ +#define WM8996_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ +#define WM8996_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ +#define WM8996_GP4_DB 0x0100 /* GP4_DB */ +#define WM8996_GP4_DB_MASK 0x0100 /* GP4_DB */ +#define WM8996_GP4_DB_SHIFT 8 /* GP4_DB */ +#define WM8996_GP4_DB_WIDTH 1 /* GP4_DB */ +#define WM8996_GP4_LVL 0x0040 /* GP4_LVL */ +#define WM8996_GP4_LVL_MASK 0x0040 /* GP4_LVL */ +#define WM8996_GP4_LVL_SHIFT 6 /* GP4_LVL */ +#define WM8996_GP4_LVL_WIDTH 1 /* GP4_LVL */ +#define WM8996_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */ +#define WM8996_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */ +#define WM8996_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */ + +/* + * R1796 (0x704) - GPIO 5 + */ +#define WM8996_GP5_DIR 0x8000 /* GP5_DIR */ +#define WM8996_GP5_DIR_MASK 0x8000 /* GP5_DIR */ +#define WM8996_GP5_DIR_SHIFT 15 /* GP5_DIR */ +#define WM8996_GP5_DIR_WIDTH 1 /* GP5_DIR */ +#define WM8996_GP5_PU 0x4000 /* GP5_PU */ +#define WM8996_GP5_PU_MASK 0x4000 /* GP5_PU */ +#define WM8996_GP5_PU_SHIFT 14 /* GP5_PU */ +#define WM8996_GP5_PU_WIDTH 1 /* GP5_PU */ +#define WM8996_GP5_PD 0x2000 /* GP5_PD */ +#define WM8996_GP5_PD_MASK 0x2000 /* GP5_PD */ +#define WM8996_GP5_PD_SHIFT 13 /* GP5_PD */ +#define WM8996_GP5_PD_WIDTH 1 /* GP5_PD */ +#define WM8996_GP5_POL 0x0400 /* GP5_POL */ +#define WM8996_GP5_POL_MASK 0x0400 /* GP5_POL */ +#define WM8996_GP5_POL_SHIFT 10 /* GP5_POL */ +#define WM8996_GP5_POL_WIDTH 1 /* GP5_POL */ +#define WM8996_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ +#define WM8996_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ +#define WM8996_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ +#define WM8996_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ +#define WM8996_GP5_DB 0x0100 /* GP5_DB */ +#define WM8996_GP5_DB_MASK 0x0100 /* GP5_DB */ +#define WM8996_GP5_DB_SHIFT 8 /* GP5_DB */ +#define WM8996_GP5_DB_WIDTH 1 /* GP5_DB */ +#define WM8996_GP5_LVL 0x0040 /* GP5_LVL */ +#define WM8996_GP5_LVL_MASK 0x0040 /* GP5_LVL */ +#define WM8996_GP5_LVL_SHIFT 6 /* GP5_LVL */ +#define WM8996_GP5_LVL_WIDTH 1 /* GP5_LVL */ +#define WM8996_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */ +#define WM8996_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */ +#define WM8996_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */ + +/* + * R1824 (0x720) - Pull Control (1) + */ +#define WM8996_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ +#define WM8996_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ +#define WM8996_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ +#define WM8996_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ +#define WM8996_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ +#define WM8996_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ +#define WM8996_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ +#define WM8996_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ +#define WM8996_MCLK2_PU 0x0200 /* MCLK2_PU */ +#define WM8996_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ +#define WM8996_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ +#define WM8996_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ +#define WM8996_MCLK2_PD 0x0100 /* MCLK2_PD */ +#define WM8996_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ +#define WM8996_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ +#define WM8996_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ +#define WM8996_MCLK1_PU 0x0080 /* MCLK1_PU */ +#define WM8996_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ +#define WM8996_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ +#define WM8996_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ +#define WM8996_MCLK1_PD 0x0040 /* MCLK1_PD */ +#define WM8996_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ +#define WM8996_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ +#define WM8996_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ +#define WM8996_DACDAT1_PU 0x0020 /* DACDAT1_PU */ +#define WM8996_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ +#define WM8996_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ +#define WM8996_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ +#define WM8996_DACDAT1_PD 0x0010 /* DACDAT1_PD */ +#define WM8996_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ +#define WM8996_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ +#define WM8996_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ +#define WM8996_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ +#define WM8996_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ +#define WM8996_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ +#define WM8996_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ +#define WM8996_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ +#define WM8996_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ +#define WM8996_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ +#define WM8996_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ +#define WM8996_BCLK1_PU 0x0002 /* BCLK1_PU */ +#define WM8996_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ +#define WM8996_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ +#define WM8996_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ +#define WM8996_BCLK1_PD 0x0001 /* BCLK1_PD */ +#define WM8996_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ +#define WM8996_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ +#define WM8996_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ + +/* + * R1825 (0x721) - Pull Control (2) + */ +#define WM8996_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */ +#define WM8996_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */ +#define WM8996_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */ +#define WM8996_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ +#define WM8996_ADDR_PD 0x0040 /* ADDR_PD */ +#define WM8996_ADDR_PD_MASK 0x0040 /* ADDR_PD */ +#define WM8996_ADDR_PD_SHIFT 6 /* ADDR_PD */ +#define WM8996_ADDR_PD_WIDTH 1 /* ADDR_PD */ +#define WM8996_DACDAT2_PU 0x0020 /* DACDAT2_PU */ +#define WM8996_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */ +#define WM8996_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */ +#define WM8996_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */ +#define WM8996_DACDAT2_PD 0x0010 /* DACDAT2_PD */ +#define WM8996_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */ +#define WM8996_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */ +#define WM8996_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */ +#define WM8996_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */ +#define WM8996_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */ +#define WM8996_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */ +#define WM8996_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */ +#define WM8996_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */ +#define WM8996_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */ +#define WM8996_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */ +#define WM8996_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */ +#define WM8996_BCLK2_PU 0x0002 /* BCLK2_PU */ +#define WM8996_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */ +#define WM8996_BCLK2_PU_SHIFT 1 /* BCLK2_PU */ +#define WM8996_BCLK2_PU_WIDTH 1 /* BCLK2_PU */ +#define WM8996_BCLK2_PD 0x0001 /* BCLK2_PD */ +#define WM8996_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */ +#define WM8996_BCLK2_PD_SHIFT 0 /* BCLK2_PD */ +#define WM8996_BCLK2_PD_WIDTH 1 /* BCLK2_PD */ + +/* + * R1840 (0x730) - Interrupt Status 1 + */ +#define WM8996_GP5_EINT 0x0010 /* GP5_EINT */ +#define WM8996_GP5_EINT_MASK 0x0010 /* GP5_EINT */ +#define WM8996_GP5_EINT_SHIFT 4 /* GP5_EINT */ +#define WM8996_GP5_EINT_WIDTH 1 /* GP5_EINT */ +#define WM8996_GP4_EINT 0x0008 /* GP4_EINT */ +#define WM8996_GP4_EINT_MASK 0x0008 /* GP4_EINT */ +#define WM8996_GP4_EINT_SHIFT 3 /* GP4_EINT */ +#define WM8996_GP4_EINT_WIDTH 1 /* GP4_EINT */ +#define WM8996_GP3_EINT 0x0004 /* GP3_EINT */ +#define WM8996_GP3_EINT_MASK 0x0004 /* GP3_EINT */ +#define WM8996_GP3_EINT_SHIFT 2 /* GP3_EINT */ +#define WM8996_GP3_EINT_WIDTH 1 /* GP3_EINT */ +#define WM8996_GP2_EINT 0x0002 /* GP2_EINT */ +#define WM8996_GP2_EINT_MASK 0x0002 /* GP2_EINT */ +#define WM8996_GP2_EINT_SHIFT 1 /* GP2_EINT */ +#define WM8996_GP2_EINT_WIDTH 1 /* GP2_EINT */ +#define WM8996_GP1_EINT 0x0001 /* GP1_EINT */ +#define WM8996_GP1_EINT_MASK 0x0001 /* GP1_EINT */ +#define WM8996_GP1_EINT_SHIFT 0 /* GP1_EINT */ +#define WM8996_GP1_EINT_WIDTH 1 /* GP1_EINT */ + +/* + * R1841 (0x731) - Interrupt Status 2 + */ +#define WM8996_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ +#define WM8996_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ +#define WM8996_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ +#define WM8996_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ +#define WM8996_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ +#define WM8996_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ +#define WM8996_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ +#define WM8996_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ +#define WM8996_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ +#define WM8996_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ +#define WM8996_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ +#define WM8996_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ +#define WM8996_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ +#define WM8996_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ +#define WM8996_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ +#define WM8996_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ +#define WM8996_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */ +#define WM8996_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */ +#define WM8996_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */ +#define WM8996_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */ +#define WM8996_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */ +#define WM8996_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */ +#define WM8996_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */ +#define WM8996_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */ +#define WM8996_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */ +#define WM8996_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */ +#define WM8996_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */ +#define WM8996_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */ +#define WM8996_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ +#define WM8996_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ +#define WM8996_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ +#define WM8996_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ +#define WM8996_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ +#define WM8996_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ +#define WM8996_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ +#define WM8996_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ +#define WM8996_MICD_EINT 0x0001 /* MICD_EINT */ +#define WM8996_MICD_EINT_MASK 0x0001 /* MICD_EINT */ +#define WM8996_MICD_EINT_SHIFT 0 /* MICD_EINT */ +#define WM8996_MICD_EINT_WIDTH 1 /* MICD_EINT */ + +/* + * R1842 (0x732) - Interrupt Raw Status 2 + */ +#define WM8996_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ +#define WM8996_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ +#define WM8996_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ +#define WM8996_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ +#define WM8996_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ +#define WM8996_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ +#define WM8996_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ +#define WM8996_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ +#define WM8996_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ +#define WM8996_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ +#define WM8996_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ +#define WM8996_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ +#define WM8996_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ +#define WM8996_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ +#define WM8996_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ +#define WM8996_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ +#define WM8996_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */ +#define WM8996_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */ +#define WM8996_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */ +#define WM8996_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */ +#define WM8996_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */ +#define WM8996_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */ +#define WM8996_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */ +#define WM8996_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */ +#define WM8996_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */ +#define WM8996_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */ +#define WM8996_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */ +#define WM8996_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ + +/* + * R1848 (0x738) - Interrupt Status 1 Mask + */ +#define WM8996_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ +#define WM8996_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ +#define WM8996_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ +#define WM8996_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ +#define WM8996_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ +#define WM8996_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ +#define WM8996_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ +#define WM8996_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ +#define WM8996_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ +#define WM8996_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ +#define WM8996_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ +#define WM8996_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ +#define WM8996_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ +#define WM8996_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ +#define WM8996_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ +#define WM8996_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ +#define WM8996_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ +#define WM8996_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ +#define WM8996_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ +#define WM8996_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ + +/* + * R1849 (0x739) - Interrupt Status 2 Mask + */ +#define WM8996_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ +#define WM8996_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ +#define WM8996_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ +#define WM8996_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ +#define WM8996_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ +#define WM8996_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ +#define WM8996_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ +#define WM8996_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ +#define WM8996_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ +#define WM8996_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ +#define WM8996_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ +#define WM8996_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ +#define WM8996_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ +#define WM8996_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ +#define WM8996_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ +#define WM8996_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ +#define WM8996_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */ +#define WM8996_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */ +#define WM8996_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ +#define WM8996_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ +#define WM8996_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */ +#define WM8996_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */ +#define WM8996_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ +#define WM8996_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ +#define WM8996_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ +#define WM8996_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ +#define WM8996_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ +#define WM8996_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ +#define WM8996_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ +#define WM8996_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ +#define WM8996_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ +#define WM8996_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ +#define WM8996_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ +#define WM8996_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ + +/* + * R1856 (0x740) - Interrupt Control + */ +#define WM8996_IM_IRQ 0x0001 /* IM_IRQ */ +#define WM8996_IM_IRQ_MASK 0x0001 /* IM_IRQ */ +#define WM8996_IM_IRQ_SHIFT 0 /* IM_IRQ */ +#define WM8996_IM_IRQ_WIDTH 1 /* IM_IRQ */ + +/* + * R2048 (0x800) - Left PDM Speaker + */ +#define WM8996_SPKL_ENA 0x0010 /* SPKL_ENA */ +#define WM8996_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */ +#define WM8996_SPKL_ENA_SHIFT 4 /* SPKL_ENA */ +#define WM8996_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ +#define WM8996_SPKL_MUTE 0x0008 /* SPKL_MUTE */ +#define WM8996_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */ +#define WM8996_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */ +#define WM8996_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ +#define WM8996_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */ +#define WM8996_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */ +#define WM8996_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */ +#define WM8996_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */ +#define WM8996_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */ +#define WM8996_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */ +#define WM8996_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */ + +/* + * R2049 (0x801) - Right PDM Speaker + */ +#define WM8996_SPKR_ENA 0x0010 /* SPKR_ENA */ +#define WM8996_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */ +#define WM8996_SPKR_ENA_SHIFT 4 /* SPKR_ENA */ +#define WM8996_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ +#define WM8996_SPKR_MUTE 0x0008 /* SPKR_MUTE */ +#define WM8996_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */ +#define WM8996_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */ +#define WM8996_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ +#define WM8996_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */ +#define WM8996_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */ +#define WM8996_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */ +#define WM8996_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */ +#define WM8996_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */ +#define WM8996_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */ +#define WM8996_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */ + +/* + * R2050 (0x802) - PDM Speaker Mute Sequence + */ +#define WM8996_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */ +#define WM8996_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */ +#define WM8996_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */ +#define WM8996_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */ +#define WM8996_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */ +#define WM8996_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */ +#define WM8996_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */ + +/* + * R2051 (0x803) - PDM Speaker Volume + */ +#define WM8996_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */ +#define WM8996_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */ +#define WM8996_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */ +#define WM8996_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */ +#define WM8996_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */ +#define WM8996_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */ + +#endif diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c index 4cc2d567f22f..e763c54c55dc 100644 --- a/sound/soc/codecs/wm_hubs.c +++ b/sound/soc/codecs/wm_hubs.c @@ -440,9 +440,8 @@ static int hp_event(struct snd_soc_dapm_widget *w, reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY; snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg); - /* Smallest supported update interval */ snd_soc_update_bits(codec, WM8993_DC_SERVO_1, - WM8993_DCS_TIMER_PERIOD_01_MASK, 1); + WM8993_DCS_TIMER_PERIOD_01_MASK, 0); calibrate_dc_servo(codec); diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig index 54b0e4b7faf7..b99091fc34eb 100644 --- a/sound/soc/samsung/Kconfig +++ b/sound/soc/samsung/Kconfig @@ -183,7 +183,7 @@ config SND_SOC_SPEYSIDE tristate "Audio support for Wolfson Speyside" depends on SND_SOC_SAMSUNG && MACH_WLF_CRAGG_6410 select SND_SAMSUNG_I2S - select SND_SOC_WM8915 + select SND_SOC_WM8996 select SND_SOC_WM9081 config SND_SOC_SPEYSIDE_WM8962 diff --git a/sound/soc/samsung/speyside.c b/sound/soc/samsung/speyside.c index d6dee4d02036..590e9274b062 100644 --- a/sound/soc/samsung/speyside.c +++ b/sound/soc/samsung/speyside.c @@ -14,10 +14,10 @@ #include <sound/jack.h> #include <linux/gpio.h> -#include "../codecs/wm8915.h" +#include "../codecs/wm8996.h" #include "../codecs/wm9081.h" -#define WM8915_HPSEL_GPIO 214 +#define WM8996_HPSEL_GPIO 214 static int speyside_set_bias_level(struct snd_soc_card *card, struct snd_soc_dapm_context *dapm, @@ -31,12 +31,12 @@ static int speyside_set_bias_level(struct snd_soc_card *card, switch (level) { case SND_SOC_BIAS_STANDBY: - ret = snd_soc_dai_set_sysclk(codec_dai, WM8915_SYSCLK_MCLK2, + ret = snd_soc_dai_set_sysclk(codec_dai, WM8996_SYSCLK_MCLK2, 32768, SND_SOC_CLOCK_IN); if (ret < 0) return ret; - ret = snd_soc_dai_set_pll(codec_dai, WM8915_FLL_MCLK2, + ret = snd_soc_dai_set_pll(codec_dai, WM8996_FLL_MCLK2, 0, 0, 0); if (ret < 0) { pr_err("Failed to stop FLL\n"); @@ -65,7 +65,7 @@ static int speyside_set_bias_level_post(struct snd_soc_card *card, case SND_SOC_BIAS_PREPARE: if (card->dapm.bias_level == SND_SOC_BIAS_STANDBY) { ret = snd_soc_dai_set_pll(codec_dai, 0, - WM8915_FLL_MCLK2, + WM8996_FLL_MCLK2, 32768, 48000 * 256); if (ret < 0) { pr_err("Failed to start FLL\n"); @@ -73,7 +73,7 @@ static int speyside_set_bias_level_post(struct snd_soc_card *card, } ret = snd_soc_dai_set_sysclk(codec_dai, - WM8915_SYSCLK_FLL, + WM8996_SYSCLK_FLL, 48000 * 256, SND_SOC_CLOCK_IN); if (ret < 0) @@ -149,26 +149,26 @@ static void speyside_set_polarity(struct snd_soc_codec *codec, int polarity) { speyside_jack_polarity = !polarity; - gpio_direction_output(WM8915_HPSEL_GPIO, speyside_jack_polarity); + gpio_direction_output(WM8996_HPSEL_GPIO, speyside_jack_polarity); /* Re-run DAPM to make sure we're using the correct mic bias */ snd_soc_dapm_sync(&codec->dapm); } -static int speyside_wm8915_init(struct snd_soc_pcm_runtime *rtd) +static int speyside_wm8996_init(struct snd_soc_pcm_runtime *rtd) { struct snd_soc_dai *dai = rtd->codec_dai; struct snd_soc_codec *codec = rtd->codec; int ret; - ret = snd_soc_dai_set_sysclk(dai, WM8915_SYSCLK_MCLK2, 32768, 0); + ret = snd_soc_dai_set_sysclk(dai, WM8996_SYSCLK_MCLK2, 32768, 0); if (ret < 0) return ret; - ret = gpio_request(WM8915_HPSEL_GPIO, "HP_SEL"); + ret = gpio_request(WM8996_HPSEL_GPIO, "HP_SEL"); if (ret != 0) pr_err("Failed to request HP_SEL GPIO: %d\n", ret); - gpio_direction_output(WM8915_HPSEL_GPIO, speyside_jack_polarity); + gpio_direction_output(WM8996_HPSEL_GPIO, speyside_jack_polarity); ret = snd_soc_jack_new(codec, "Headset", SND_JACK_HEADSET | SND_JACK_BTN_0, @@ -182,7 +182,7 @@ static int speyside_wm8915_init(struct snd_soc_pcm_runtime *rtd) if (ret) return ret; - wm8915_detect(codec, &speyside_headset, speyside_set_polarity); + wm8996_detect(codec, &speyside_headset, speyside_set_polarity); return 0; } @@ -205,16 +205,16 @@ static struct snd_soc_dai_link speyside_dai[] = { .name = "CPU", .stream_name = "CPU", .cpu_dai_name = "samsung-i2s.0", - .codec_dai_name = "wm8915-aif1", + .codec_dai_name = "wm8996-aif1", .platform_name = "samsung-audio", - .codec_name = "wm8915.1-001a", - .init = speyside_wm8915_init, + .codec_name = "wm8996.1-001a", + .init = speyside_wm8996_init, .ops = &speyside_ops, }, { .name = "Baseband", .stream_name = "Baseband", - .cpu_dai_name = "wm8915-aif2", + .cpu_dai_name = "wm8996-aif2", .codec_dai_name = "wm1250-ev1", .codec_name = "wm1250-ev1.1-0027", .ops = &speyside_ops, diff --git a/sound/usb/caiaq/input.c b/sound/usb/caiaq/input.c index 4432ef7a70a9..a213813487bd 100644 --- a/sound/usb/caiaq/input.c +++ b/sound/usb/caiaq/input.c @@ -30,7 +30,7 @@ static unsigned short keycode_ak1[] = { KEY_C, KEY_B, KEY_A }; static unsigned short keycode_rk2[] = { KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, KEY_7 }; static unsigned short keycode_rk3[] = { KEY_1, KEY_2, KEY_3, KEY_4, - KEY_5, KEY_6, KEY_7, KEY_5, KEY_6 }; + KEY_5, KEY_6, KEY_7, KEY_8, KEY_9 }; static unsigned short keycode_kore[] = { KEY_FN_F1, /* "menu" */ diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c index 7c0d21ecd821..7d46e482375d 100644 --- a/sound/usb/endpoint.c +++ b/sound/usb/endpoint.c @@ -352,7 +352,7 @@ int snd_usb_parse_audio_endpoints(struct snd_usb_audio *chip, int iface_no) continue; } if (((protocol == UAC_VERSION_1) && (fmt->bLength < 8)) || - ((protocol == UAC_VERSION_2) && (fmt->bLength != 6))) { + ((protocol == UAC_VERSION_2) && (fmt->bLength < 6))) { snd_printk(KERN_ERR "%d:%u:%d : invalid UAC_FORMAT_TYPE desc\n", dev->devnum, iface_no, altno); continue; diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index c22fa76e363a..c04d7c71ac88 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -1191,6 +1191,11 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, void if (state->mixer->protocol == UAC_VERSION_1) { csize = hdr->bControlSize; + if (!csize) { + snd_printdd(KERN_ERR "usbaudio: unit %u: " + "invalid bControlSize == 0\n", unitid); + return -EINVAL; + } channels = (hdr->bLength - 7) / csize - 1; bmaControls = hdr->bmaControls; } else { @@ -1934,15 +1939,13 @@ static int snd_usb_mixer_controls(struct usb_mixer_interface *mixer) struct mixer_build state; int err; const struct usbmix_ctl_map *map; - struct usb_host_interface *hostif; void *p; - hostif = mixer->chip->ctrl_intf; memset(&state, 0, sizeof(state)); state.chip = mixer->chip; state.mixer = mixer; - state.buffer = hostif->extra; - state.buflen = hostif->extralen; + state.buffer = mixer->hostif->extra; + state.buflen = mixer->hostif->extralen; /* check the mapping table */ for (map = usbmix_ctl_maps; map->id; map++) { @@ -1955,7 +1958,8 @@ static int snd_usb_mixer_controls(struct usb_mixer_interface *mixer) } p = NULL; - while ((p = snd_usb_find_csint_desc(hostif->extra, hostif->extralen, p, UAC_OUTPUT_TERMINAL)) != NULL) { + while ((p = snd_usb_find_csint_desc(mixer->hostif->extra, mixer->hostif->extralen, + p, UAC_OUTPUT_TERMINAL)) != NULL) { if (mixer->protocol == UAC_VERSION_1) { struct uac1_output_terminal_descriptor *desc = p; @@ -2162,17 +2166,15 @@ int snd_usb_mixer_activate(struct usb_mixer_interface *mixer) /* create the handler for the optional status interrupt endpoint */ static int snd_usb_mixer_status_create(struct usb_mixer_interface *mixer) { - struct usb_host_interface *hostif; struct usb_endpoint_descriptor *ep; void *transfer_buffer; int buffer_length; unsigned int epnum; - hostif = mixer->chip->ctrl_intf; /* we need one interrupt input endpoint */ - if (get_iface_desc(hostif)->bNumEndpoints < 1) + if (get_iface_desc(mixer->hostif)->bNumEndpoints < 1) return 0; - ep = get_endpoint(hostif, 0); + ep = get_endpoint(mixer->hostif, 0); if (!usb_endpoint_dir_in(ep) || !usb_endpoint_xfer_int(ep)) return 0; @@ -2202,7 +2204,6 @@ int snd_usb_create_mixer(struct snd_usb_audio *chip, int ctrlif, }; struct usb_mixer_interface *mixer; struct snd_info_entry *entry; - struct usb_host_interface *host_iface; int err; strcpy(chip->card->mixername, "USB Mixer"); @@ -2219,8 +2220,8 @@ int snd_usb_create_mixer(struct snd_usb_audio *chip, int ctrlif, return -ENOMEM; } - host_iface = &usb_ifnum_to_if(chip->dev, ctrlif)->altsetting[0]; - switch (get_iface_desc(host_iface)->bInterfaceProtocol) { + mixer->hostif = &usb_ifnum_to_if(chip->dev, ctrlif)->altsetting[0]; + switch (get_iface_desc(mixer->hostif)->bInterfaceProtocol) { case UAC_VERSION_1: default: mixer->protocol = UAC_VERSION_1; diff --git a/sound/usb/mixer.h b/sound/usb/mixer.h index ae1a14dcfe82..81b2d8a32fb0 100644 --- a/sound/usb/mixer.h +++ b/sound/usb/mixer.h @@ -3,6 +3,7 @@ struct usb_mixer_interface { struct snd_usb_audio *chip; + struct usb_host_interface *hostif; struct list_head list; unsigned int ignore_ctl_error; struct urb *urb; diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index dba0b7f11c54..4d4f86552a23 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -2417,6 +2417,12 @@ YAMAHA_DEVICE(0x7010, "UB99"), .idProduct = 0x1020, }, +/* KeithMcMillen Stringport */ +{ + USB_DEVICE(0x1f38, 0x0001), + .bInterfaceClass = USB_CLASS_AUDIO, +}, + /* Miditech devices */ { USB_DEVICE(0x4752, 0x0011), diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index 77762c99afbe..81e07d842581 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -426,7 +426,7 @@ static int snd_usb_cm106_boot_quirk(struct usb_device *dev) */ static int snd_usb_cm6206_boot_quirk(struct usb_device *dev) { - int err, reg; + int err = 0, reg; int val[] = {0x2004, 0x3000, 0xf800, 0x143f, 0x0000, 0x3000}; for (reg = 0; reg < ARRAY_SIZE(val); reg++) { |