diff options
| -rw-r--r-- | arch/arm/common/gic.c | 10 | ||||
| -rw-r--r-- | arch/arm/include/asm/hardware/gic.h | 8 |
2 files changed, 13 insertions, 5 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index cfbe8b17e989..48a70afca283 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -87,7 +87,7 @@ static inline unsigned int gic_irq(unsigned int irq) * our "acknowledge" routine disable the interrupt, then mark it as * complete. */ -static void gic_ack_irq(unsigned int irq) +void gic_ack_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); @@ -97,7 +97,7 @@ static void gic_ack_irq(unsigned int irq) spin_unlock(&irq_controller_lock); } -static void gic_mask_irq(unsigned int irq) +void gic_mask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); @@ -106,7 +106,7 @@ static void gic_mask_irq(unsigned int irq) spin_unlock(&irq_controller_lock); } -static void gic_unmask_irq(unsigned int irq) +void gic_unmask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); @@ -115,7 +115,7 @@ static void gic_unmask_irq(unsigned int irq) spin_unlock(&irq_controller_lock); } -static int gic_set_type(unsigned int irq, unsigned int type) +int gic_set_type(unsigned int irq, unsigned int type) { void __iomem *base = gic_dist_base(irq); unsigned int gicirq = gic_irq(irq); @@ -161,7 +161,7 @@ static int gic_set_type(unsigned int irq, unsigned int type) } #ifdef CONFIG_SMP -static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) +int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) { void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3); unsigned int shift = (irq % 4) * 8; diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 0a198b0f29c4..5fd0ff2bb821 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -41,6 +41,14 @@ void gic_cpu_init(unsigned int gic_nr, void __iomem *base); void gic_cpu_exit(unsigned int gic_nr); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); + +void gic_ack_irq(unsigned int irq); +void gic_mask_irq(unsigned int irq); +void gic_unmask_irq(unsigned int irq); +int gic_set_type(unsigned int irq, unsigned int type); +#ifdef CONFIG_SMP +int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val); +#endif #endif #endif |