diff options
Diffstat (limited to 'Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 83aeb1f5a645..c1de909e5231 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie" +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie", + "fsl,imx8qm-pcie","fsl,imx8qxp-pcie","fsl,imx8mq-pcie","fsl,imx8mm-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -12,6 +13,8 @@ Required properties: - "msi": The interrupt that is asserted when an MSI is received - clock-names: Must include the following additional entries: - "pcie_phy" +- ext_osc: use the external oscillator or not. +- hard-wired: the port is hard wired in hw design or not. Optional properties: - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 @@ -34,6 +37,22 @@ Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: - "pcie_inbound_axi" +Additional required properties for imx8 pcie: +- hsio : should be <&hsio>. + The phandle points to the hsio region containing the hsio + such as the pcie and sata control registers. +- hsio-cfg: hsio configration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. +- ctrl-id: used to distinguish pciea or pcieb. + 0: pciea, 1: pcieb. +- cpu-base-addr: the base cpu address mapped from hsio address. + Example: + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + hsio = <&hsio>; + ctrl-id = <0>; /* pciea */ + cpu-base-addr = <0x40000000>; Example: pcie@0x01000000 { |