diff options
Diffstat (limited to 'Documentation')
69 files changed, 4017 insertions, 106 deletions
diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 6a8b7158697f..9c92bb879b6d 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -1,6 +1,6 @@ <?xml version="1.0"?> -<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN" - "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" [ +<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.2//EN" + "http://www.oasis-open.org/docbook/xml/4.2/docbookx.dtd" [ <!ENTITY % media-entities SYSTEM "./media-entities.tmpl"> %media-entities; <!ENTITY media-indices SYSTEM "./media-indices.tmpl"> diff --git a/Documentation/arm/nvidia/tegra_parameters.txt b/Documentation/arm/nvidia/tegra_parameters.txt new file mode 100644 index 000000000000..5f60f89e9a84 --- /dev/null +++ b/Documentation/arm/nvidia/tegra_parameters.txt @@ -0,0 +1,190 @@ +This file documents NVIDIA Tegra specific sysfs and debugfs files and +kernel module parameters. + +/sys/power/suspend/mode +----------------------- + +Used to select the LP1 or LP0 power state during system suspend. +# echo lp0 > /sys/kernel/debug/suspend_mode +# echo lp1 > /sys/kernel/debug/suspend_mode + +/sys/module/cpuidle/parameters/power_down_in_idle +------------------------------------------ + +Used to enable/disable CPU power down in idle. +# echo 1 > /sys/module/cpuidle/parameters/power_down_in_idle +# echo 0 > /sys/module/cpuidle/parameters/power_down_in_idle + +/sys/kernel/debug/cpuidle/power_down_stats +----------------------------- + +Contains CPU power down statistics. +# cat /sys/kernel/debug/cpuidle/power_down_stats + +/sys/kernel/debug/powergate +--------------------------- + +Contains power gating state of different tegra blocks. + +# cat /sys/kernel/debug/powergate + +/sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/enable +------------------------------------------------------ + +Control hotplugging of cores. +# echo 0 > /sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/enable +# echo 1 > /sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/enable + +Cpuquiet supports the implementation of multiple policies in the form of +governors. The balanced governor implements the exact same policy previously +implemented as "auto hotplug". The behavior with regards to cores coming +online/offline and switching between the LP and G cluster remain the same. + +/sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/no_lp +----------------------------------------------------- + +Enable/disable shadow cluster. +# echo 0 > /sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/no_lp +# echo 1 > /sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/no_lp + +/sys/devices/system/cpu/cpuquiet/available_governors +---------------------------------------------------- + +List available governors. +# cat /sys/devices/system/cpu/cpuquiet/available_governors + +/sys/devices/system/cpu/cpuquiet/current_governor +------------------------------------------------- + +Set the current active cpuquiet governor. +# echo [governor name] > /sys/devices/system/cpu/cpuquiet/current_governor + +/sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/idle_bottom_freq +---------------------------------------------------------------- + +Main cluster minimum frequency. + +/sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/idle_top_freq +------------------------------------------------------------- + +Shadow cluster maximum frequency. + +/sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/down_delay +---------------------------------------------------------- + +Delay (in jiffies) for switching to shadow cluster. + +/sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/up_delay +-------------------------------------------------------- + +Delay for switching to main cluster. + +/sys/devices/system/cpu/cpuquiet/balanced/balance_level +------------------------------------------------------- + +Percentage of max speed considered to be in balance. Half of balanced +speed is considered skewed. Requires balanced governor to be set active. + +/sys/devices/system/cpu/cpuquiet/balanced/down_delay +---------------------------------------------------- + +Delay for reducing cores. Requires balanced governor to be set active. + +/sys/devices/system/cpu/cpuquiet/balanced/up_delay +-------------------------------------------------- + +Delay for bringing additional cores online in main cluster. Requires +balanced governor to be set active. + +/sys/kernel/debug/tegra_hotplug/stats +------------------------------------- + +Contains hotplug statistics. + +/sys/kernel/cluster/active +-------------------------- + +Controls active CPU cluster: main (G) or shadow (LP). +For manual control disable auto hotlug, enable immediate switch and +possibly force switch to happen always: +# echo 0 > /sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/enable +# echo 1 > /sys/kernel/cluster/immediate +# echo 1 > /sys/kernel/cluster/force + +Cluster switching can happen only when only core 0 is online. + +Active cluster can be set or toggled: +# echo "G" > /sys/kernel/cluster/active +# echo "LP" > /sys/kernel/cluster/active +# echo "toggle" > /sys/kernel/cluster/active + +/sys/module/tegra*_clocks/parameters/detach_shared_bus +------------------------------------------------------ + +Enable/disable shared bus clock update. Module name depends on Tegra +chip version. + +/sys/module/tegra*_emc/parameters/emc_enable +-------------------------------------------- + +Enable/disable EMC DFS. Module name depends on Tegra chip version. + +/sys/kernel/debug/tegra_emc/stats +--------------------------------- + +Contains EMC clock statistics. + +/sys/module/tegra*_dvfs/parameters/disable_cpu +---------------------------------------------- + +Enable/disable DVFS for CPU domain. Module name depends on Tegra chip +version. + +/sys/module/tegra*_dvfs/parameters/disable_core +----------------------------------------------- + +Enable/disable DVFS for CORE domain. Module name depends on Tegra chip +version. + +/sys/kernel/debug/clock/emc/rate +-------------------------------- + +Get/set EMC clock rate. + +/sys/kernel/debug/clock/<module>/rate +------------------------------------- + +/sys/kernel/debug/clock/<module>/parent +--------------------------------------- + +/sys/kernel/debug/clock/<module>/state +-------------------------------------- + +/sys/kernel/debug/clock/<module>/time_on +---------------------------------------- + +/sys/kernel/debug/clock/clock_tree +---------------------------------- + +Shows the state of the clock tree. + +/sys/kernel/debug/clock/dvfs +---------------------------- + +Contains voltage state. + +/sys/kernel/debug/tegra_actmon/avp/state +---------------------------------------- + +/sys/kernel/debug/clock/mon.avp/rate +------------------------------------ + +/sys/kernel/debug/clock/rails +----------------------------- + +Contains the time at each voltage. + +/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state +-------------------------------------------------------- + +Contains the time at each frequency. diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt new file mode 100644 index 000000000000..2188203dc2dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt @@ -0,0 +1,201 @@ +NVIDIA Tegra DFLL clock source data in the SoC DTS file: + +Required properties: +- compatible : Must be one of the following + "nvidia,tegra124-dfll" + "nvidia,tegra148-dfll" + "nvidia,tegra114-dfll" +- reg : Must contain the starting physical address and length for the DFLL's + MMIO register space including the DFLL-to-I2C controller interface and the + DFLL's I2C controller. +- out-clock-name : Must contain a "dfll_cpu" string, name of the DFLL output + clock. + +Optional properties: +- status : device availability -- managed by the DT integration code. + Should be set to "disabled" in the SoC DTS file. + +Example: + +dfll@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0x70110000 0x400>; + out-clock-name = "dfll_cpu"; + status = "disabled"; +}; + + +NVIDIA Tegra DFLL clock source data in the board DTS file + +Required properties: +- board-params : phandle pointing to the board-specific configuration data + for this DFLL instance. + +Optional properties: +- i2c-quiet-output-workaround : If the DFLL IP block version implemented on + this SoC requires the I2C output to the PMIC to be quiesced before disabling + it, this property should be set. +- monitor-data-new-workaround : If the DFLL IP block version implemented on + this SoC may erroneously clear DFLL monitor data new indicator, this property + should be set. +- dynamic-output-lut-workaround : If the DFLL IP block version implemented on + this SoC does not support dynamic change of DFLL output limits register + fields, this property should be set. + +- status : device availability -- managed by the DT integration code. + Should be set to "okay" if the DFLL is to be used on this board type. + +- i2c-pmic-integration : phandle pointing to the integration data for + PMIC controlled by this DFLL instance via I2C interface. + +Optional subnode: +- pwm-pmic-integration : should have integration data for PMIC controlled by + this DFLL instance via PWM interface. + +Note that one and only one of 'i2c-pmic-integration', or 'pwm-pmic-integration', +must be included. + +Example: + +dfll@70110000 { + board-params = <&{/cpu_dfll_board_params}>; + i2c-pmic-integration = <&{/cpu_dfll_pmic_integration}>; + status = "okay"; +}; + + +DFLL board params node in the board DTS file + +Required properties: +- sample-rate : control loop sample rate (in Hz). +- cf : I2C: duration to force the PMIC voltage after frequency change. +- cg : loop gain (signed) - determined during board characterization. +- ci : loop integral gain selector. +- droop-cut-value : DFLL output clock throttle setting at voltage droop event. +- droop-restore-ramp : DFLL clock recovery rate after a voltage droop event. +- scale-out-ramp : DFLL clock output scaling ramp rate. + +Optional properties: +- cg-scale : if present, divide loop gain by 8 (see 'cg' above). + +- fixed-output-forcing : force PMIC voltage during req change for a fixed time. +- auto-output-forcing : force PMIC voltage during req change for a dynamic time. +- no-output-forcing : don't force PMIC voltage output during request change. +Note that one and only one of 'fixed-output-forcing', or 'auto-output-forcing', +or 'no-output-forcing' must be specified. + +Example: + +cpu_dfll_board_params { + sample-rate = <12500>; + fixed-output-forcing; + cf = <10>; + ci = <0>; + cg = <2>; + droop-cut-value = <0xf>; + droop-restore-ramp = <0x0>; + scale-out-ramp = <0x0>; +}; + + +DFLL I2C PMIC integration node in the board DTS file + +Required properties: +- pmic-i2c-address : PMIC I2C bus address. +- pmic-i2c-voltage-register : internal PMIC address of the select-output-voltage + register (vsel register) for the rail that supplies the DFLL. +- sel-slope : slope coefficient for linear conversion of selector values exposed + by regulator framework into PMIC vsel register settings. +- i2c-fs-rate : I2C bus rate in Hz, in FS mode. + +Optional properties: +- i2c-10-bit-addresses : PMIC requires a 10-bit I2C address. +- i2c-hs-rate : use HS I2C bus mode to communicate with the PMIC, at this rate + in Hz. +- i2c-hs-master-code : I2C master code to use - only applies in HS mode; must + be set if i2c-hs-rate is set, ignored otherwise. +- sel-offset : offset coefficient for linear conversion of selector values + exposed by regulator framework into PMIC vsel register settings (offset zero, + if not present). +- pmic-undershoot-gb : PMIC undershoot guard-band in mV (zero, if not present). + +Example: + +cpu_dfll_pmic_integration { + pmic-i2c-address = <0xb0>; + pmic-i2c-voltage-register = <0x23>; + i2c-fs-rate = <400000>; + sel-conversion-slope = <1>; + pmic-undershoot-gb = <100>; +}; + +DFLL PWM PMIC integration subnode in the board DTS file + +Required properties: +- compatible : Must be + "nvidia,tegra124-dfll-pwm" +- pwm-data-gpio : DFLL PWM data GPIO. + +- #pwm-cells : Number of cells in PWM regulator specification, must be 2. +- pwm-regulator : phandle pointing to the node of regulator controlled by DFLL. + PWM regulator properties are defined by pwm-regulator.txt binding; pwm-list + of the regulator node must refer to PWM PMIC integration node, and include 2 + cells in the spec: cell 0 for PWM channel number within DFLL, and cell 1 for + PWM period in nanoseconds. + +Optional properties: +- pwm-1wire-buffer : DFLL is connected to PMIC by 1 wire (data only) via external + buffer with tri-state control. +- pwm-1wire-direct : DFLL is directly connected to PMIC by 1 wire (data only). +- pwm-2wire : DFLL is directly connected to PMIC by 2 wires (data/clock). +Note that one and only one of 'pwm-1wire-buffer', or 'pwm-1wire-direct', +or 'pwm-2wire' must be specified. + +- pwm-buffer-ctrl-gpio : External buffer control GPIO. + Must be specified if 'pwm-1wire-buffer' property is present. +- pwm-clk-gpio : DFLL PWM clock GPIO. + Must be specified if 'pwm-2wire' property is present. +- pwm-delta-mode : Stop PWM clock when no changes. + Can be specified if 'pwm-2wire' property is present. + +Example: + +dfll@70110000 { + board-params = <&{/cpu_dfll_board_params}>; + status = "okay"; + pwm_dfll: pwm-pmic-integration { + compatible = "nvidia,tegra124-dfll-pwm"; + pwm-1wire-buffer; + pwm-data-gpio = <&gpio TEGRA_GPIO(X, 0) 0>; + pwm-buffer-ctrl-gpio = <&gpio TEGRA_GPIO(S, 5) 1>; + #pwm-cells = <2>; + pwm-regulator = <&cpu_pwm_reg>; + }; +}; + +pwm_regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + cpu_pwm_reg: pwm-regulator@0 { + reg = <0>; + compatible = "regulator-pwm"; + pwms = <&pwm_dfll 0 2500>; + regulator-name = "vdd-cpu-pwm-reg"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1275000>; + regulator-init-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-n-voltages = <33>; + voltage-time-sel = <80>; + idle-gpio = <&gpio TEGRA_GPIO(X, 2) 0>; + + consumers { + c1 { + regulator-consumer-supply = "vdd_cpu"; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index 4c33b29dc660..18967ccf0aa7 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -4,14 +4,15 @@ Properties: - name : Should be emc - #address-cells : Should be 1 - #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". +- compatible : Should contain "nvidia,tegra20-emc" or "nvidia,tegra30-emc" - reg : Offset and length of the register set for the device - nvidia,use-ram-code : If present, the sub-nodes will be addressed and chosen using the ramcode board selector. If omitted, only one set of tables can be present and said tables will be used irrespective of ram-code configuration. -Child device nodes describe the memory settings for different configurations and clock rates. +Child device nodes describe the memory settings for different configurations +and clock rates. Example: @@ -61,6 +62,8 @@ There are two ways of specifying which tables to use: these strappings can be read through a register in the SoC, and thus used to select which tables to use. +Tables for Tegra20: + Properties: - name : Should be emc-table - compatible : Should contain "nvidia,tegra20-emc-table". @@ -98,3 +101,299 @@ Properties: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 >; }; + +Tables for Tegra30: + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra30-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- nvidia,revision : SDRAM revision +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-registers : a word array of EMC registers to be programmed + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, + WEXT, WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, + PRE_REFRESH_REQ_CNT, PDEX2WR, PDEX2RD, PCHG2PDEN, ACT2PDEN, + AR2PDEN, RW2PDEN, TXSR, TXSRDLL, TCKE, TFAW, TRPAB,TCLKSTABLE, + TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, ODT_READ, + FBIO_CFG5, CFG_DIG_DLL, CFG_DIG_DLL_PERIOD, + DLL_XFORM_DQS0, DLL_XFORM_DQS1, DLL_XFORM_DQS2, DLL_XFORM_DQS3, + DLL_XFORM_DQS4, DLL_XFORM_DQS5, DLL_XFORM_DQS6, DLL_XFORM_DQS7, + DLL_XFORM_QUSE0, DLL_XFORM_QUSE1, DLL_XFORM_QUSE2, DLL_XFORM_QUSE3, + DLL_XFORM_QUSE4, DLL_XFORM_QUSE5, DLL_XFORM_QUSE6, DLL_XFORM_QUSE7, + DLI_TRIM_TXDQS0, DLI_TRIM_TXDQS1, DLI_TRIM_TXDQS2, DLI_TRIM_TXDQS3, + DLI_TRIM_TXDQS4, DLI_TRIM_TXDQS5, DLI_TRIM_TXDQS6, DLI_TRIM_TXDQS7, + DLL_XFORM_DQ0, DLL_XFORM_DQ1, DLL_XFORM_DQ2, DLL_XFORM_DQ3, + DLL_XFORM_DQ1, DLL_XFORM_DQ2, DLL_XFORM_DQ3, XM2CMDPADCTRL, XM2DQSPADCTRL2, + XM2DQPADCTRL2, XM2CLKPADCTRL, XM2COMPPADCTRL, XM2VTTGENPADCTRL, + XM2VTTGENPADCTRL2, XM2QUSEPADCTRL, XM2DQSPADCTRL3, CTT_TERM_CTRL, + ZCAL_INTERVAL, ZCAL_WAIT_CNT, MRS_WAIT_CNT, AUTO_CAL_CONFIG, CTT, + CTT_DURATION, DYN_SELF_REF_CONTROL, EMEM_ARB_CFG, EMEM_ARB_OUTSTANDING_REQ, + EMEM_ARB_TIMING_RCD, EMEM_ARB_TIMING_RP, EMEM_ARB_TIMING_RC, + EMEM_ARB_TIMING_RAS, EMEM_ARB_TIMING_FAW, EMEM_ARB_TIMING_RRD, + EMEM_ARB_TIMING_RAP2PRE, EMEM_ARB_TIMING_WAP2PRE, EMEM_ARB_TIMING_R2R, + EMEM_ARB_TIMING_W2W, EMEM_ARB_TIMING_R2W, EMEM_ARB_TIMING_W2R, + EMEM_ARB_DA_TURNS, EMEM_ARB_DA_COVERS, EMEM_ARB_MISC0, + EMEM_ARB_RING1_THROTTLE, FBIO_SPARE, CFG_RSV + +optional properties: +- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change +- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL +- nvidia,emc-periodic-qrst : EMC_CFG.PERIODIC_QRST +- nvidia,emc-mode-reset : Mode Register 0 +- nvidia,emc-mode-1 : Mode Register 1 +- nvidia,emc-mode-2 : Mode Register 2 +- nvidia,emc-dsr : EMC_CFG.DYN_SELF_REF +- nvidia,emc-min-mv : Minimum voltage + + emc-table@166000 { + reg = <166000>; + compatible = "nvidia,tegra30-emc-table"; + clock-frequency = < 166000 >; + nvidia,revision = <0>; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0>; + nvidia,emc-zcal-cnt-long = <0>; + nvidia,emc-acal-interval = <0>; + nvidia,emc-periodic-qrst = <0>; + nvidia,emc-mode-reset = <0>; + nvidia,emc-mode-1 = <0>; + nvidia,emc-mode-2 = <0>; + nvidia,emc-dsr = <0>; + nvidia,emc-min-mv = <0>; + }; + +Tables for Tegra114: + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra11-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- nvidia,revision : SDRAM revision. +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-min-mv : Minimum voltage +- nvidia,source : Source name. +- nvidia,src-sel-reg : Source register settings +- nvidia, burst-regs-num : Number of emc-registers +- nvidia,emc-registers : a word array of EMC registers to be programmed + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RFC_SLR, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, + RRD, REXT, WEXT, WDV, WDV_MASK, IBDLY, PUTERM_EXTRA, CDB_CNTL_2, + QRST, RDV_MASK, REFRESH, BURST_REFRESH_NUM, PRE_REFRESH_REQ_CNT, + PDEX2WR, PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, + TXSRDLL, TCKE, TCKESR, TPD, TFAW, TRPAB, TCLKSTABLE, TCLKSTOP, + TREFBW, QUSE_EXTRA, ODT_WRITE, ODT_READ, FBIO_CFG5, CFG_DIG_DLL, + CFG_DIG_DLL_PERIOD, DLL_XFORM_DQS4, DLL_XFORM_DQS5, DLL_XFORM_DQS6, + DLL_XFORM_DQS7, DLL_XFORM_QUSE4, DLL_XFORM_QUSE5, DLL_XFORM_QUSE6, + DLL_XFORM_QUSE7, DLI_TRIM_TXDQS4, DLI_TRIM_TXDQS5, DLI_TRIM_TXDQS6, + DLI_TRIM_TXDQS7, XM2CMDPADCTRL, XM2CMDPADCTRL4, XM2DQSPADCTRL2, + XM2DQPADCTRL2, XM2CLKPADCTRL, XM2COMPPADCTRL, XM2VTTGENPADCTRL, + XM2VTTGENPADCTRL2, DSR_VTTGEN_DRV, TXDSRVTTGEN, FBIO_SPARE, + CTT_TERM_CTRL, ZCAL_INTERVAL, ZCAL_WAIT_CNT, MRS_WAIT_CNT, + MRS_WAIT_CNT2, AUTO_CAL_CONFIG2, AUTO_CAL_CONFIG3, CTT, + CTT_DURATION, DYN_SELF_REF_CONTROL, CA_TRAINING_TIMING_CNTL1, + CA_TRAINING_TIMING_CNTL2, EMEM_ARB_CFG, EMEM_ARB_OUTSTANDING_REQ, + EMEM_ARB_TIMING_RCD, EMEM_ARB_TIMING_RP, EMEM_ARB_TIMING_RC, + EMEM_ARB_TIMING_RAS, EMEM_ARB_TIMING_FAW, EMEM_ARB_TIMING_RRD, + EMEM_ARB_TIMING_RAP2PRE, EMEM_ARB_TIMING_WAP2PRE, EMEM_ARB_TIMING_R2R, + EMEM_ARB_TIMING_W2W, EMEM_ARB_TIMING_R2W, EMEM_ARB_TIMING_W2R, + EMEM_ARB_DA_TURNS, EMEM_ARB_DA_COVERS, EMEM_ARB_MISC0, + EMEM_ARB_RING1_THROTTLE +- nvidia, emc-trimmers-num : number of trimmer registers +- nvidia, emc-trimmer-0 : a word array of trimmer channel 0 settings +- nvidia, emc-trimmer-1 : a word array of trimmer channel 1 settings + The order and contents of the registers are: + CDB_CNTL_1, FBIO_CFG6, QUSE, INPUT, EINPUT_DURATION, DLL_XFORM_DQS0, + QSAFE, DLL_XFORM_QUSE0, RDV, XM2DQSPADCTRL4, XM2DQSPADCTRL3, DLL_XFORM_DQ0 + AUTO_CAL_CONFIG, DLL_XFORM_ADDR0, XM2CLKPADCTRL2, DLI_TRIM_TXDQS0, + DLL_XFORM_ADDR1, DLL_XFORM_ADDR2, DLL_XFORM_DQS1, DLL_XFORM_DQS2, + DLL_XFORM_DQS3, DLL_XFORM_DQ1, DLL_XFORM_DQ2, DLL_XFORM_DQ3, + DLI_TRIM_TXDQS1, DLI_TRIM_TXDQS2, DLI_TRIM_TXDQS3, DLL_XFORM_QUSE1, + DLL_XFORM_QUSE2, DLL_XFORM_QUSE3 + +- nvidia, burst-up-down-regs-num : Number of burst up/down registers +- nvidia, burst-up-down-regs : a word array of burst register values + The order and contents of the registers are: + PTSA_GRANT_DECREMENT, LATENCY_ALLOWANCE_G2_0, LATENCY_ALLOWANCE_G2_1, + LATENCY_ALLOWANCE_NV_0, LATENCY_ALLOWANCE_NV2_0, LATENCY_ALLOWANCE_NV_2, + LATENCY_ALLOWANCE_NV_1, LATENCY_ALLOWANCE_NV2_1, LATENCY_ALLOWANCE_NV3, + LATENCY_ALLOWANCE_EPP_0, LATENCY_ALLOWANCE_EPP_1 + +- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change +- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL +- nvidia,emc-mode-cfg : Mode config register +- nvidia,emc-mode-reset : Mode Register 0 +- nvidia,emc-mode-1 : Mode Register 1 +- nvidia,emc-mode-2 : Mode Register 2 +- nvidia,emc-mode-4 : Mode Register 4 + +optional properties: +- nvidia,emc-clock-latency-change : latency information + + emc-table@166000 { + reg = <166000>; + compatible = "nvidia,tegra11-emc-table"; + clock-frequency = < 166000 >; + nvidia,revision = <0>; + nvidia,source = "pll_m"; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0>; + nvidia,emc-zcal-cnt-long = <0>; + nvidia,emc-acal-interval = <0>; + nvidia,emc-mode-reset = <0>; + nvidia,emc-mode-1 = <0>; + nvidia,emc-mode-2 = <0>; + nvidia,emc-mode-4 = <0>; + nvidia,emc-min-mv = <0>; + }; + +Tables for Tegra124: + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra12-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- nvidia,revision : SDRAM revision. +- nvidia,dvfs-version : DVFS table versionl. +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-min-mv : Minimum voltage +- nvidia,source : Source name. +- nvidia,src-sel-reg : Source register settings. +- nvidia, burst-regs-num : Number of emc-registers. +- nvidia,burst-up-down-regs-num : Number of up_down_regs. +- nvidia,emc-registers : a word array of EMC registers to be programmed. + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RFC_SLR, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, + RRD, REXT, WEXT, WDV, WDV_MASK, QUSE, QUSE_WIDTH, IBDLY, EINPUT, + EINPUT_DURATION, PUTERM_EXTRA, PUTERM_WIDTH, PUTERM_ADJ, CDB_CNTL_1, + CDB_CNTL_2, CDB_CNTL_3, QRST, QSAFE, RDV, RDV_MASK, REFRESH, + BURST_REFRESH_NUM, PRE_REFRESH_REQ_CNT, PDEX2WR, PDEX2RD, PCHG2PDEN, + ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TXSRDLL, TCKE, TCKESR, TPD, TFAW, + TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, FBIO_CFG6, ODT_WRITE, ODT_READ, + FBIO_CFG5, CFG_DIG_DLL, CFG_DIG_DLL_PERIOD, DLL_XFORM_DQS0, + DLL_XFORM_DQS1, DLL_XFORM_DQS2, DLL_XFORM_DQS3, DLL_XFORM_DQS4, + DLL_XFORM_DQS5, DLL_XFORM_DQS6, DLL_XFORM_DQS7, DLL_XFORM_DQS8, + DLL_XFORM_DQS9, DLL_XFORM_DQS10, DLL_XFORM_DQS11, DLL_XFORM_DQS12, + DLL_XFORM_DQS13, DLL_XFORM_DQS14, DLL_XFORM_DQS15, DLL_XFORM_QUSE0, + DLL_XFORM_QUSE1, DLL_XFORM_QUSE2, DLL_XFORM_QUSE3, DLL_XFORM_QUSE4, + DLL_XFORM_QUSE5, DLL_XFORM_QUSE6, DLL_XFORM_QUSE7, DLL_XFORM_ADDR0, + DLL_XFORM_ADDR1, DLL_XFORM_ADDR2, DLL_XFORM_ADDR3, DLL_XFORM_ADDR4, + DLL_XFORM_ADDR5, DLL_XFORM_QUSE8, DLL_XFORM_QUSE9, DLL_XFORM_QUSE10, + DLL_XFORM_QUSE11, DLL_XFORM_QUSE12, DLL_XFORM_QUSE13, DLL_XFORM_QUSE14, + DLL_XFORM_QUSE15, DLI_TRIM_TXDQS0, DLI_TRIM_TXDQS1, DLI_TRIM_TXDQS2, + DLI_TRIM_TXDQS3, DLI_TRIM_TXDQS4, DLI_TRIM_TXDQS5, DLI_TRIM_TXDQS6, + DLI_TRIM_TXDQS7, DLI_TRIM_TXDQS8, DLI_TRIM_TXDQS9, DLI_TRIM_TXDQS10, + DLI_TRIM_TXDQS11, DLI_TRIM_TXDQS12, DLI_TRIM_TXDQS13, DLI_TRIM_TXDQS14, + DLI_TRIM_TXDQS15, DLL_XFORM_DQ0, DLL_XFORM_DQ1, DLL_XFORM_DQ2, + DLL_XFORM_DQ3, DLL_XFORM_DQ4, DLL_XFORM_DQ5, DLL_XFORM_DQ6, + DLL_XFORM_DQ7, XM2CMDPADCTRL, XM2CMDPADCTRL4, XM2CMDPADCTRL5, + XM2DQSPADCTRL2, XM2DQPADCTRL2, XM2DQPADCTRL3, XM2CLKPADCTRL, + XM2CLKPADCTRL2, XM2COMPPADCTRL, XM2VTTGENPADCTRL, XM2VTTGENPADCTRL2, + XM2VTTGENPADCTRL3, XM2DQSPADCTRL3, XM2DQSPADCTRL4, XM2DQSPADCTRL5, + XM2DQSPADCTRL6, DSR_VTTGEN_DRV, TXDSRVTTGEN, FBIO_SPARE, ZCAL_INTERVAL, + ZCAL_WAIT_CNT, MRS_WAIT_CNT, MRS_WAIT_CNT2, AUTO_CAL_CONFIG2, + AUTO_CAL_CONFIG3, AUTO_CAL_CONFIG, CTT, CTT_DURATION, CFG_PIPE, + DYN_SELF_REF_CONTROL, QPOP, EMEM_ARB_CFG, EMEM_ARB_OUTSTANDING_REQ, + EMEM_ARB_TIMING_RCD, EMEM_ARB_TIMING_RP, EMEM_ARB_TIMING_RC, + EMEM_ARB_TIMING_RAS, EMEM_ARB_TIMING_FAW, EMEM_ARB_TIMING_RRD, + EMEM_ARB_TIMING_RAP2PRE, EMEM_ARB_TIMING_WAP2PRE, EMEM_ARB_TIMING_R2R, + EMEM_ARB_TIMING_W2W, EMEM_ARB_TIMING_R2W, EMEM_ARB_TIMING_W2R, + EMEM_ARB_DA_TURNS, EMEM_ARB_DA_COVERS, EMEM_ARB_MISC0, + EMEM_ARB_RING1_THROTTLE + +- nvidia, burst-up-down-regs : a word array of burst register values + The order and contents of the registers are: + MLL_MPCORER_PTSA_RATE, PTSA_GRANT_DECREMENT, LATENCY_ALLOWANCE_XUSB_0, + LATENCY_ALLOWANCE_XUSB_1, LATENCY_ALLOWANCE_TSEC_0, + LATENCY_ALLOWANCE_SDMMCA_0,LATENCY_ALLOWANCE_SDMMCAA_0, + LATENCY_ALLOWANCE_SDMMC_0, LATENCY_ALLOWANCE_SDMMCAB_0, + LATENCY_ALLOWANCE_PPCS_0, LATENCY_ALLOWANCE_PPCS_1, + LATENCY_ALLOWANCE_MPCORE_0, LATENCY_ALLOWANCE_MPCORELP_0, + LATENCY_ALLOWANCE_HC_0, LATENCY_ALLOWANCE_HC_1, + LATENCY_ALLOWANCE_AVPC_0, LATENCY_ALLOWANCE_GPU_0, + LATENCY_ALLOWANCE_MSENC_0, LATENCY_ALLOWANCE_HDA_0, + LATENCY_ALLOWANCE_VIC_0, LATENCY_ALLOWANCE_VI2_0, + LATENCY_ALLOWANCE_ISP2_0, LATENCY_ALLOWANCE_ISP2_1, + LATENCY_ALLOWANCE_ISP2B_0, LATENCY_ALLOWANCE_ISP2B_1, + LATENCY_ALLOWANCE_VDE_0, LATENCY_ALLOWANCE_VDE_1, + LATENCY_ALLOWANCE_VDE_2, LATENCY_ALLOWANCE_VDE_3, + LATENCY_ALLOWANCE_SATA_0, LATENCY_ALLOWANCE_AFI_0 + +- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change +- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL +- nvidia,emc-ctt-term_ctrl : Configure CTT termination output drive strength +- nvidia,emc-cfg : Configuration Register +- nvidia,emc-cfg-2 : EMC Configuration 2 +- nvidia,emc-sel-dpd-ctrl : Configures functional SEL_DPD modes +- nvidia,emc-cfg-dig-dll : Configure Digital DLL. +- nvidia,emc-mode-0 : Mode Register 0 +- nvidia,emc-mode-1 : Mode Register 1 +- nvidia,emc-mode-2 : Mode Register 2 +- nvidia,emc-mode-4 : Mode Register 4 + +optional properties: +- nvidia,gk20a-min-mv : gpu min voltage + + emc-table@40800 { + compatible = "nvidia,tegra12-emc-table"; + nvidia,revision = <0>; + nvidia,dvfs-version = "04_40800_0_V5.0.1_V0.3"; + clock-frequency = <40800>; + nvidia,emc-min-mv = <0>; + nvidia,gk20a-min-mv = <800>; + nvidia,source = "pllp_out0"; + nvidia,src-sel-reg = <0>; + nvidia,burst-regs-num = <167>; + nvidia,burst-up-down-regs-num = <31>; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0>; + nvidia,emc-burst-up-down-regs = < + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0>; + nvidia,emc-zcal-cnt-long = <0>; + nvidia,emc-acal-interval = <0>; + nvidia,emc-ctt-term_ctrl = <0>; + nvidia,emc-cfg = <0>; + nvidia,emc-cfg-2 = <0>; + nvidia,emc-sel-dpd-ctrl = <0>; + nvidia,emc-cfg-dig-dll = <0>; + nvidia,emc-mode-0 = <0>; + nvidia,emc-mode-1 = <0>; + nvidia,emc-mode-2 = <0>; + nvidia,emc-mode-4 = <0>; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-dvfs.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-dvfs.txt new file mode 100644 index 000000000000..0ecc7aeef42a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-dvfs.txt @@ -0,0 +1,50 @@ +NVIDIA Tegra30 DVFS tables + +dvfs-tables node: +All the tables must be contained in dvfs-tables parent node. This node is just +container for all dvfs tables, it does not have any compatible property. + +Tables: +Required properties for child nodes of dvfs-tables: + +compatible: Must be any of + "nvidia,tegra30-cpu-dvfs" for CPU dvfs tables or + "nvidia,tegra30-cpu0-dvfs" for cpu0 dvfs tables or + "nvidia,tegra30-core-dvfs" for core dvfs tables. + +voltage-table: Voltage steps for rail. Unit for voltage value is mV. + +#address-cells: Should be 0. +#size-cells: Should be 1. + +Frequency tables: + +Frequency tables are grouped using the combination of speedo-id, process-id and manual-dvfs. + +Required properties: + +reg: Can be any number but same as used in node name. Should be unique within the dvfs table. +clock-name: Clock name for which frequencies are mentioned in table. +frequencies: Array of frequencies. Unit for frequency is KHz. + +Optional properties: +speedo-id: If not present, speedo id value will be -1. +process-id: If not present, process id value will be -1. +manual-dvfs: If not present, dvfs for the clocks in this frequency table is auto. + +Example: + + dvfs-tables { + cpudvfs { + compatible = "nvidia,tegra30-cpu-dvfs"; + voltage-table = <800 825 850 875 900 916 950 975 1000 1007 1025 1050 1075 1100 1125 1150 1175 1200 1212 1237>; + + frequency-table@1 { + reg = <1>; + speedo-id = <0>; + process-id = <0>; + clock-name = "cpu_g"; + frequencies = <1 1 684000 684000 817000 817000 817000 1026000 1102000 1102000 1149000 1187000 1225000 1282000 1300000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/clk-palmas.txt b/Documentation/devicetree/bindings/clock/clk-palmas.txt new file mode 100644 index 000000000000..851f7832de58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/clk-palmas.txt @@ -0,0 +1,36 @@ +* palmas clock IP block devicetree bindings + +Required properties: +- compatible : Must be "ti,palmas-clk". + +Optional sub-nodes: + The Palmas clock node have the subnode to configure the Palmas'c clock. + The subnode name should match with the name of the clocks. + + The valid clock names are: clk32k_kg and clk32k_kg_audio. + +- ti,clock-boot-enable: Enable the clock on boot time. +- ti,external-sleep-control: Sleep control for the clock. The clock + is enabled/disabled through external pins. + The valid value for external pins are: + ENABLE1 then 1, + ENABLE2 then 2 or + NSLEEP then 3. +Example: + +pmic { + compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; + ... + clocks { + compatible = "ti,palmas-clk"; + clk32k_kg { + ti,clock-boot-enable; + ti,external-sleep-control = <3>; + } + + clk32k_kg_audio { + ti,clock-boot-enable; + }; + }; + ... +}; diff --git a/Documentation/devicetree/bindings/edp/sysedp_batmon_calc.txt b/Documentation/devicetree/bindings/edp/sysedp_batmon_calc.txt new file mode 100644 index 000000000000..1237b3254c0f --- /dev/null +++ b/Documentation/devicetree/bindings/edp/sysedp_batmon_calc.txt @@ -0,0 +1,56 @@ +System-EDP Battery Monitor + +Required properties: +- compatible : "nvidia,tegra124-sysedp_batmon_calc" +- ocv_lut: The property contains several sets of combinations of + capacity battery remained and battery open-circuit-voltage (in uV). + Take <60 7641110> for exmaple, it means the battery + open-circuit-voltage is 7641.11mV when battery remained capacity is + 60%. Entries must be in descending order wrt capacity and last entry + must be <0 ...>. +- update_interval: The defines the period (in ms) for system to update the + available power budget. +- ibat_lut: This defines the maximum allowed current (in mA) from the + battery under specific temperature. The property contains several + sets of combinations of temperature and current with the format of + <C mA>. C is the temperature in Celcius, negative values reprented + with 2's complement. mA is the maximum current battery can supply + under this temperature. Take <60 6150> for example, this means that + battery can supply 6150mA when temperature is 60 degree + Celsius. Entries must be in descending order wrt temperature and + last entry must be <... 0>. +- rbat_data: An array of battery impedance (in uOhm) under different temperatures + and capacity. +- temp_axis: An array of different temperatures. Negative values are + represented with 2's complement +- capacity_axis: An array of capacity battery remains. +- power_supply : The name of system power supply. +- r_const: This value describes the system impedance(in uOhm). +- vsys_min: The minmum voltage (in uV) needed for PMIC. + +Example: + sysedp_batmon_calc { + compatible = "nvidia,tegra124-sysedp_batmon_calc"; + update_interval = <30000>; + ocv_lut = < + 100 8372010 + 60 7641110 + 0 5999850 + >; + ibat_lut = < + 60 6150 + 40 6150 + 0 6150 + S32_TO_U32(-30) 0 + >; + rbat_data = < + 70000 + 70000 + 90000 + >; + temp_axis = <25>; + capacity_axis = <100 13 0>; + power_supply = "battery"; + r_const = <60000>; + vsys_min = <2900000>; + }; diff --git a/Documentation/devicetree/bindings/extcon/extcon-palmas.txt b/Documentation/devicetree/bindings/extcon/extcon-palmas.txt new file mode 100644 index 000000000000..723aaf798a08 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-palmas.txt @@ -0,0 +1,16 @@ +EXTCON FOR PALMAS/TWL CHIPS + +PALMAS USB COMPARATOR +Required Properties: + - compatible : Should be "ti,palmas-usb" or "ti,twl6035-usb" + +Optional Properties: + - ti,wakeup : To enable the wakeup comparator in probe + - ti,enable-id-detection: Perform ID detection. + - ti,enable-vbus-detection: Perform VBUS detection. + - extcon-name: Name of extcon connection. + +palmas-usb { + compatible = "ti,twl6035-usb", "ti,palmas-usb"; + ti,wakeup; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index d933af370697..dc90b0559269 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -53,6 +53,40 @@ Example of the node using GPIOs: In this example gpio-specifier is "18 0" and encodes GPIO pin number, and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. +1.1) Default initialisation of GPIOs: +----------------------------------- +The GPIOs can be set as input or output-low or output-high during +GPIO registration with gpiolib. +The two properties are provided with this +- gpio-init-names: The state names of the GPIO initialisation. +- gpio-init-0: The state 0 node handle for GPIO initialisation. + : +- gpio-init-n: The state n node handle for GPIO initialisation. + +The subnode property: +-------------------- +The subnode should have following properties with the list of GPIOs number +belongs to that device. +- gpio-input: The list of GPIOs to be set as input. +- gpio-output-low: The list of GPIOs to be set as output with low output. +- gpio-output-high: The list of GPIOs to be set as output with high output. + +Example: + gpio: gpio@6000d000 { + gpio-init-names = "default"; + gpio-init-0 = <&gpio_default>; + + gpio_default: default { + gpio-input = <189 190 178 179>; + gpio-output-low = <188 191>; + gpio-output-high = <149 138>; + }; + }; + +Here GPIO driver will have one state "default" and with this, the GPIOs +189, 190, 178, 179 are set as input, 188 and 191 are set as output low and +GPIOs 149 and 138 are set as GPIO output-high. + 2) gpio-controller nodes ------------------------ diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra-host1x.txt index b4fa934ae3a2..8223e7572eaf 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra-host1x.txt @@ -9,6 +9,7 @@ Required properties: - #size-cells: The number of cells used to represent the size of an address range in the host1x address space. Should be 1. - ranges: The mapping of the host1x address space to the CPU address space. +- nvidia,memory-clients: memory client ID of the controller. The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -26,6 +27,7 @@ of the following host1x client modules: - compatible: "nvidia,tegra<chip>-vi" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. + - nvidia,memory-clients: memory client ID of the controller. - epp: encoder pre-processor @@ -40,6 +42,7 @@ of the following host1x client modules: - compatible: "nvidia,tegra<chip>-isp" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. + - nvidia,memory-clients: memory client ID of the controller. - gr2d: 2D graphics engine @@ -60,6 +63,7 @@ of the following host1x client modules: - compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. + - nvidia,memory-clients: memory client ID of the controller. Each display controller node has a child node, named "rgb", that represents the RGB output associated with the controller. It can take the following @@ -95,6 +99,35 @@ of the following host1x client modules: - compatible: "nvidia,tegra<chip>-dsi" - reg: Physical base address and length of the controller's registers. +- msenc: Multi-Stream Encoder + + Required properties: + - compatible: "nvidia,tegra<chip>-msenc" + - reg: Physical base address and length of the controller's registers. + - nvidia,memory-clients: memory client ID of the controller. + +- tsec: Tegra Security Engine Controller + + Required properties: + - compatible: "nvidia,tegra<chip>-tsec" + - reg: Physical base address and length of the controller's registers. + - nvidia,memory-clients: memory client ID of the controller. + +- vic: Video Image Compositor + + Required properties: + - compatible: "nvidia,tegra<chip>-vic" + - reg: Physical base address and length of the controller's registers. + - nvidia,memory-clients: memory client ID of the controller. + +- gk20a: Kepler GPU + + Required properties: + - compatible: "nvidia,tegra<chip>-gk20a" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - nvidia,memory-clients: memory client ID of the controller. + Example: / { @@ -105,6 +138,7 @@ Example: reg = <0x50000000 0x00024000>; interrupts = <0 65 0x04 /* mpcore syncpt */ 0 67 0x04>; /* mpcore general */ + nvidia,memory-clients = <6>; #address-cells = <1>; #size-cells = <1>; @@ -121,6 +155,7 @@ Example: compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; interrupts = <0 69 0x04>; + nvidia,memory-clients = <18>; }; epp { @@ -133,6 +168,7 @@ Example: compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; interrupts = <0 71 0x04>; + nvidia,memory-clients = <8>; }; gr2d { @@ -150,6 +186,7 @@ Example: compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; + nvidia,memory-clients = <2>; rgb { status = "disabled"; @@ -160,6 +197,7 @@ Example: compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; + nvidia,memory-clients = <3>; rgb { status = "disabled"; @@ -185,6 +223,35 @@ Example: reg = <0x54300000 0x00040000>; status = "disabled"; }; + + vic { + compatible = "nvidia,tegra124-vic"; + reg = <0x54340000 0x00040000>; + nvidia,memory-clients = <19>; + }; + + msenc { + compatible = "nvidia,tegra124-msenc"; + reg = <0x544c0000 0x00040000>; + nvidia,memory-clients = <11>; + }; + + tsec { + compatible = "nvidia,tegra124-tsec"; + reg = <0x54500000 0x00040000>; + nvidia,memory-clients = <23>; + }; + + gk20a { + compatible = "nvidia,tegra124-gk20a"; + reg = <0x538F0000 0x00001000>, + <0x57000000 0x01000000>, + <0x58000000 0x01000000>; + interrupts = <0 157 0x04 + 0 158 0x04>; + nvidia,memory-clients = <56 57>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra-i2c.txt new file mode 100644 index 000000000000..742cb8b0fbd1 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra-i2c.txt @@ -0,0 +1,35 @@ +NVIDIA I2C controller driver interface. + +Required properties: +- compatible : The driver is compatible with + "nvidia,tegra114-i2c". + "nvidia,tegra30-i2c". + "nvidia,tegra20-i2c", + "nvidia,tegra20-i2c-dvc". +- reg: Should contain I2C registers location and length. +- interrupts: Should contain I2C interrupts. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for this SLINK controller. + +Recommended properties: +- clock-frequency: desired I2C bus clock frequency in Hz. + +Optional properties: +- nvidia,clock-always-on: If clock should be always ON and dynamic clock management + need to be disable. +- nvidia,hs-master-code: Hisgh speed master code if highspeed mode need to be enable. + +Example: + + i2c@7000c000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + clock-frequency = <100000>; + nvidia,clock-always-on; + nvidia,hs-master-code = <0x1234>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + diff --git a/Documentation/devicetree/bindings/iio/adc/palmas-gpadc.txt b/Documentation/devicetree/bindings/iio/adc/palmas-gpadc.txt new file mode 100644 index 000000000000..32a3ed146ebe --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/palmas-gpadc.txt @@ -0,0 +1,49 @@ +* Palmas general purpose ADC IP block devicetree bindings + +Required properties: +- compatible : Must be "ti,palmas-gpadc". + +Optional sub-nodes: +ti,channel0-current-microamp: Channel 0 current in uA. + Valid values 0uA, 5uA, 15uA, 20uA. +ti,channel3-current-microamp: Channel 3 current in uA. + Valid value 0uA, 10uA, 400uA, 800uA. +ti,enable-channel3-dual-current: Enable dual current on channel 3. +ti,enable-extended-delay: Enable extended delay. + +Optional sub-node: +The Palmas ADC node has optional subnode to define the iio mapping. +It is the name with "iio_map". This node has again subnode to define +the property of the channel. The sub subnode has following properties: +- ti,adc-channel-number: ADC channel numbber. +- ti,adc-consumer-device: Consumer device name. +- ti,adc-consumer-channel: ADC consumer channel name. + +Example: + +pmic { + compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; + ... + gpadc { + compatible = "ti,palmas-gpadc"; + interrupts = <18 0 + 16 0 + 17 0>; + ti,channel0-current-microamp = <5>; + ti,channel3-current-microamp = <10>; + iio_map { + ch1 { + ti,adc-channel-number = <1>; + ti,adc-consumer-device = "generic-adc-thermal.0"; + ti,adc-consumer-channel ="battery-temp-channel"; + }; + + ch6 { + ti,adc-channel-number = <6>; + ti,adc-consumer-device = "palmas-battery"; + ti,adc-consumer-channel ="vbat_channel"; + }; + }; + }; + ... +}; diff --git a/Documentation/devicetree/bindings/input/ak-akm89xx.txt b/Documentation/devicetree/bindings/input/ak-akm89xx.txt new file mode 100644 index 000000000000..e91c08ee2ebd --- /dev/null +++ b/Documentation/devicetree/bindings/input/ak-akm89xx.txt @@ -0,0 +1,25 @@ +* Asahi Kasei AKM89XX compass sensor + +Required properties: +- compatible: should be one of the following. + - "ak,ak8963" + - "ak,ak8972" + - "ak,ak8975" +- reg: the I2C address of AKM89XX +- config: the selection determines the device behavior. + - "auto": auto detect connection to MPU + - "mpu": connected to MPU + - "host": connected to host +- orientation: the orientation matricies are 3x3 rotation matricies that are + applied to the data to rotate from the mounting orientation to the platform + orientation. The values must be one of 0, 1, or -1(0xff in byte array) and + each row and column should have exactly 1 non-zero value. + +Example: + +akm8963@0d { + compatible = "ak,ak8963"; + reg = <0x0d>; + orientation = [00 01 00 ff 00 00 00 00 01]; + config = "mpu"; +}; diff --git a/Documentation/devicetree/bindings/input/capella-cm3217.txt b/Documentation/devicetree/bindings/input/capella-cm3217.txt new file mode 100644 index 000000000000..92688eb74110 --- /dev/null +++ b/Documentation/devicetree/bindings/input/capella-cm3217.txt @@ -0,0 +1,12 @@ +* Capella CM3217 Ambient light sensor + +Required properties: +- compatible: "capella,cm3217" +- reg : the I2C address of CM3217 + +Example: + +cm3217@10 { + compatible = "capella,cm3217"; + reg = <0x10>; +}; diff --git a/Documentation/devicetree/bindings/input/inv-mpu-sensors.txt b/Documentation/devicetree/bindings/input/inv-mpu-sensors.txt new file mode 100644 index 000000000000..f29d202ff866 --- /dev/null +++ b/Documentation/devicetree/bindings/input/inv-mpu-sensors.txt @@ -0,0 +1,42 @@ +* Invensense MPU6xxx Gyro + Accelerometer +* Invensense MPU9xxx Gyro + Accelerometer + Compass + +Required properties: +- compatible: The driver is compatible with + "invensense,itg3500" + "invensense,mpu3050" + "invensense,mpu6050" + "invensense,mpu9150" + "invensense,mpu6500" + "invensense,mpu9250" + "invensense,mpu6xxx" +- reg: the I2C address +- interrupt-parent: the interrupt controller that it is attached to. +- interrupts: The intterrupt property of device node. +- invensense,int_config: Bits [7:3] of the int config register. +- invensense,level_shifter: 0: VLogic, 1: VDD +- invensense,orientation: the orientation matricies are 3x3 rotation matricies + that are applied to the data to rotate from the mounting orientation to the + platform orientation. The values must be one of 0, 1, or -1(0xff in byte + array) and each row and column should have exactly 1 non-zero value. +- invensense,sec_slave_type: secondary slave device type + 0: SECONDARY_SLAVE_TYPE_NONE + 1: SECONDARY_SLAVE_TYPE_ACCEL + 2: SECONDARY_SLAVE_TYPE_COMPASS + 3: SECONDARY_SLAVE_TYPE_PRESSURE +- invensense,key: key for MPL library. + +Example: + +mpu9250@69 { + compatible = "invensense,mpu9250"; + reg = <0x69>; + interrupt-parent = <&gpio>; + interrupts = <144 0x01>; + invensense,int_config = <0x10>; + invensense,level_shifter = <0>; + invensense,orientation = [01 00 00 00 01 00 00 00 01]; + invensense,sec_slave_type = <0>; + invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89]; +}; + diff --git a/Documentation/devicetree/bindings/input/solteam-jsa1127.txt b/Documentation/devicetree/bindings/input/solteam-jsa1127.txt new file mode 100644 index 000000000000..e6dd6301cab0 --- /dev/null +++ b/Documentation/devicetree/bindings/input/solteam-jsa1127.txt @@ -0,0 +1,29 @@ +* Solteam Opto Light Sensor JSA-1127 + +Required properties: +- compatible: should be from the list below + "solteam-opto,jsa1127" +- reg: I2C Address +- solteam-opto,rint: resistor for adjusting integration time +- solteam-opto,integration-time: integration time +- solteam-opto,use-internal-integration-time: switch to en/disable + using internal integration time + 0: disable + 1: enable +- solteam-opto,tint-coeff: integration time coefficient +- solteam-opto,noisy: noisy option will make driver report values in + random variations to make ALS's applications working normally + 0: disable + 1: enable + +Example: + +jsa1127@39 { + compatible = "solteam-opto,jsa1127"; + reg = <0x39>; + solteam-opto,rint = <100>; + solteam-opto,integration-time = <200>; + solteam-opto,use-internal-integration-timing = <1>; + solteam-opto,tint-coeff = <22>; + solteam-opto,noisy = <1>; +}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/raydium_rm_ts_spidev.txt b/Documentation/devicetree/bindings/input/touchscreen/raydium_rm_ts_spidev.txt new file mode 100644 index 000000000000..947c6c1e3259 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/raydium_rm_ts_spidev.txt @@ -0,0 +1,28 @@ +raydium touch. + +Required properties: +- compatible : should be "raydium,rm_ts_spidev". +- reg: Should contain registers location and length. +- interrupts: Should contain touch interrupts. +- rx-clk-tap-delay: should contain rx_clk_tap_delay in tegra_spi_device_controller_data +- tx-clk-tap-delay: should contain tx_clk_tap_delay in tegra_spi_device_controller_data +- reset-gpio: gpio spec for touch reset +- platform-id: value for spec platform_id in rm_spi_ts_platform_data +- name-of-clock: spec clock name for name_of_clock in rm_spi_ts_platform_data +- name-of-clock-con: spec clock name for name_of_clock_con in rm_spi_ts_platform_data + +Example: + + spi-touch@0 { + compatible = "raydium,rm_ts_spidev"; + reg = <0>; /* spi chip select 0 */ + spi-max-frequency = <12000000>; + interrupt-parent = <&gpio>; + interrupts = <82 0x01>; /* GPIO_PK2 */ + reset-gpio = <&gpio 84 0>; /* GPIO_PK4 */ + config = <0>; + platform-id = <0x8>; + name-of-clock = "clk_out_2"; + name-of-clock-con = "extern2"; + }; + diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt deleted file mode 100644 index 89fb5434b730..000000000000 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) - -Required properties: -- compatible : "nvidia,tegra30-smmu" -- reg : Should contain 3 register banks(address and length) for each - of the SMMU register blocks. -- interrupts : Should contain MC General interrupt. -- nvidia,#asids : # of ASIDs -- dma-window : IOVA start address and length. -- nvidia,ahb : phandle to the ahb bus connected to SMMU. - -Example: - smmu { - compatible = "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x05c>; - nvidia,#asids = <4>; /* # of ASIDs */ - dma-window = <0 0x40000000>; /* IOVA start & length */ - nvidia,ahb = <&ahb>; - }; diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt new file mode 100644 index 000000000000..c9f157f9f67a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/palmas.txt @@ -0,0 +1,52 @@ +* palmas device tree bindings + +The TI palmas family current members :- +twl6035 (palmas) +twl6037 (palmas) +tps65913 (palmas) +tps65914 (palmas) +tps659038 +tps80036 + +Required properties: +- compatible : Should be from the list + ti,twl6035 + ti,twl6036 + ti,twl6037 + ti,tps65913 + ti,tps65914 + ti,tps80036 + ti,tps659038 +and also the generic series names + ti,palmas +- interrupt-controller : palmas has its own internal IRQs +- #interrupt-cells : should be set to 2 for IRQ number and flags + The first cell is the IRQ number. + The second cell is the flags, encoded as the trigger masks from + Documentation/devicetree/bindings/interrupts.txt +- interrupt-parent : The parent interrupt controller. + +Optional properties: + ti,mux-padX : set the pad register X (1-2) to the correct muxing for the + hardware, if not set will use muxing in OTP. + +Example: + +palmas { + compatible = "ti,twl6035", "ti,palmas"; + reg = <0x48> + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <2>; + + ti,mux-pad1 = <0>; + ti,mux-pad2 = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + pmic { + compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; + .... + }; +} diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index c6d7b11db9eb..236dc63d525f 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -8,9 +8,15 @@ by mmc.txt and the properties used by the sdhci-tegra driver. Required properties: - compatible : Should be "nvidia,<chip>-sdhci" +- base-clk : Integer. Optional properties: - power-gpios : Specify GPIOs for power control +- tap-delay : Integer. Valid range 0...31. +- trim-delay : Integer. Valid range 0...255. +- ddr-clk-limit : Integer. +- built-in : Boolean, indicates whether it is built-in card or not. +- mmc-ocr-mask : 0: 1V8, 1: 2V8. Example: @@ -22,4 +28,5 @@ sdhci@c8000200 { wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <8>; + base-clk = <104000000>; }; diff --git a/Documentation/devicetree/bindings/nvidia,imx135.txt b/Documentation/devicetree/bindings/nvidia,imx135.txt new file mode 100644 index 000000000000..bde03160e623 --- /dev/null +++ b/Documentation/devicetree/bindings/nvidia,imx135.txt @@ -0,0 +1,29 @@ +NVIDIA Camera sensor imx135 driver interface. + +Required properties: +- compatible : The driver is compatible with + "nvidia,imx135". + +- cam1_gpios : Camera GPIO. + +- reset_gpios : Reset GPIO. + +- af_gpios : AF1 GPIO. + +- reg: Should contain I2C slave address of the driver. + +- nvidia,ext_reg : For few platforms this driver needs extra power regulators +to be enabled. This bool property indicates the same. It must be programmed +only when imx135 driver needs extra power rails for particular platform. + +Example: + + imx135@10 { + compatible = "nvidia,imx135"; + cam1-gpios = <&gpio 221 0>; /* gpio PBB5 */ + reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ + af-gpios = <&gpio 225 0>; /* gpio PCC1 */ + nvidia,ext_reg; /* Extra power-regulators needed */ + reg = <0x10>; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index c95ea8278f87..34155c2534e1 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -126,3 +126,52 @@ device; they may be grandchildren, for example. Whether this is legal, and whether there is any interaction between the child and intermediate parent nodes, is again defined entirely by the binding for the individual pin controller device. + +== Using generic pinconfig options == + +Generic pinconfig parameters can be used by defining a separate node containing +the applicable parameters (and optional values), like: + +pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + drive-strength = <20>; +}; + +This node should then be referenced in the appropriate pinctrl node as a phandle +and parsed in the driver using the pinconf_generic_parse_dt_config function. + +Supported configuration parameters are: + +bias-disable - disable any pin bias +bias-high-impedance - high impedance mode ("third-state", "floating") +bias-bus-hold - latch weakly +bias-pull-up - pull up the pin +bias-pull-down - pull down the pin +bias-pull-pin-default - use pin-default pull state +drive-push-pull - drive actively high and low +drive-open-drain - drive with open drain +drive-open-source - drive with open source +drive-strength - sink or source at most X mA +input-schmitt-enable - enable schmitt-trigger mode +input-schmitt-disable - disable schmitt-trigger mode +input-debounce - debounce mode with debound time X +low-power-enable - enable low power mode +low-power-disable - disable low power mode +output-low - set the pin to output mode with low level +output-high - set the pin to output mode with high level + +Arguments for parameters: + +- bias-pull-up, -down and -pin-default take as optional argument 0 to disable + the pull, on hardware supporting it the pull strength in Ohm. bias-disable + will also disable any active pull. + +- drive-strength takes as argument the target strength in mA. + +- input-debounce takes the debounce time in usec as argument + or 0 to disable debouncing + +All parameters not listed here, do not take an argument. + +More in-depth documentation on these parameters can be found in +<include/linux/pinctrl/pinconfig-generic.h> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt new file mode 100644 index 000000000000..734d9b04d533 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt @@ -0,0 +1,96 @@ +Palmas Pincontrol bindings + +The pins of Palmas device can be set on different option and provides +the configuration for Pull UP/DOWN, open drain etc. + +Required properties: +- compatible: It must be one of following: + - "ti,palmas-pinctrl" for Palma series of the pincontrol. + - "ti,tps65913-pinctrl" for Palma series device TPS65913. + - "ti,tps80036-pinctrl" for Palma series device TPS80036. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Palmas's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +list of pins. This configuration can include the mux function to select on +those pin(s), and various pin configuration parameters, such as pull-up, +open drain. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Optional properties: +- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode. + Selection primary or secondary function associated to I2C2_SCL_SCE, + I2C2_SDA_SDO pin/pad for DVFS1 interface +- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode. + Selection primary or secondary function associated to GPADC_START + and SYSEN2 pin/pad for DVFS2 interface + +This binding uses the following generic properties as defined in +pinctrl-bindings.txt: + +Required: pins +Options: function, bias-disable, bias-pull-up, bias-pull-down, + bias-pin-default, drive-open-drain. + +Note that many of these properties are only valid for certain specific pins. +See the Palmas device datasheet for complete details regarding which pins +support which functionality. + +Valid values for pin names are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, + gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood, + nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2, + int. + +Valid value of function names are: + gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det, + vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm, + simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start, + reset_in, nsleep, enable. + +There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these +functions is selected then directly pins register will be written with 0, 1, 2 +or 3 respectively if it is valid for that pins or list of pins. + +Example: + palmas: tps65913 { + .... + pinctrl { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_pins_state>; + + palmas_pins_state: pinmux { + gpio0 { + pins = "gpio0"; + function = "id"; + bias-pull-up; + }; + + vac { + pins = "vac"; + function = "vacok"; + bias-pull-down; + }; + + gpio5 { + pins = "gpio5"; + function = "opt0"; + drive-open-drain = <1>; + }; + }; + }; + .... + }; diff --git a/Documentation/devicetree/bindings/power/bq2419x-charger.txt b/Documentation/devicetree/bindings/power/bq2419x-charger.txt new file mode 100644 index 000000000000..b47812c66097 --- /dev/null +++ b/Documentation/devicetree/bindings/power/bq2419x-charger.txt @@ -0,0 +1,90 @@ +* bq2419x charger devicetree bindings + +Required properties: +- compatible : Should be from the list + ti,bq2419x + to be drawn by the charger from the power source. + +Required nodes: +- regulators: There must a regulator subnode each for the following purposes: + (1) Setting battery charging current. + (2) Enabling current supply to vbus (To enable otg mode) + Each of these regulator nodes must have atleast one consumer + subnode which in turn must have certain mandatory properties + supplied. To know about these mandatory properties and more about + consumer subnodes, please refer + Documentation/devicetree/bindings/regulator/regulator.txt + +Additional properties to be added to charger regulator subnode: + +Required properties: +- auto-recharge-time : Time interval in seconds after which the charging + should be restarted after the charging is complete. + +Optional properties: +- watchdog-timeout : Watchdog timer expiry timeout value in seconds. + When not specified, watchdog timer functionality + will be disabled. +- rtc-alarm-time : Time setting in seconds for the rtc alarm timer + which wakes the board up for charging after shutdown. +- ti,temp-range: List of temperatures in degC for thermal profiling. +- ti,charge-current-limit: List of fast charging current limit in mA for + thermal profiling. + The value is provided as + ti,temp-range = <15 60>; + ti,charge-current-limit = <2048 5200>; + + This will set chargign current limit to + 2048 for <= 15 degC and + 5200 for 16 to 60 degC + This will result: + < 0 -> Charger disable. (As by HW) + 0 to 10 -> 1048mA charging current limit (as by 50% HW) + 11 to 15 -> 2048mA + 16 to 60 -> 5200 mA + > 60 : Charging will be disabled by HW. + +Subnode properties: +================== +There is two optional subnodes, vbus and charger. + +vbus properties: +================ +otg-iusb-gpio: The GPIO which is connected to OTG/IUSB pin. + + +Example +bq2419x: bq2419x@6b { + compatible = "ti,bq2419x"; + reg = <0x6b>; + ti,charging-term-current-mA = <100>; + charger { + regulator-name = "batt_regulator"; + regulator-max-microamp = <3000>; + ti,watchdog-timeout = <40>; + ti,rtc-alarm-time = <3600>; + ti,auto-recharge-time = <1800>; + consumers { + c1 { + regulator-consumer-supply = "usb_bat_chg"; + regulator-consumer-device = "tegra-udc.0"; + }; + }; + }; + vbus { + regulator-name = "vbus_regulator"; + consumers { + c1 { + regulator-consumer-supply = "usb_vbus"; + regulator-consumer-device = "tegra-ehci.0"; + }; + + c2 { + regulator-consumer-supply = "usb_vbus"; + regulator-consumer-device = "tegra-otg"; + }; + }; + }; +}; + + diff --git a/Documentation/devicetree/bindings/power/reset/palmas-poweroff.txt b/Documentation/devicetree/bindings/power/reset/palmas-poweroff.txt new file mode 100644 index 000000000000..61beae9330be --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/palmas-poweroff.txt @@ -0,0 +1,15 @@ +Power off for Palmas series devices. + +Required Properties: + - compatible : Must be "ti,palmas-pm" + +Optional Properties: + - system-pmic-power-off : Use system PMIC to power off device. + - system-pmic-power-reset : Use system PMIC to power reset device. + +Example: +palmas_power { + compatible = "ti,palmas-pm"; + system-pmic-power-off; + system-pmic-power-reset; +}; diff --git a/Documentation/devicetree/bindings/power_supply/bq27441_battery.txt b/Documentation/devicetree/bindings/power_supply/bq27441_battery.txt new file mode 100644 index 000000000000..349cb4239166 --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/bq27441_battery.txt @@ -0,0 +1,29 @@ +bq27441 battery +~~~~~~~~~~~~~~~~ + +Required properties : + - compatible : Should contain "ti,bq27441". + - ti,tz-name : Thermal zone name. +Optional properties : + - ti,design-capacity : The designed battery capacity used for + gauge's predictions. in mAh. + - ti,design-energy : The designed battery energy. in mWh. + - ti,taper-rate : The current threshold below which your charger + IC is set to stop charging once it considers the battery to be + full. in mA. + - ti,terminate-voltage : Should be set to the minimum operating + voltage of your system. This is the target where the gauge + typically reports 0% capacity. in mV. + - ti,v-at-chg-term : Voltage at charge termination. in mV. + +Example: + + bq27441@55 { + compatible = "ti,bq27441"; + ti,design-capacity = <7800>; + ti,design-energy = <28314>; + ti,taper-rate = <167>; + ti,terminate-voltage = <3150>; + ti,v-at-chg-term = <4200>; + ti,tz-name = "battery-temp"; + }; diff --git a/Documentation/devicetree/bindings/power_supply/cw201x_battery.txt b/Documentation/devicetree/bindings/power_supply/cw201x_battery.txt new file mode 100644 index 000000000000..7739cc35fe68 --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/cw201x_battery.txt @@ -0,0 +1,25 @@ +cw201x_battery +~~~~~~~~~~~~~~~~ + +Required properties : + - compatible : Should contain "cw,cw201x". + - alert-threshold : Alert threshold. in %(percentage). 0~32. + - profile-tbl : Custom profile data. This should be 64 entries(64 bytes). + This value depends on custom model. + +Contact Cellwise for details on how to configure the values involved with custom model. + +Example: + cw201x@62 { + compatible = "cw,cw201x"; + reg = <0x62>; + alert-threshold = <0>; + profile-tbl = <0x15 0x7E 0x64 0x63 0x60 0x5A 0x53 0x50 + 0x4E 0x4B 0x49 0x46 0x48 0x43 0x2F 0x22 + 0x18 0x0F 0x0D 0x12 0x21 0x36 0x48 0x58 + 0x4F 0xA2 0x08 0xF6 0x1D 0x3B 0x46 0x4C + 0x59 0x5C 0x5C 0x60 0x3F 0x1B 0x6C 0x45 + 0x26 0x41 0x20 0x56 0x86 0x95 0x96 0x0E + 0x45 0x6A 0x96 0xC1 0x80 0xB8 0xF0 0xCB + 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x5B 0x1D>; + }; diff --git a/Documentation/devicetree/bindings/power_supply/lc709203f_battery.txt b/Documentation/devicetree/bindings/power_supply/lc709203f_battery.txt new file mode 100644 index 000000000000..0a2d75200a90 --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/lc709203f_battery.txt @@ -0,0 +1,44 @@ +lc709203f battery +~~~~~~~~~~~~~~~~ + +Required properties : + - compatible : Should contain "onsemi,lc709203f". + - onsemi,initial-rsoc : INITIAL_RSOC register value to be written + +Optional properties: + - onsemi,tz-name : Thermal zone name. + - onsemi,thermistor-beta : THERMISTOR_B register value to be written + - onsemi,appli-adjustment: adjustment appli of parameter. + - onsemi,thermistor-adjustment: adjustment thermistor pack. + - onsemi,kernel-threshold-soc: Minimum SoC for kernel read from device. + Bootloader jumps to kernel when SoC is more than this value. + Driver make this SoC as 0% before reporting it to teh framework. + - onsemi,kernel-maximum-soc: Maximum SoC for kernel read from device. + Kernel read maximum SoC from device for given battery. Kernel + translate the SoC to 100% before reporting to framework if it + reads equal/more than this value. + +Note: The device has capabilty to read battery temp through thermistor. +This also calulate SoC based on temperature of battery. If thermistor +is not connected to this device on a given platform then the temp can be +written on the the device register to consider the battery temperature +on SoC calculation. + +If battery thermistor is connected to the device's Tsense pin then following +properties are required: + onsemi,thermistor-beta + +if battery thermistor isnot connected to device and temperature is read from +other source then following properties are required: + onsemi,tz-name + +Example: + + lc709203f@0b { + compatible = "onsemi,lc709203f"; + onsemi,tz-name = "battery-temp"; + onsemi,thermistor-beta = 0x0d34; + onsemi,initial-rsoc = 0xAA55; + onsemi,kernel-threshold-soc = <5>; + onsemi,kernel-maximum-soc = <99>; + }; diff --git a/Documentation/devicetree/bindings/power_supply/max17048_battery.txt b/Documentation/devicetree/bindings/power_supply/max17048_battery.txt new file mode 100644 index 000000000000..32b1d2bedfbe --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/max17048_battery.txt @@ -0,0 +1,76 @@ +max17048_battery +~~~~~~~~~~~~~~~~ + +Required properties : + - compatible : Should contain "maxim,max17048". + - alert-threshold : Alert threshold. in %(percentage). 0~32. + - one-percent-alerts : 1% alert mode control. + 1=enable, 0=disable. + - valert-max : Maximum Voltage threshold for alert. in mV. + This value should be multiple of 20mV. 0~5100mV. + - valert-min : Minimum voltage threshold for alert. in mV. + This value should be multiple of 20mV. 0~5100mV. + - vreset-threshold : Voltage threshold for reset. in mV. + This value should be multiple of 40mV. 0~5080mV. + - vreset-disable : Voltage threshold reset control. + 1=disable, 0=enable + - hib-thhreshold : Threshold to enter hibernate mode. in 0.208%/hr. 0~255. + If the absolute value of CRATE is less than this for longer than 6min, + the IC enters hibernate mode. + - hib-active-threshold : Hibernate active threshold. in 1.25mV. 0~255. + If at any ADC sample is greater than this, the IC exits hibernate mode + and 6min timer is reset. + - bits : 19-bit or 18-bit model. + 19=19-bit model, 18=18-bit model. + This value is depends on custom model. + - rcomp : Starting RCOMP value. 0~255. + This value is depends on custom model. + - rcomp-seg : RCOMPSEG register. + This value is depends on custom model. + - soccheck-a : SOC check low value. in %(percentage). + This value is depends on custom model. + - soccheck-b : SOC check high value. in %(percentage). + This value is depends on custom model. + - ocvtest : OCV test value. + This value is depends on custom model. + - data-tbl : Custom model data. This should be 64 entries(64 bytes). + This value is depends on custom model. + +Contact Maxim for details on how to configure the values involved with custom model. + +Optional properties : + - use-ac : Use AC charging. + If not present, AC charging will not be used. + - use-usb : Use USB charging. + If not present, USB charging will not be used. + +Example: + + max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + use-ac; + use-usb; + alert-threshold = <0>; + one-percent-alerts = <0>; + valert-max = <0>; + valert-min = <0>; + vreset-threshold = <0>; + vreset-disable = <0>; + hib-threshold = <0>; + hib-active-threshold = <0>; + bits = <0>; + rcomp = <0>; + rcomp-seg = <0x0000>; + soccheck-a = <0>; + soccheck-b = <0>; + ocvtest = <0>; + data-tbl = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + }; diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt new file mode 100644 index 000000000000..daa3ee2e198b --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt @@ -0,0 +1,89 @@ +* palmas regulator IP block devicetree bindings + +Required properties: +- compatible : Should be from the list + ti,twl6035-pmic + ti,twl6036-pmic + ti,twl6037-pmic + ti,tps65913-pmic + ti,tps65914-pmic + ti,tps80036-pmic +and also the generic series names + ti,palmas-pmic +- interrupt-parent : The parent interrupt controller which is palmas. +- interrupts : The interrupt number and the type which can be looked up here: + arch/arm/boot/dts/include/dt-bindings/interrupt-controller/irq.h +- interrupts-name: The names of the individual interrupts. + +Optional properties: +- ti,ldo6-vibrator : ldo6 is in vibrator mode +- ti,config_flags: Configuration flags. + 0x1: Force off on suspendi. + 0x2: Trackign enable. + 0x4: Tracking disable on suspend. +- ti,tracking-regulator: Tracking regulator phandle. +- gpio-extcontrol: GPIO for external control. + +Optional nodes: +- regulators : Must contain a sub-node per regulator from the list below. + Each sub-node should contain the constraints and initialization + information for that regulator. See regulator.txt for a + description of standard properties for these sub-nodes. + Additional custom properties are listed below. + + For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP, + smps45, smps457, smps7 depending on variant, smps6, smps[8-9], + smps10_out2, smps10_out1, ldo[1-14], ldoln, ldousb, regen[1-5], + regen7, sysen1, sysen2. + + Optional sub-node properties: + ti,warm-reset - maintain voltage during warm reset(boolean) + ti,roof-floor - This takes as optional argument on platform supporting + the rail from desired external control. If there is no argument then + it will be assume that it is controlled by NSLEEP pin. + The valid value for external pins are: + ENABLE1 then 1, + ENABLE2 then 2 or + NSLEEP then 3. + ti,mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - auto, + 2 - eco, 3 - forced pwm + ti,smps-range - OTP has the wrong range set for the hardware so override + 0 - low range, 1 - high range. + +- ti,system-power-controller: Telling whether or not this pmic is controlling + the system power. + +Example: + +#include <dt-bindings/interrupt-controller/irq.h> + +pmic { + compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; + interrupt-parent = <&palmas>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupts-name = "short-irq"; + + ti,ldo6-vibrator; + + ti,system-power-controller; + + regulators { + smps12_reg : smps12 { + regulator-name = "smps12"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + ti,warm-reset; + ti,roof-floor = <1>; /* ENABLE1 control */ + ti,mode-sleep = <0>; + ti,smps-range = <1>; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt new file mode 100644 index 000000000000..ef560e1e2261 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt @@ -0,0 +1,47 @@ +PWM controlled regulators + +Required properties: +- compatible : Must be "regulator-pwm". +- pwms : Must be pwm-list specified by pwm binding pwm.txt +- regulator-min-microvolt : Must be smallest voltage at pwm duty cycle 0% +- regulator-max-microvolt : Must be largest voltage at pwm duty cycle 100% + (must be above min; if equal, then use a fixed + regulator) + +Optional properties: +- regulator-n-voltages : number of voltages, if specified implies evenly + distributed duty cycle levels; must be at least 2 +- voltage-time-sel : time in microseconds of voltage transition between + voltage levels (specified if regulator settling time + is independent of voltage change; for regulators with + fixed slew-rate use regulator-ramp-delay property) + +Control GPIOs specified according to gpio binding in gpio.txt +- enable-gpio : GPIO to use to enable/disable the regulator +- idle-gpio : GPIO to use to enter/exit regulator idle mode +- standby-gpio : GPIO to use to enter/exit regulator standby mode + +Any property defined as part of the pwm user binding in pwm.txt. +Any property defined as part of the core regulator binding in regulator.txt. + +Example: + + pwm: pwm-controller { + #pwm-cells = <2>; + }; + + abc_pwm_reg: pwm-regulator { + compatible = "regulator-pwm"; + pwms = <&pwm 0 3000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <2500000>; + + regulator-name = "vdd-abc-pwm-reg"; + regulator-enable-ramp-delay = <700>; + regulator-boot-on; + + regulator-n-voltages = <64>; + voltage-time-sel = <50>; + enable-gpio = <&gpio0 21 0x0>; + standby-gpio = <&gpio0 22 0x0>; + }; diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index ecfc6ccd67ef..d8d57a136c8a 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -11,6 +11,12 @@ Optional properties: - regulator-boot-on: bootloader/firmware enabled regulator - <name>-supply: phandle to the parent supply/regulator node - regulator-ramp-delay: ramp delay for regulator(in uV/uS) +- regulator-init-microvolt: Initial microvolt need to be set during registration +- regulator-enable-ramp-delay: The time taken, in microseconds, for the supply + rail to reach the target voltage, plus/minus whatever tolerance the board + design requires. This property describes the total system ramp time + required due to the combination of internal ramping of the regulator itself, + and board design issues such as trace capacitance and load on the supply. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple @@ -19,6 +25,27 @@ Deprecated properties: this child node is intended to configure. If this property is missing, the node's name will be used instead. +Consumer name support from DT: +To support the consumer list of the rails from DT to map the power tree +so that driver who uses the regualtor can still be non-dt, adding following +properties. +The consumer list will be provided under subnode of each regualtor called +"consumer". The consumer list has the supply name and device name. This can +be set with properties: +regulator-consumer-supply: Consumer supply name. +regulator-consumer-device: Consumer device name. +The properties will be passed as + consumers { + c1 { + regulator-consumer-supply = "vana"; + regulator-consumer-device = "2-0010"; + }; + + c2 { + regulator-consumer-supply = "vana"; + regulator-consumer-device = "2-0036"; + }; + Example: xyzreg: regulator@0 { @@ -60,3 +87,35 @@ regulators (twl_reg1 and twl_reg2), vmmc-supply = <&twl_reg1>; vmmcaux-supply = <&twl_reg2>; }; + + +Example: Consumer list from DT + ldo3 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + ams,enable-tracking; + consumers { + c1 { + regulator-consumer-supply = "vdd_rtc"; + }; + }; + }; + + ldo4 { + regulator-name = "avdd_cam"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + consumers { + c1 { + regulator-consumer-supply = "vana"; + regulator-consumer-device = "2-0010"; + }; + c2 { + regulator-consumer-supply = "vana"; + regulator-consumer-device = "2-0036"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt index 392a4493eebd..c5ae7ae269a4 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt @@ -1,7 +1,16 @@ NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. Required properties: -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". +- compatible : Must be one of following: + "nvidia,tegra114-hsuart", + "nvidia,tegra30-hsuart", + "nvidia,tegra20-hsuart". + "nvidia,tegra114-hs-serial" + "nvidia,tegra20-hs-serial" + "nvidia,tegra30-hs-serial" + There is no differece in nvidia,tegra114-hsuart and + nvidia,tegra114-hs-serial. Two separate names are provided for + ease of usage only. - reg: Should contain UART controller registers location and length. - interrupts: Should contain UART controller interrupts. - nvidia,dma-request-selector : The Tegra DMA controller's phandle and diff --git a/Documentation/devicetree/bindings/sound/ak4618.txt b/Documentation/devicetree/bindings/sound/ak4618.txt new file mode 100644 index 000000000000..7ab86d3eb9f6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak4618.txt @@ -0,0 +1,34 @@ +AK4618 audio CODEC + +This device supports only I2C. + +Required properties: + + - compatible : "akm,ak4618" + + - reg : the I2C address of the device for I2C. + +Pins on the device (for linking into audio routes): + + * DACOUT1 + * DACOUT2 + * DACOUT3 + * DACOUT4 + * DACOUT5 + * DACOUT6 + * IN1 + * IN2 + * IN3 + * IN4 + * IN5 + * IN6 + * MICBIAS + + - note : DACOUTs are stereo output, INs are mono input. + +Example: + +codec: ak4618@10 { + compatible = "akm,ak4618"; + reg = <0x10>; +}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra124-adx.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra124-adx.txt new file mode 100644 index 000000000000..a1aaed30731f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra124-adx.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra124 ADX controller + +Required properties: +- compatible : "nvidia,tegra124-adx" +- reg : Should contain ADX registers location and length + +Example: + +amx@70303800 { + compatible = "nvidia,tegra124-adx"; + reg = <0x70303800 0x100>; +}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra124-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra124-ahub.txt new file mode 100644 index 000000000000..ce4f6feddea6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra124-ahub.txt @@ -0,0 +1,38 @@ +NVIDIA Tegra124 AHUB (Audio Hub) + +Required properties: +- compatible : "nvidia,tegra124-ahub" +- reg : Should contain the register physical address and length for each of + the AHUB's APBIF registers, the AHUB's own registers and the AHUB's APBIF2 + registers. +- interrupts : Should contain AHUB interrupt +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for each APBIF channels. Should have 10 of apbdma phandles. +- ranges : The bus address mapping for the configlink register bus. + Can be empty since the mapping is 1:1. +- #address-cells : For the configlink bus. Should be <1>; +- #size-cells : For the configlink bus. Should be <1>. + +I2S, DAM and SPDIF in AHUB client modules need to specify the IDs of their +CIFs (Client InterFaces). +For RX CIFs, the numbers indicate the register number within AHUB routing +register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). +For TX CIFs, the numbers indicate the bit position within the AHUB routing +registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1) + +Example: + +ahub@70300000 { + compatible = "nvidia,tegra124-ahub"; + reg = <0x70300000 0x200>, + <0x70300800 0x800>, + <0x70300200 0x200>; + interrupts = < 0 103 0x04 >; + nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, <&apbdma 29>; + + ranges; + #address-cells = <1>; + #size-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra124-amx.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra124-amx.txt new file mode 100644 index 000000000000..5549577e693c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra124-amx.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra124 AMX controller + +Required properties: +- compatible : "nvidia,tegra124-amx" +- reg : Should contain AMX registers location and length + +Example: + +amx@70303000 { + compatible = "nvidia,tegra124-amx"; + reg = <0x70303000 0x100>; +}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra124-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra124-i2s.txt new file mode 100644 index 000000000000..272ca4bb1334 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra124-i2s.txt @@ -0,0 +1,15 @@ +NVIDIA Tegra124 I2S controller + +Required properties: +- compatible : "nvidia,tegra124-i2s" +- reg : Should contain I2S registers location and length +- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) + first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. + +Example: + +i2s@70301000 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301000 0x100>; + nvidia,ahub-cif-ids = <4 4>; +}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt deleted file mode 100644 index c1454979c1ef..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt +++ /dev/null @@ -1,22 +0,0 @@ -NVIDIA Tegra 20 AC97 controller - -Required properties: -- compatible : "nvidia,tegra20-ac97" -- reg : Should contain AC97 controller registers location and length -- interrupts : Should contain AC97 interrupt -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and - request selector for the AC97 controller -- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number - of the GPIO used to reset the external AC97 codec -- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number - of the GPIO corresponding with the AC97 DAP _FS line -Example: - -ac97@70002000 { - compatible = "nvidia,tegra20-ac97"; - reg = <0x70002000 0x200>; - interrupts = <0 81 0x04>; - nvidia,dma-request-selector = <&apbdma 12>; - nvidia,codec-reset-gpio = <&gpio 170 0>; - nvidia,codec-sync-gpio = <&gpio 120 0>; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt index 0e5c12c66523..1ac7b1642186 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt @@ -1,22 +1,12 @@ NVIDIA Tegra30 AHUB (Audio Hub) Required properties: -- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc. +- compatible : "nvidia,tegra30-ahub" - reg : Should contain the register physical address and length for each of - the AHUB's register blocks. - - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. - - Tegra114 requires an additional entry, for the APBIF2 register block. + the AHUB's APBIF registers and the AHUB's own registers. - interrupts : Should contain AHUB interrupt -- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each - entry contains the Tegra DMA controller's phandle and request selector. - If a single entry is present, the request selectors for the channels are - assumed to be contiguous, and increment from this value. - If multiple values are given, one value must be given per channel. -- clocks : Must contain an entry for each required entry in clock-names. -- clock-names : Must include the following entries: - - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0, - dam1, dam2, spdif_in. - - Tegra114: Additionally requires amx, adx. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for the first APBIF channel. - ranges : The bus address mapping for the configlink register bus. Can be empty since the mapping is 1:1. - #address-cells : For the configlink bus. Should be <1>; @@ -35,13 +25,7 @@ ahub@70080000 { reg = <0x70080000 0x200 0x70080200 0x100>; interrupts = < 0 103 0x04 >; nvidia,dma-request-selector = <&apbdma 1>; - clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, - <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, - <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, - <&tegra_car 110>, <&tegra_car 162>; - clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif_in"; + ranges; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt b/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt new file mode 100644 index 000000000000..2d961d8e3d69 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt @@ -0,0 +1,47 @@ +NVIDIA Tegra114 SPI controller. + +Required properties: +- compatible : should be "nvidia,tegra114-spi". +- reg: Should contain SPI registers location and length. +- interrupts: Should contain SPI interrupts. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for this SPI controller. + +Recommended properties: +- spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt +Optional properties: +- nvidia,clock-always-on: Enable clock of spi always. + +spi-client device controller properties: +- nvidia,enable-hw-based-cs: (Boolean) Use the HW based CS if enabled. +- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device + with this tap value. +- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device + with this tap value. +- nvidia,cs-setup-clk-count: CS setup timing parameter. +- nvidia,cs-hold-clk-count: CS hold timing parameter. + +Example: +spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + spi-max-frequency = <25000000>; + nvidia,clock-always-on; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + <spi-client>@<bus_num> { + ... + ... + nvidia,enable-hw-based-cs; + nvidia,cs-setup-clk-count = <10>; + nvidia,cs-hold-clk-count = <10>; + nvidia,rx-clk-tap-delay = <0>; + nvidia,tx-clk-tap-delay = <16>; + ... + }; +}; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt deleted file mode 100644 index 91ff771c7e77..000000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt +++ /dev/null @@ -1,26 +0,0 @@ -NVIDIA Tegra114 SPI controller. - -Required properties: -- compatible : should be "nvidia,tegra114-spi". -- reg: Should contain SPI registers location and length. -- interrupts: Should contain SPI interrupts. -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and - request selector for this SPI controller. -- This is also require clock named "spi" as per binding document - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -Example: - -spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; diff --git a/Documentation/devicetree/bindings/staging/iio/light/iqs253-ps.txt b/Documentation/devicetree/bindings/staging/iio/light/iqs253-ps.txt new file mode 100644 index 000000000000..7c536efeb995 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/iio/light/iqs253-ps.txt @@ -0,0 +1,24 @@ +* IQS253 proximity sensor + +Required properties: +- compatible: must be "azoteq,iqs253" +- reg: i2c address of the device. It is one of 0x44-0x47. +- vendor: vendor of the hardware part. +- proximity,max-range: maximum range of this sensor's value in SI units. +- proximity,integration-time: minimum sampling period in nano seconds. +- proximity,power-consumed: rough estimate of this sensor's power consumption in mA. +- rdy-gpio: gpio to be used for i2c handshake with the sensor. +- wake-gpio: gpio to be used for wakeup on stylus insert/removal event. + +Example: + + iqs253@44 { + compatible = "azoteq,iqs253"; + reg = <0x44>; + vendor = "Azoteq"; + proximity,max-range = "2"; /* 2 cm */; + proximity,integration-time = "16000000"; /* 16 msec */ + proximity,power-consumed = "1.67"; /* mA */ + rdy-gpio = <&gpio TEGRA_GPIO(PK, 5) 1>; + wake-gpio = <&gpio TEGRA_GPIO(PW, 3) 1>; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 6931c4348d24..85841117e230 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -13,6 +13,7 @@ arm ARM Ltd. atmel Atmel Corporation bosch Bosch Sensortec GmbH brcm Broadcom Corporation +capella Capella Microsystems, Inc. cavium Cavium, Inc. chrp Common Hardware Reference Platform cirrus Cirrus Logic, Inc. diff --git a/Documentation/devicetree/bindings/video/nvidia,ad5816.txt b/Documentation/devicetree/bindings/video/nvidia,ad5816.txt new file mode 100644 index 000000000000..a11d5f4d318e --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,ad5816.txt @@ -0,0 +1,36 @@ +NVIDIA Camera sensor ad5816 driver interface. + +Required properties: +- compatible : The driver is compatible with + "nvidia,ad5816". + +- reg: Should contain I2C slave address of the driver. + +All other properties are based on nvc (nvidia camera interface) standard +structures definitions, which are generic across the devices. Few of them are +explained below: + +- nvidia,num: Indicates the instance of particular camera device, in this case +it is for camera focuser device. Currently for rear camera focuser "0" is used. + +- nvidia,sync: Used for stereo synchronization. "0" for non-stereo usecase. + +- nvidia,dev_name: Camera device driver name. + +For more details refer nvc headers at : $TOP/kernel/include/media/ +nvc.h +nvc_focus.h +nvc_image.h +nvc_torch.h + +Example: + + ad5816@0E { + compatible = "nvidia,ad5816"; + reg = <0x0E>; + nvidia,cfg = <0>; + nvidia,num = <0>; + nvidia,sync = <0>; + nvidia,dev_name = "focuser"; + status = "okay"; + };
\ No newline at end of file diff --git a/Documentation/devicetree/bindings/video/nvidia,ad5823.txt b/Documentation/devicetree/bindings/video/nvidia,ad5823.txt new file mode 100644 index 000000000000..bc7399c39802 --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,ad5823.txt @@ -0,0 +1,18 @@ +NVIDIA Camera focuser ad5823 driver interface. + +Required properties: +- compatible : The driver is compatible with + "nvidia,ad5823". + +- reg : Should contain I2C slave address of the driver. + +- af-pwdn-gpios : ad5823 power down GPIO + +Example: + + ad5823@0c { + compatible = "nvidia,ad5823"; + reg = <0x0c>; + af-pwdn-gpios = <&gpio 223 0>; /* gpo PBB7 */ + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,imx091.txt b/Documentation/devicetree/bindings/video/nvidia,imx091.txt new file mode 100644 index 000000000000..d7bc9ae5ebff --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,imx091.txt @@ -0,0 +1,91 @@ +NVIDIA Camera sensor imx091 driver interface. + +Properties: +- compatible : The driver is compatible with + "nvidia,imx091". + +- reg: Should contain I2C slave address of the driver. + +- nvidia,vcm_vdd : For few platforms this driver needs extra power regulator +"vcm_vdd" to be enabled. This bool property indicates the same. It must be +programmed only when imx091 driver needs it for a particular platform. + +- nvidia,i2c_vdd : For few platforms this driver needs extra power regulator +"i2c_vdd" to be enabled. This bool property indicates the same. It must be +programmed only when imx091 driver needs it for a particular platform. + +- nvidia,num: Indicates the instance of particular camera device, in this case +it is for camera focuser device. Currently for rear camera focuser "0" is used. + +- nvidia,sync: Used for stereo synchronization. "0" for non-stereo usecase. + +- nvidia,dev_name: Camera device driver name. + +- imx091 caps: These properties are based on nvc (nvidia camera interface) +standard structure definition: nvc_imager_cap , which is generic across +the devices. For details refer nvc headers at : +$TOP/kernel/include/media/nvc_image.h + +- edpc configs: standard edp paramters. + - states: EDP state array holding the IMAX for each state. This must be + sorted in descending order. + - num_states: length of the above array. + - e0_index: index of the E0 state in the above array. + - priority: client priority - should be between EDP_MIN_PRIO & EDP_MAX_PRIO. + +- flash caps: Please see below example for properties related to imx091 +flash capabilities. + +Example: + + imx091@10 { + compatible = "nvidia,imx091"; + reg = <0x10>; + nvidia,ext_reg; /* Extra power-regulators needed */ + + nvidia,num = <0>; + nvidia,sync = <0>; + nvidia,dev_name = "camera"; + + /* edpc config */ + nvidia,imx091_estates = <876 656 220 0>; + nvidia,num_states = <4>; + nvidia,e0_index = <0>; + nvidia,priority = <1>; + + /* imx091 gpios */ + reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ + power-gpios = <&gpio 221 0>; /* gpio PBB6 */ + gp1-gpios = <&gpio 225 0>; /* gpio PCC1 */ + + /* imx091 caps */ + nvidia,identifier = "IMX091"; + nvidia,sensor_nvc_interface = <3>; + nvidia,pixel_types = <0x100>; + nvidia,orientation = <0>; + nvidia,direction = <0>; + nvidia,initial_clock_rate_khz = <6000>; + nvidia,h_sync_edge = <0>; + nvidia,v_sync_edge = <0>; + nvidia,mclk_on_vgp0 = <0>; + nvidia,csi_port = <0>; + nvidia,data_lanes = <4>; + nvidia,virtual_channel_id = <0>; + nvidia,discontinuous_clk_mode = <1>; + nvidia,cil_threshold_settle = <0x0>; + nvidia,min_blank_time_width = <16>; + nvidia,min_blank_time_height = <16>; + nvidia,preferred_mode_index = <0>; + nvidia,external_clock_khz_0 = <24000>; + nvidia,clock_multiplier_0 = <850000>; + nvidia,external_clock_khz_1 = <0>; + nvidia,clock_multiplier_1 = <0>; + + /* flash caps */ + nvidia,sdo_trigger_enabled; + nvidia,adjustable_flash_timing; + + status = "okay"; + + }; + diff --git a/Documentation/devicetree/bindings/video/nvidia,imx132.txt b/Documentation/devicetree/bindings/video/nvidia,imx132.txt new file mode 100644 index 000000000000..05d6f385e57a --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,imx132.txt @@ -0,0 +1,24 @@ +NVIDIA Camera sensor imx132 driver interface. + +Required properties: +- compatible : The driver is compatible with + "nvidia,imx132". + +- cam2_gpios : Camera GPIO. + +- reg: Should contain I2C slave address of the driver. + +- nvidia,ext_reg : For few platforms this driver needs extra power regulators +to be enabled. This bool property indicates the same. It must be programmed +only when imx132 driver needs extra power rails for particular platform. + +Example: + + imx132@36 { + compatible = "nvidia,imx132"; + cam2_gpios = <&gpio 222 0>; /* gpio PBB6 */ + reg = <0x36>; + nvidia,ext_reg; /* Extra power-regulators needed */ + status = "okay"; + }; + diff --git a/Documentation/devicetree/bindings/video/nvidia,nvavp.txt b/Documentation/devicetree/bindings/video/nvidia,nvavp.txt new file mode 100644 index 000000000000..3e848723cd8a --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,nvavp.txt @@ -0,0 +1,15 @@ +Device-Tree bindings for tegra nvavp driver + +Required properties: +- compatible: value should be "nvidia,tegra114-nvavp"/"nvidia,tegra124-nvavp"/"nvidia,tegra30-nvavp" +- reg: physical base address of mailbox, nvavp vector table +- interrupts: interrupt number to the cpu. + +Note: nvavp should is child of the host1x +Example: + nvavp { + compatible = "nvidia,tegra114-nvavp"; + interrupts = <0 4 0x04>; /* mailbox AVP IRQ */ + reg = <0x60001000 0x0000e200>; + }; + diff --git a/Documentation/devicetree/bindings/video/nvidia,ov5693.txt b/Documentation/devicetree/bindings/video/nvidia,ov5693.txt new file mode 100644 index 000000000000..0aeb4b238f20 --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,ov5693.txt @@ -0,0 +1,32 @@ +NVIDIA Camera sensor ov5693 driver interface. + +Properties: +- compatible : The driver is compatible with + "nvidia,ov5693". + +- reg : Should contain I2C slave address of the driver. + +- nvidia,num : Indicates the instance of particular camera device, in this +case it is for camera sensor device. Currently for rear camera sensor "0" +is used. + +- nvidia,dev-name : Camera device driver name. + +- nvidia,use-vcm-vdd : For few platforms this driver needs extra power +regulator "ext_vcm_vdd" to be enabled. This bool property indicates the +same. It must be programmed only when ov5693 driver needs it for a +particular platform. + +- reset-gpios : ov5693 reset GPIO + +Example: + + ov5693@10 { + compatible = "nvidia,ov5693"; + reg = <0x10>; + nvidia,num = <0>; + nvidia,dev-name = "camera"; + nvidia,use-vcm-vdd; + reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,ov9772.txt b/Documentation/devicetree/bindings/video/nvidia,ov9772.txt new file mode 100644 index 000000000000..066fb4c10fdd --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,ov9772.txt @@ -0,0 +1,33 @@ +NVIDIA Camera sensor ov9772 driver interface. + +Required properties: +- compatible : The driver is compatible with + "nvidia,ov9772". + +- reg: Should contain I2C slave address of the driver. + +- nvidia,dev_name: Indicates device name. + +- nvidia,num: Indicates device number. + +- nvidia,vcm_vdd : For few platforms this driver needs extra power +regulator (vcm_vdd) to be enabled. This bool property indicates the +same. It must be programmed only when ov9772 driver needs extra power +rail for a platform in context. + +Example: + + ov9772@10 { + compatible = "nvidia,ov9772"; + reg = <0x10>; + nvidia,num = <1>; + + nvidia,vcm_vdd; /* extra regulator needed */ + + /* ov9772 gpios */ + reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ + power-gpios = <&gpio 222 0>; /* gpio PBB6 */ + + nvidia,dev_name = "camera"; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt new file mode 100644 index 000000000000..6a055fefeadb --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt @@ -0,0 +1,370 @@ +NVIDIA Tegra114 Display Controller +================================== + +1) The dc node: + dc node must be contained in host1x parent node. This node represents + NVIDIA Tegra114 Display controller. + + Required properties: + - name: dc + - compatible: Should contain "nvidia,tegra114-dc". + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - nvidia,memory-clients: This is the "swgroup" ID in the Tegra TRM term. + - nvidia,dc-flags: This is to enable display controller in probe time. + "dc_flag_en" or remove this property (do not set this property). + - nvidia,emc-clk-rate: Initially required embedded memory controller clk rate. + - nvidia,cmu-enable: Toggle switch for color management unit. + - nvidia,low-v-win: If low_v_win is set, we can lower vdd_core when that windows + is the only one active. + - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage, + HDMI_AVDD. + - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply. + - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source. + + - Child nodes represent node of modes, output settings, framebuffer data, + smart dimmer settings, color management unit settings, dsi output device settings. + +1.A) NVIDIA Display Controller Modes + This must be contained in dc parent node. This contains supported modes. + + Required properties: + - name: Should be "display-timings" + + - Child nodes represent modes. Several modes can be prepared. + +1.A.i) NVIDIA Display Controller Mode timing + This must be contained in display-timings parent node. This contains mode settings, including + display timings. For hdmi out-type case, display-timings properties are only valid in case of + hdmi fb console mode. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - hactive, vactive: display resolution. + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels. + - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines. + - clock-frequency: display clock in Hz. + - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC + with respect to H reference point. + - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC + with respect to V reference point. + +1.B) NVIDIA Display Controller Default Output Settings + This must be contained in dc parent node. This is default output settings. + + Required properties: + - name: Should be "dc-default-out". + - nvidia,out-type: Output type. Should be "dsi" or "hdmi". + - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. + - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. + - nvidia,out-flags: Should be "continuous" or "oneshot" or "hotplug_high" or "hotplug_low" + or "continuous_initialized" or "oneshot_initialized" + - nvidia,out-parent-clk: Parent clk for display controller. + - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. + - nvidia,out-align: Display data alignment. Should be "msb" or "lsb". + - nvidia,out-order: Display data order. Should be "rtob" or "btor". + - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for + BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, + BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, + and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. + For hdmi out-type case, depth selection is only valid for hdmi fb console mode, + otherwise, BASE_COLOR_SIZE888 is chosen as a default. + +1.C) NVIDIA Display Controller framebuffer data + This must be contained in dc parent node. This is required framebuffer data. + +Required properties: + - name: Should be "framebuffer-data". + - nvidia,fb-bpp: Bits per pixel of fb. + - nvidia,fb-flags: Window is updated in display controller device probe. Should be "flip_on_probe", + or remove this property (do not set this property). + - nvidia,fb-xres: Visible resolution for width. + - nvidia,fb-yres: Visible resolution for height. + +1.D) NVIDIA Display Controller Smart Dimmer Settings + This must be contained in dc parent node. This is smart dimmer settings. + + Required properties: + - name: Should be "smartdimmer". + - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control + signal directly. + - nvidia,hw-update-delay: It determines the delay of the update of the hardware + enhancement value (K) that is applied to the pixels. + - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. + 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment + of -1, indicates automatic based on aggressiveness. + - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. + - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. + - nvidia,phase-in-adjustments: Software backlight phase-in + - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) + rather than computed from nvidia,aggressiveness. + - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of + aggressiveness. + - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) + to a rectangular subset of display. + - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels + above nvidia,soft-clipping-threshold level to avoid saturation. + - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. + - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to + nvidia,smooth-k-incr. + - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed + at most by smooth-k-incr per frame. + - nvidia,coeff: Luminance calculation coefficients used to convert the red green and + blue color components into a luminance value. The conversion is performed according to + the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. + Need to write blue, green, red coefficient for luminance calculation in sequence. + - nvidia,fc: Flicker control that prevents rapid and frequent changes + in the enhancement value. Need to write time_limit, threshold in sequence. + - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to + write time_constant for the response curve and step that determines the instantaneous + portion of the target value of enhancement that is applied: <time_constant, step>. + - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve + defines how the backlight output changes with respect to the control input. The 17th point + is defined to be the maximum value. + - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k + for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). + There are nine entries in total. + - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. + - nvidia,bl-device-name: Backlight device name. + +1.E) NVIDIA Display Controller Color Management Unit Settings + This must be contained in dc parent node. This is color management unit settings. + + Required properties: + - name: Should be "cmu". + - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. + - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + +Example + host1x { + /* tegradc.0 */ + dc@54200000 { + compatible = "nvidia,tegra114-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + status = "okay"; + nvidia,dc-flags = "dc_flag_en"; + nvidia,emc-clk-rate = <204000000>; + nvidia,cmu-enable = <1>; + avdd_hdmi-supply = <&palmas_ldoln>; + avdd_hdmi_pll-supply = <&palmas_ldo1>; + vdd_hdmi_5v0-supply = <&vdd_hdmi>; + dc-default-out { + nvidia,out-type = "dsi"; + nvidia,out-width = <217>; + nvidia,out-height = <135>; + nvidia,out-flags = "continuous"; + nvidia,out-parent-clk = "pll_d_out0"; + }; + display-timings { + 1920p32 { + clock-frequency = <154700000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <120>; + hback-porch = <32>; + hsync-len = <16>; + vfront-porch = <17>; + vback-porch = <16>; + vsync-len = <2>; + nvidia,h-ref-to-sync = <4>; + nvidia,v-ref-to-sync = <1>; + }; + }; + framebuffer-data { + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = "flip_on_probe"; + nvidia,fb-xres = <1920>; + nvidia,fb-yres = <1200>; + }; + smartdimmer { + status = "okay"; + nvidia,use-auto-pwm = <0>; + nvidia,hw-update-delay = <0>; + nvidia,bin-width = <0xffffffff>; + nvidia,aggressiveness = <5>; + nvidia,use-vid-luma = <0>; + nvidia,phase-in-settings = <0>; + nvidia,phase-in-adjustments = <0>; + nvidia,k-limit-enable = <1>; + nvidia,k-limit = <200>; + nvidia,sd-window-enable = <0>; + nvidia,soft-clipping-enable= <1>; + nvidia,soft-clipping-threshold = <128>; + nvidia,smooth-k-enable = <1>; + nvidia,smooth-k-incr = <4>; + nvidia,coeff = <5 9 2>; + nvidia,fc = <0 0>; + nvidia,blp = <1024 255>; + nvidia,bltf = <57 65 73 82 + 92 103 114 125 + 138 150 164 178 + 193 208 224 241>; + nvidia,lut = <255 255 255 + 199 199 199 + 153 153 153 + 116 116 116 + 85 85 85 + 59 59 59 + 36 36 36 + 17 17 17 + 0 0 0>; + nvidia,use-vpulse2 = <1>; + nvidia,bl-device-name = "pwm-backlight"; + }; + cmu { + status = "okay"; + nvidia,cmu-csc = < 0x138 0x3Ba 0x00D + 0x3F5 0x120 0x3E6 + 0x3FE 0x3F8 0x0E9 >; + nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6 + 7 8 9 10 11 11 12 13 + 13 14 15 15 16 17 17 18 + 18 19 19 20 20 21 21 22 + 22 23 23 23 24 24 24 25 + 25 25 26 26 26 27 27 27 + 28 28 28 28 29 29 29 29 + 30 30 30 30 31 31 31 31 + 32 32 32 32 33 33 33 33 + 34 34 34 35 35 35 35 36 + 36 36 37 37 37 37 38 38 + 38 39 39 39 39 40 40 40 + 41 41 41 41 42 42 42 43 + 43 43 43 44 44 44 45 45 + 45 45 46 46 46 46 47 47 + 47 47 48 48 48 48 49 49 + 49 49 50 50 50 50 50 51 + 51 51 51 52 52 52 52 52 + 53 53 53 53 53 53 54 54 + 54 54 54 55 55 55 55 55 + 55 56 56 56 56 56 56 57 + 57 57 57 57 57 57 58 58 + 58 58 58 58 59 59 59 59 + 59 59 59 60 60 60 60 60 + 60 60 61 61 61 61 61 61 + 61 62 62 62 62 62 62 62 + 63 63 63 63 63 63 63 64 + 64 64 64 64 64 64 65 65 + 65 65 65 65 66 66 66 66 + 66 66 66 67 67 67 67 67 + 67 68 68 68 68 68 68 69 + 69 69 69 69 69 70 70 70 + 70 70 70 71 71 71 71 71 + 71 72 72 72 72 72 72 73 + 73 73 73 73 73 74 74 74 + 74 74 74 74 75 75 75 75 + 75 75 76 76 76 76 76 76 + 77 77 77 77 77 77 77 78 + 78 78 78 78 78 79 79 79 + 79 79 79 79 80 80 80 80 + 80 80 80 80 81 81 81 81 + 81 81 81 82 82 82 82 82 + 82 82 82 83 83 83 83 83 + 83 83 83 83 84 84 84 84 + 84 84 84 84 85 85 85 85 + 85 85 85 85 85 85 86 86 + 86 86 86 86 86 86 86 86 + 87 87 87 87 87 87 87 87 + 87 87 88 88 88 88 88 88 + 88 88 88 88 88 88 89 89 + 89 89 89 89 89 89 89 89 + 89 89 90 90 90 90 90 90 + 90 90 90 90 90 90 91 91 + 91 91 91 91 91 91 91 91 + 91 91 91 92 92 92 92 92 + 92 92 92 92 92 92 92 92 + 93 93 93 93 93 93 93 93 + 93 93 93 93 93 93 94 94 + 94 94 94 94 94 94 94 94 + 94 94 94 94 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 96 96 96 96 96 96 96 + 96 96 96 96 96 96 97 97 + 97 97 97 97 97 97 97 97 + 98 99 99 100 101 101 102 103 + 103 104 105 105 106 107 107 108 + 109 110 110 111 112 112 113 114 + 114 115 115 116 117 117 118 119 + 119 120 120 121 121 122 123 123 + 124 124 125 125 126 126 127 128 + 128 129 129 130 130 131 131 132 + 132 133 133 134 134 135 135 136 + 136 137 138 138 139 139 140 140 + 141 141 142 142 143 143 144 144 + 144 145 145 146 146 147 147 148 + 148 149 149 150 150 151 151 152 + 152 153 153 153 154 154 155 155 + 156 156 157 157 157 158 158 159 + 159 160 160 160 161 161 162 162 + 162 163 163 164 164 164 165 165 + 165 166 166 167 167 167 168 168 + 168 169 169 169 170 170 171 171 + 171 172 172 172 173 173 173 174 + 174 174 175 175 175 176 176 176 + 177 177 177 178 178 178 179 179 + 179 180 180 180 181 181 181 182 + 182 182 183 183 183 184 184 184 + 185 185 185 185 186 186 186 187 + 187 187 188 188 188 189 189 189 + 190 190 190 191 191 191 191 192 + 192 192 193 193 193 194 194 194 + 195 195 195 195 196 196 196 197 + 197 197 198 198 198 199 199 199 + 199 200 200 200 201 201 201 202 + 202 202 203 203 203 203 204 204 + 204 205 205 205 206 206 206 207 + 207 207 208 208 208 208 209 209 + 209 210 210 210 211 211 211 212 + 212 212 213 213 213 214 214 214 + 215 215 215 215 216 216 216 217 + 217 217 218 218 218 219 219 219 + 220 220 220 220 221 221 221 222 + 222 222 222 223 223 223 224 224 + 224 224 225 225 225 226 226 226 + 226 227 227 227 227 228 228 228 + 229 229 229 229 230 230 230 230 + 230 231 231 231 231 232 232 232 + 232 233 233 233 233 234 234 234 + 234 234 235 235 235 235 236 236 + 236 236 236 237 237 237 237 238 + 238 238 238 238 239 239 239 239 + 239 240 240 240 240 240 241 241 + 241 241 241 242 242 242 242 243 + 243 243 243 243 244 244 244 244 + 244 245 245 245 245 245 246 246 + 246 246 246 247 247 247 247 248 + 248 248 248 248 249 249 249 249 + 250 250 250 250 251 251 251 251 + 251 252 252 252 253 253 253 253 + 254 254 254 254 255 255 255 255 >; + }; + }; + + /* tegradc.1 */ + dc@54240000 { + compatible = "nvidia,tegra114-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + status = "okay"; + nvidia,dc-flags = "dc_flag_en"; + nvidia,emc-clk-rate = <300000000>; + nvidia,cmu-enable = <1>; + dc-default-out { + nvidia,out-type = "hdmi"; + nvidia,out-flags = "hotplug_high"; + nvidia,out-parent-clk = "pll_d2_out0"; + nvidia,out-max-pixclk = <297000>; + nvidia,out-align = "msb"; + nvidia,out-order = "rtob"; /*red to blue*/ + }; + framebuffer-data { + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = "flip_on_probe"; + nvidia,fb-xres = <1280>; + nvidia,fb-yres = <720>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt new file mode 100644 index 000000000000..fc16f67c0fd5 --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt @@ -0,0 +1,118 @@ +NVIDIA TEGRA114 Display Serial Interface +======================================== + +1) The dsi node: + dsi node must be contained in host1x parent node. This node represents NVIDIA Tegra114 Display + Serial Interface. + + Required properties + - name: dsi + - compatible: Should contain "nvidia,tegra114-dsi". + - reg: Physical base address and length of the controller's registers. + - nvidia,dsi-controller-vs: DSI version. Write 0, 1 for DSI_VS_0 and DSI_VS_1, respectively. For TEGRA114, + it should be 1. + + - Child node represents dsi panel node. + +1.A) dsi panel node: + dsi panel node must be contained in dsi parent node. This node represents dsi panel node. + + Required properties + - name: Can be arbitrary. + - compatible: Can be arbitrary. One panel has its own unique compatible. + - nvidia,dsi-panel-rst-gpio: panel reset gpio. + - nvidia,dsi-panel-bl-en-gpio: backlight enabling gpio. + - nvidia,dsi-panel-bl-pwm-gpio: gpio for backlight pwm signal. + - nvidia,dsi-te-gpio: gpio for panel TE(Tearing Effect) signal. + - nvidia,dsi-n-data-lanes: Number of DSI lanes in use. Should be one of 2, 3, 4, and 8 + - nvidia,dsi-video-burst-mode: Video mode. Write 0, 1, 2, 3, 4, 5 and 6 for TEGRA_DSI_VIDEO_NONE_BURST_MODE, + TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END, TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED, + TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED, TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED, + TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED and TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED, + respectively. + - nvidia,dsi-pixel-format: DSI pixel data format. Write 0, 1, 2, 3 for TEGRA_DSI_PIXEL_FORMAT_16BIT_P, + TEGRA_DSI_PIXEL_FORMAT_18BIT_P, TEGRA_DSI_PIXEL_FORMAT_18BIT_NP and TEGRA_DSI_PIXEL_FORMAT_24BIT_P, + respectively. + - nvidia,dsi-refresh-rate: Refresh rate. + - nvidia,dsi-virtual-channel: DSI virtual channel number. Write 0, 1, 2 and 3 for TEGRA_DSI_VIRTUAL_CHANNEL_0, + TEGRA_DSI_VIRTUAL_CHANNEL_1, TEGRA_DSI_VIRTUAL_CHANNEL_2 and TEGRA_DSI_VIRTUAL_CHANNEL_3, respectively. + - nvidia,dsi-instance: Should be 0 or 1: DSI controller or DSIB controller. + - nvidia,dsi-panel-reset: Indicate if dsi output device requires hardware reset or not. + - nvidia,dsi-power-saving-suspend: With enabled, set dsi controller ultra low power mode in suspend. + - nvidia,dsi-video-data-type: The DSI operates in two transmission modes: video and host/command. + Write 0, 1 for TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, respectively. + - nvidia,dsi-video-clock-mode: Control for the hs clock lane. Continuous means hs clock on all the time. + Txonly means only hs clock active during hs transmissions. Write 0, 1 for TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS, + and TEGRA_DSI_VIDEO_CLOCK_TX_ONLY, respectively. + - nvidia,dsi-init-cmd: panel required init command sequence. + - nvidia,dsi-n-init-cmd: command counts of init command sequence, including delay set. + - nvidia,dsi-suspend-cmd: panel required suspend command sequence. + - nvidia,dsi-n-suspend-cmd: command counts of suspend command sequence, including delay set. + - nvidia,dsi-early-suspend-cmd: panel required early suspend command sequence. + - nvidia,dsi-n-early-suspend-cmd: command counts of early suspend command sequence, including delay set. + - nvidia,dsi-late-resume-cmd: panel required late resume command sequence. + - nvidia,dsi-n-late-resume-cmd: command counts of late resume command sequence, including delay set. + - nvidia,dsi-pkt-seq: custom packet sequence since some panels need non standard packet sequence. + - nvidia,dsi-te-gpio: specifies a GPIO used for dsi panel TE signal. + - nvidia,nvidia,dsi-ganged-type: specifies dsi ganged type. 1 for TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT, + 2 for TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD. + - nvidia,dsi-phy-hsdexit: dsi phy timing, t_hsdexit_ns. + - nvidia,dsi-phy-hstrail: dsi phy timing, t_hstrail_ns. + - nvidia,dsi-phy-datzero: dsi phy timing, t_datzero_ns. + - nvidia,dsi-phy-hsprepare: dsi phy timing, t_hsprepare_ns. + - nvidia,dsi-phy-clktrail: dsi phy timing, t_clktrail_ns. + - nvidia,dsi-phy-clkpost: dsi phy timing, t_clkpost_ns. + - nvidia,dsi-phy-clkzero: dsi phy timing, t_clkzero_ns. + - nvidia,dsi-phy-tlpx: dsi phy timing, t_tlpx_ns. + - nvidia,dsi-phy-clkprepare: dsi phy timing, t_clkprepare_ns. + - nvidia,dsi-phy-clkpre: dsi phy timing, t_clkpre_ns. + - nvidia,dsi-phy-wakeup: dsi phy timing, t_wakeup_ns. + - nvidia,dsi-phy-taget: dsi phy timing, t_taget_ns. + - nvidia,dsi-phy-tasure: dsi phy timing, t_tasure_ns. + - nvidia,dsi-phy-tago: dsi phy timing, t_tago_ns. + +Example + host1x { + dsi { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>, + <0x54400000 0x00040000>; + status = "okay"; + nvidia,dsi-controller-vs = <1>; + panel-l-wxga-7 { + status = "okay"; + compatible = "lg,wxga-7"; + nvidia,dsi-instance = <0>; + nvidia,dsi-n-data-lanes = <4>; + nvidia,dsi-pixel-format = <3>; + nvidia,dsi-refresh-rate = <60>; + nvidia,dsi-video-data-type = <0>; + nvidia,dsi-video-clock-mode = <0>; + nvidia,dsi-video-burst-mode = <0>; + nvidia,dsi-virtual-channel = <0>; + nvidia,dsi-power-saving-suspend = <1>; + nvidia,dsi-phy-datzero = <270>; + nvidia,dsi-phy-hsprepare = <30>; + nvidia,dsi-phy-clkzero = <330>; + nvidia,dsi-phy-clkprepare = <27>; + nvidia,dsi-init-cmd = <0x0 0x15 0x01 0x0 0x0>, + <1 20>, + <0x0 0x15 0xae 0x0b 0x0>, + <0x0 0x15 0xee 0xea 0x0>, + <0x0 0x15 0xef 0x5f 0x0>, + <0x0 0x15 0xf2 0x68 0x0>, + <0x0 0x15 0xee 0x0 0x0>, + <0x0 0x15 0xef 0x0 0x0>; + nvidia,dsi-n-init-cmd = <8>; + nvidia,dsi-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, + <1 160>; + nvidia,dsi-n-suspend-cmd = <2>; + nvidia,dsi-late-resume-cmd = <0x0 0x15 0x10 0x0 0x0>, + <1 120>; + nvidia,dsi-n-late-resume-cmd = <2>; + nvidia,dsi-early-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, + <1 160>; + nvidia,dsi-n-early-suspend-cmd = <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt new file mode 100644 index 000000000000..83cfc2df95a0 --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt @@ -0,0 +1,55 @@ +NVIDIA TEGRA114 High Definition Multimedia Interface +==================================================== + +1) The hdmi node: + hdmi node must be contained in host1x parent node. This node represents NVIDIA TEGRA114 + High Definition Multimedia Interface. + + Required properties + - name: hdmi + - compatible: Should contain "nvidia,tegra114-hdmi". + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + + Optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,hotplug-report: With 1, it will have optional hotplug report callback + which does only set DDC_SDA and DDC_SCL pull downs to be active when hotplug + is detected, otherwise keep them disabled. + + 1.B) NVIDIA HDMI TMDS configurations + This must be contained in hdmi parent node. This includes tmds configurations. + + Required properties: + - name: Should be "nvidia,out-tmds-cfg" + + - Child nodes represent tmds configurations. Several configurations can be prepared. + + 1.B.i) NVIDIA HDMI TMDS configuration + This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - pclk: pixel clk required in tmds table for each mode. + - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM. + - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM. + - pe-current: Individual lane pre-emphasis current control (4bits per lane) + See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM. + - drive-current: TMDS per-lane I/O current control. + See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM. + - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane. + See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM. + +Example + host1x { + hdmi { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + status = "okay"; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt new file mode 100644 index 000000000000..e91b7c3f5998 --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt @@ -0,0 +1,370 @@ +NVIDIA Tegra124 Display Controller +================================== + +1) The dc node: + dc node must be contained in host1x parent node. This node represents + NVIDIA Tegra124 Display controller. + + Required properties: + - name: dc + - compatible: Should contain "nvidia,tegra124-dc". + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - nvidia,memory-clients: This is the "swgroup" ID in the Tegra TRM term. + - nvidia,dc-flags: This is to enable display controller in probe time. + "dc_flag_en" or remove this property (do not set this property). + - nvidia,emc-clk-rate: Initially required embedded memory controller clk rate. + - nvidia,cmu-enable: Toggle switch for color management unit. + - nvidia,low-v-win: If low_v_win is set, we can lower vdd_core when that windows + is the only one active. + - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage, + HDMI_AVDD. + - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply. + - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source. + + - Child nodes represent node of modes, output settings, framebuffer data, + smart dimmer settings, color management unit settings, dsi output device settings. + +1.A) NVIDIA Display Controller Modes + This must be contained in dc parent node. This contains supported modes. + + Required properties: + - name: Should be "display-timings" + + - Child nodes represent modes. Several modes can be prepared. + +1.A.i) NVIDIA Display Controller Mode timing + This must be contained in display-timings parent node. This contains mode settings, including + display timings. For hdmi out-type case, display-timings properties are only valid in case of + hdmi fb console mode. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - hactive, vactive: display resolution. + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels. + - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines. + - clock-frequency: display clock in Hz. + - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC + with respect to H reference point. + - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC + with respect to V reference point. + +1.B) NVIDIA Display Controller Default Output Settings + This must be contained in dc parent node. This is default output settings. + + Required properties: + - name: Should be "dc-default-out". + - nvidia,out-type: Output type. Should be "dsi" or "hdmi". + - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. + - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. + - nvidia,out-flags: Should be "continuous" or "oneshot" or "hotplug_high" or "hotplug_low" + or "continuous_initialized" or "oneshot_initialized" + - nvidia,out-parent-clk: Parent clk for display controller. + - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. + - nvidia,out-align: Display data alignment. Should be "msb" or "lsb". + - nvidia,out-order: Display data order. Should be "rtob" or "btor". + - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for + BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, + BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, + and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. + For hdmi out-type case, depth selection is only valid for hdmi fb console mode, + otherwise, BASE_COLOR_SIZE888 is chosen as a default. + +1.C) NVIDIA Display Controller framebuffer data + This must be contained in dc parent node. This is required framebuffer data. + +Required properties: + - name: Should be "framebuffer-data". + - nvidia,fb-bpp: Bits per pixel of fb. + - nvidia,fb-flags: Window is updated in display controller device probe. Should be "flip_on_probe", + or remove this property (do not set this property). + - nvidia,fb-xres: Visible resolution for width. + - nvidia,fb-yres: Visible resolution for height. + +1.D) NVIDIA Display Controller Smart Dimmer Settings + This must be contained in dc parent node. This is smart dimmer settings. + + Required properties: + - name: Should be "smartdimmer". + - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control + signal directly. + - nvidia,hw-update-delay: It determines the delay of the update of the hardware + enhancement value (K) that is applied to the pixels. + - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. + 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment + of -1, indicates automatic based on aggressiveness. + - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. + - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. + - nvidia,phase-in-adjustments: Software backlight phase-in + - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) + rather than computed from nvidia,aggressiveness. + - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of + aggressiveness. + - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) + to a rectangular subset of display. + - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels + above nvidia,soft-clipping-threshold level to avoid saturation. + - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. + - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to + nvidia,smooth-k-incr. + - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed + at most by smooth-k-incr per frame. + - nvidia,coeff: Luminance calculation coefficients used to convert the red green and + blue color components into a luminance value. The conversion is performed according to + the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. + Need to write blue, green, red coefficient for luminance calculation in sequence. + - nvidia,fc: Flicker control that prevents rapid and frequent changes + in the enhancement value. Need to write time_limit, threshold in sequence. + - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to + write time_constant for the response curve and step that determines the instantaneous + portion of the target value of enhancement that is applied: <time_constant, step>. + - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve + defines how the backlight output changes with respect to the control input. The 17th point + is defined to be the maximum value. + - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k + for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). + There are nine entries in total. + - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. + - nvidia,bl-device-name: Backlight device name. + +1.E) NVIDIA Display Controller Color Management Unit Settings + This must be contained in dc parent node. This is color management unit settings. + + Required properties: + - name: Should be "cmu". + - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. + - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + +Example + host1x { + /* tegradc.0 */ + dc@54200000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + status = "okay"; + nvidia,dc-flags = "dc_flag_en"; + nvidia,emc-clk-rate = <204000000>; + nvidia,cmu-enable = <1>; + avdd_hdmi-supply = <&palmas_ldoln>; + avdd_hdmi_pll-supply = <&palmas_ldo1>; + vdd_hdmi_5v0-supply = <&vdd_hdmi>; + dc-default-out { + nvidia,out-type = "dsi"; + nvidia,out-width = <217>; + nvidia,out-height = <135>; + nvidia,out-flags = "continuous"; + nvidia,out-parent-clk = "pll_d_out0"; + }; + display-timings { + 1920p32 { + clock-frequency = <154700000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <120>; + hback-porch = <32>; + hsync-len = <16>; + vfront-porch = <17>; + vback-porch = <16>; + vsync-len = <2>; + nvidia,h-ref-to-sync = <4>; + nvidia,v-ref-to-sync = <1>; + }; + }; + framebuffer-data { + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = "flip_on_probe"; + nvidia,fb-xres = <1920>; + nvidia,fb-yres = <1200>; + }; + smartdimmer { + status = "okay"; + nvidia,use-auto-pwm = <0>; + nvidia,hw-update-delay = <0>; + nvidia,bin-width = <0xffffffff>; + nvidia,aggressiveness = <5>; + nvidia,use-vid-luma = <0>; + nvidia,phase-in-settings = <0>; + nvidia,phase-in-adjustments = <0>; + nvidia,k-limit-enable = <1>; + nvidia,k-limit = <200>; + nvidia,sd-window-enable = <0>; + nvidia,soft-clipping-enable= <1>; + nvidia,soft-clipping-threshold = <128>; + nvidia,smooth-k-enable = <1>; + nvidia,smooth-k-incr = <4>; + nvidia,coeff = <5 9 2>; + nvidia,fc = <0 0>; + nvidia,blp = <1024 255>; + nvidia,bltf = <57 65 73 82 + 92 103 114 125 + 138 150 164 178 + 193 208 224 241>; + nvidia,lut = <255 255 255 + 199 199 199 + 153 153 153 + 116 116 116 + 85 85 85 + 59 59 59 + 36 36 36 + 17 17 17 + 0 0 0>; + nvidia,use-vpulse2 = <1>; + nvidia,bl-device-name = "pwm-backlight"; + }; + cmu { + status = "okay"; + nvidia,cmu-csc = < 0x138 0x3Ba 0x00D + 0x3F5 0x120 0x3E6 + 0x3FE 0x3F8 0x0E9 >; + nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6 + 7 8 9 10 11 11 12 13 + 13 14 15 15 16 17 17 18 + 18 19 19 20 20 21 21 22 + 22 23 23 23 24 24 24 25 + 25 25 26 26 26 27 27 27 + 28 28 28 28 29 29 29 29 + 30 30 30 30 31 31 31 31 + 32 32 32 32 33 33 33 33 + 34 34 34 35 35 35 35 36 + 36 36 37 37 37 37 38 38 + 38 39 39 39 39 40 40 40 + 41 41 41 41 42 42 42 43 + 43 43 43 44 44 44 45 45 + 45 45 46 46 46 46 47 47 + 47 47 48 48 48 48 49 49 + 49 49 50 50 50 50 50 51 + 51 51 51 52 52 52 52 52 + 53 53 53 53 53 53 54 54 + 54 54 54 55 55 55 55 55 + 55 56 56 56 56 56 56 57 + 57 57 57 57 57 57 58 58 + 58 58 58 58 59 59 59 59 + 59 59 59 60 60 60 60 60 + 60 60 61 61 61 61 61 61 + 61 62 62 62 62 62 62 62 + 63 63 63 63 63 63 63 64 + 64 64 64 64 64 64 65 65 + 65 65 65 65 66 66 66 66 + 66 66 66 67 67 67 67 67 + 67 68 68 68 68 68 68 69 + 69 69 69 69 69 70 70 70 + 70 70 70 71 71 71 71 71 + 71 72 72 72 72 72 72 73 + 73 73 73 73 73 74 74 74 + 74 74 74 74 75 75 75 75 + 75 75 76 76 76 76 76 76 + 77 77 77 77 77 77 77 78 + 78 78 78 78 78 79 79 79 + 79 79 79 79 80 80 80 80 + 80 80 80 80 81 81 81 81 + 81 81 81 82 82 82 82 82 + 82 82 82 83 83 83 83 83 + 83 83 83 83 84 84 84 84 + 84 84 84 84 85 85 85 85 + 85 85 85 85 85 85 86 86 + 86 86 86 86 86 86 86 86 + 87 87 87 87 87 87 87 87 + 87 87 88 88 88 88 88 88 + 88 88 88 88 88 88 89 89 + 89 89 89 89 89 89 89 89 + 89 89 90 90 90 90 90 90 + 90 90 90 90 90 90 91 91 + 91 91 91 91 91 91 91 91 + 91 91 91 92 92 92 92 92 + 92 92 92 92 92 92 92 92 + 93 93 93 93 93 93 93 93 + 93 93 93 93 93 93 94 94 + 94 94 94 94 94 94 94 94 + 94 94 94 94 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 96 96 96 96 96 96 96 + 96 96 96 96 96 96 97 97 + 97 97 97 97 97 97 97 97 + 98 99 99 100 101 101 102 103 + 103 104 105 105 106 107 107 108 + 109 110 110 111 112 112 113 114 + 114 115 115 116 117 117 118 119 + 119 120 120 121 121 122 123 123 + 124 124 125 125 126 126 127 128 + 128 129 129 130 130 131 131 132 + 132 133 133 134 134 135 135 136 + 136 137 138 138 139 139 140 140 + 141 141 142 142 143 143 144 144 + 144 145 145 146 146 147 147 148 + 148 149 149 150 150 151 151 152 + 152 153 153 153 154 154 155 155 + 156 156 157 157 157 158 158 159 + 159 160 160 160 161 161 162 162 + 162 163 163 164 164 164 165 165 + 165 166 166 167 167 167 168 168 + 168 169 169 169 170 170 171 171 + 171 172 172 172 173 173 173 174 + 174 174 175 175 175 176 176 176 + 177 177 177 178 178 178 179 179 + 179 180 180 180 181 181 181 182 + 182 182 183 183 183 184 184 184 + 185 185 185 185 186 186 186 187 + 187 187 188 188 188 189 189 189 + 190 190 190 191 191 191 191 192 + 192 192 193 193 193 194 194 194 + 195 195 195 195 196 196 196 197 + 197 197 198 198 198 199 199 199 + 199 200 200 200 201 201 201 202 + 202 202 203 203 203 203 204 204 + 204 205 205 205 206 206 206 207 + 207 207 208 208 208 208 209 209 + 209 210 210 210 211 211 211 212 + 212 212 213 213 213 214 214 214 + 215 215 215 215 216 216 216 217 + 217 217 218 218 218 219 219 219 + 220 220 220 220 221 221 221 222 + 222 222 222 223 223 223 224 224 + 224 224 225 225 225 226 226 226 + 226 227 227 227 227 228 228 228 + 229 229 229 229 230 230 230 230 + 230 231 231 231 231 232 232 232 + 232 233 233 233 233 234 234 234 + 234 234 235 235 235 235 236 236 + 236 236 236 237 237 237 237 238 + 238 238 238 238 239 239 239 239 + 239 240 240 240 240 240 241 241 + 241 241 241 242 242 242 242 243 + 243 243 243 243 244 244 244 244 + 244 245 245 245 245 245 246 246 + 246 246 246 247 247 247 247 248 + 248 248 248 248 249 249 249 249 + 250 250 250 250 251 251 251 251 + 251 252 252 252 253 253 253 253 + 254 254 254 254 255 255 255 255 >; + }; + }; + + /* tegradc.1 */ + dc@54240000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + status = "okay"; + nvidia,dc-flags = "dc_flag_en"; + nvidia,emc-clk-rate = <300000000>; + nvidia,cmu-enable = <1>; + dc-default-out { + nvidia,out-type = "hdmi"; + nvidia,out-flags = "hotplug_high"; + nvidia,out-parent-clk = "pll_d2"; + nvidia,out-max-pixclk = <297000>; + nvidia,out-align = "msb"; + nvidia,out-order = "rtob"; /*red to blue*/ + }; + framebuffer-data { + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = "flip_on_probe"; + nvidia,fb-xres = <1280>; + nvidia,fb-yres = <720>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt new file mode 100644 index 000000000000..3b37ec66b16f --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt @@ -0,0 +1,118 @@ +NVIDIA TEGRA124 Display Serial Interface +======================================== + +1) The dsi node: + dsi node must be contained in host1x parent node. This node represents NVIDIA Tegra124 Display + Serial Interface. + + Required properties + - name: dsi + - compatible: Should contain "nvidia,tegra124-dsi". + - reg: Physical base address and length of the controller's registers. + - nvidia,dsi-controller-vs: DSI version. Write 0, 1 for DSI_VS_0 and DSI_VS_1, respectively. For TEGRA124, + it should be 1. + + - Child node represents dsi panel node. + +1.A) dsi panel node: + dsi panel node must be contained in dsi parent node. This node represents dsi panel node. + + Required properties + - name: Can be arbitrary. + - compatible: Can be arbitrary. One panel has its own unique compatible. + - nvidia,dsi-panel-rst-gpio: panel reset gpio. + - nvidia,dsi-panel-bl-en-gpio: backlight enabling gpio. + - nvidia,dsi-panel-bl-pwm-gpio: gpio for backlight pwm signal. + - nvidia,dsi-te-gpio: gpio for panel TE(Tearing Effect) signal. + - nvidia,dsi-n-data-lanes: Number of DSI lanes in use. Should be one of 2, 3, 4, and 8 + - nvidia,dsi-video-burst-mode: Video mode. Write 0, 1, 2, 3, 4, 5 and 6 for TEGRA_DSI_VIDEO_NONE_BURST_MODE, + TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END, TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED, + TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED, TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED, + TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED and TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED, + respectively. + - nvidia,dsi-pixel-format: DSI pixel data format. Write 0, 1, 2, 3 for TEGRA_DSI_PIXEL_FORMAT_16BIT_P, + TEGRA_DSI_PIXEL_FORMAT_18BIT_P, TEGRA_DSI_PIXEL_FORMAT_18BIT_NP and TEGRA_DSI_PIXEL_FORMAT_24BIT_P, + respectively. + - nvidia,dsi-refresh-rate: Refresh rate. + - nvidia,dsi-virtual-channel: DSI virtual channel number. Write 0, 1, 2 and 3 for TEGRA_DSI_VIRTUAL_CHANNEL_0, + TEGRA_DSI_VIRTUAL_CHANNEL_1, TEGRA_DSI_VIRTUAL_CHANNEL_2 and TEGRA_DSI_VIRTUAL_CHANNEL_3, respectively. + - nvidia,dsi-instance: Should be 0 or 1: DSI controller or DSIB controller. + - nvidia,dsi-panel-reset: Indicate if dsi output device requires hardware reset or not. + - nvidia,dsi-power-saving-suspend: With enabled, set dsi controller ultra low power mode in suspend. + - nvidia,dsi-video-data-type: The DSI operates in two transmission modes: video and host/command. + Write 0, 1 for TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, respectively. + - nvidia,dsi-video-clock-mode: Control for the hs clock lane. Continuous means hs clock on all the time. + Txonly means only hs clock active during hs transmissions. Write 0, 1 for TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS, + and TEGRA_DSI_VIDEO_CLOCK_TX_ONLY, respectively. + - nvidia,dsi-init-cmd: panel required init command sequence. + - nvidia,dsi-n-init-cmd: command counts of init command sequence, including delay set. + - nvidia,dsi-suspend-cmd: panel required suspend command sequence. + - nvidia,dsi-n-suspend-cmd: command counts of suspend command sequence, including delay set. + - nvidia,dsi-early-suspend-cmd: panel required early suspend command sequence. + - nvidia,dsi-n-early-suspend-cmd: command counts of early suspend command sequence, including delay set. + - nvidia,dsi-late-resume-cmd: panel required late resume command sequence. + - nvidia,dsi-n-late-resume-cmd: command counts of late resume command sequence, including delay set. + - nvidia,dsi-pkt-seq: custom packet sequence since some panels need non standard packet sequence. + - nvidia,dsi-te-gpio: specifies a GPIO used for dsi panel TE signal. + - nvidia,nvidia,dsi-ganged-type: specifies dsi ganged type. 1 for TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT, + 2 for TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD. + - nvidia,dsi-phy-hsdexit: dsi phy timing, t_hsdexit_ns. + - nvidia,dsi-phy-hstrail: dsi phy timing, t_hstrail_ns. + - nvidia,dsi-phy-datzero: dsi phy timing, t_datzero_ns. + - nvidia,dsi-phy-hsprepare: dsi phy timing, t_hsprepare_ns. + - nvidia,dsi-phy-clktrail: dsi phy timing, t_clktrail_ns. + - nvidia,dsi-phy-clkpost: dsi phy timing, t_clkpost_ns. + - nvidia,dsi-phy-clkzero: dsi phy timing, t_clkzero_ns. + - nvidia,dsi-phy-tlpx: dsi phy timing, t_tlpx_ns. + - nvidia,dsi-phy-clkprepare: dsi phy timing, t_clkprepare_ns. + - nvidia,dsi-phy-clkpre: dsi phy timing, t_clkpre_ns. + - nvidia,dsi-phy-wakeup: dsi phy timing, t_wakeup_ns. + - nvidia,dsi-phy-taget: dsi phy timing, t_taget_ns. + - nvidia,dsi-phy-tasure: dsi phy timing, t_tasure_ns. + - nvidia,dsi-phy-tago: dsi phy timing, t_tago_ns. + +Example + host1x { + dsi { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54300000 0x00040000>, + <0x54400000 0x00040000>; + status = "okay"; + nvidia,dsi-controller-vs = <1>; + panel-l-wxga-7 { + status = "okay"; + compatible = "lg,wxga-7"; + nvidia,dsi-instance = <0>; + nvidia,dsi-n-data-lanes = <4>; + nvidia,dsi-pixel-format = <3>; + nvidia,dsi-refresh-rate = <60>; + nvidia,dsi-video-data-type = <0>; + nvidia,dsi-video-clock-mode = <0>; + nvidia,dsi-video-burst-mode = <0>; + nvidia,dsi-virtual-channel = <0>; + nvidia,dsi-power-saving-suspend = <1>; + nvidia,dsi-phy-datzero = <270>; + nvidia,dsi-phy-hsprepare = <30>; + nvidia,dsi-phy-clkzero = <330>; + nvidia,dsi-phy-clkprepare = <27>; + nvidia,dsi-init-cmd = <0x0 0x15 0x01 0x0 0x0>, + <1 20>, + <0x0 0x15 0xae 0x0b 0x0>, + <0x0 0x15 0xee 0xea 0x0>, + <0x0 0x15 0xef 0x5f 0x0>, + <0x0 0x15 0xf2 0x68 0x0>, + <0x0 0x15 0xee 0x0 0x0>, + <0x0 0x15 0xef 0x0 0x0>; + nvidia,dsi-n-init-cmd = <8>; + nvidia,dsi-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, + <1 160>; + nvidia,dsi-n-suspend-cmd = <2>; + nvidia,dsi-late-resume-cmd = <0x0 0x15 0x10 0x0 0x0>, + <1 120>; + nvidia,dsi-n-late-resume-cmd = <2>; + nvidia,dsi-early-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, + <1 160>; + nvidia,dsi-n-early-suspend-cmd = <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt new file mode 100644 index 000000000000..9a0ccc2f5e6f --- /dev/null +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt @@ -0,0 +1,55 @@ +NVIDIA TEGRA124 High Definition Multimedia Interface +==================================================== + +1) The hdmi node: + hdmi node must be contained in host1x parent node. This node represents NVIDIA TEGRA124 + High Definition Multimedia Interface. + + Required properties + - name: hdmi + - compatible: Should contain "nvidia,tegra124-hdmi". + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + + Optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,hotplug-report: With 1, it will have optional hotplug report callback + which does only set DDC_SDA and DDC_SCL pull downs to be active when hotplug + is detected, otherwise keep them disabled. + + 1.B) NVIDIA HDMI TMDS configurations + This must be contained in hdmi parent node. This includes tmds configurations. + + Required properties: + - name: Should be "nvidia,out-tmds-cfg" + + - Child nodes represent tmds configurations. Several configurations can be prepared. + + 1.B.i) NVIDIA HDMI TMDS configuration + This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - pclk: pixel clk required in tmds table for each mode. + - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM. + - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM. + - pe-current: Individual lane pre-emphasis current control (4bits per lane) + See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM. + - drive-current: TMDS per-lane I/O current control. + See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM. + - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane. + See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM. + +Example + host1x { + hdmi { + compatible = "nvidia,tegra124-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + status = "okay"; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 1>; + }; + }; diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt index b4671459857f..d6baf9a42762 100644 --- a/Documentation/driver-model/devres.txt +++ b/Documentation/driver-model/devres.txt @@ -237,6 +237,14 @@ MEM devm_kzalloc() devm_kfree() +IIO + devm_iio_device_alloc() + devm_iio_device_free() + devm_iio_trigger_alloc() + devm_iio_trigger_free() + devm_iio_device_register() + devm_iio_device_unregister() + IO region devm_request_region() devm_request_mem_region() @@ -277,6 +285,7 @@ REGULATOR devm_regulator_get() devm_regulator_put() devm_regulator_bulk_get() + devm_regulator_register() CLOCK devm_clk_get() diff --git a/Documentation/hwmon/k10temp b/Documentation/hwmon/k10temp index 90956b618025..4dfdc8f83633 100644 --- a/Documentation/hwmon/k10temp +++ b/Documentation/hwmon/k10temp @@ -12,6 +12,7 @@ Supported chips: * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series) * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series) * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity" +* AMD Family 16h processors: "Kabini" Prefix: 'k10temp' Addresses scanned: PCI space diff --git a/Documentation/i2c/busses/i2c-piix4 b/Documentation/i2c/busses/i2c-piix4 index 1e6634f54c50..a370b2047cf3 100644 --- a/Documentation/i2c/busses/i2c-piix4 +++ b/Documentation/i2c/busses/i2c-piix4 @@ -13,7 +13,7 @@ Supported adapters: * AMD SP5100 (SB700 derivative found on some server mainboards) Datasheet: Publicly available at the AMD website http://support.amd.com/us/Embedded_TechDocs/44413.pdf - * AMD Hudson-2 + * AMD Hudson-2, CZ Datasheet: Not publicly available * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge Datasheet: Publicly available at the SMSC website http://www.smsc.com diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 3458d6343e01..a59ee432a98f 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -478,6 +478,15 @@ tcp_syn_retries - INTEGER tcp_timestamps - BOOLEAN Enable timestamps as defined in RFC1323. +tcp_min_tso_segs - INTEGER + Minimal number of segments per TSO frame. + Since linux-3.12, TCP does an automatic sizing of TSO frames, + depending on flow rate, instead of filling 64Kbytes packets. + For specific usages, it's possible to force TCP to build big + TSO frames. Note that TCP stack might split too big TSO packets + if available window is too small. + Default: 2 + tcp_tso_win_divisor - INTEGER This allows control over what percentage of the congestion window can be consumed by a single TSO frame. @@ -562,9 +571,6 @@ tcp_limit_output_bytes - INTEGER typical pfifo_fast qdiscs. tcp_limit_output_bytes limits the number of bytes on qdisc or device to reduce artificial RTT/cwnd and reduce bufferbloat. - Note: For GSO/TSO enabled flows, we try to have at least two - packets in flight. Reducing tcp_limit_output_bytes might also - reduce the size of individual GSO packet (64KB being the max) Default: 131072 tcp_challenge_ack_limit - INTEGER diff --git a/Documentation/parisc/registers b/Documentation/parisc/registers index dd3caddd1ad9..10c7d1730f5d 100644 --- a/Documentation/parisc/registers +++ b/Documentation/parisc/registers @@ -78,6 +78,14 @@ Shadow Registers used by interruption handler code TOC enable bit 1 ========================================================================= + +The PA-RISC architecture defines 7 registers as "shadow registers". +Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce +the state save and restore time by eliminating the need for general register +(GR) saves and restores in interruption handlers. +Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. + +========================================================================= Register usage notes, originally from John Marvin, with some additional notes from Randolph Chung. diff --git a/Documentation/pasr.txt b/Documentation/pasr.txt new file mode 100644 index 000000000000..d40e3f6678cb --- /dev/null +++ b/Documentation/pasr.txt @@ -0,0 +1,183 @@ +Partial Array Self-Refresh Framework + +(C) 2012 Maxime Coquelin <maxime.coquelin@stericsson.com>, ST-Ericsson. + +CONTENT +1. Introduction +2. Command-line parameters +3. Allocators patching +4. PASR platform drivers + + +1. Introduction + +PASR Frameworks brings support for the Partial Array Self-Refresh DDR power +management feature. PASR has been introduced in LP-DDR2, and is also present +in DDR3. + +PASR provides 4 modes: + +* Single-Ended: Only 1/1, 1/2, 1/4 or 1/8 are refreshed, masking starting at + the end of the DDR die. + +* Double-Ended: Same as Single-Ended, but refresh-masking does not start + necessairly at the end of the DDR die. + +* Bank-Selective: Refresh of each bank of a die can be masked or unmasked via + a dedicated DDR register (MR16). This mode is convenient for DDR configured + in BRC (Bank-Row-Column) mode. + +* Segment-Selective: Refresh of each segment of a die can be masked or unmasked + via a dedicated DDR register (MR17). This mode is convenient for DDR configured + in RBC (Row-Bank-Column) mode. + +The role of this framework is to stop the refresh of unused memory to enhance +DDR power consumption. + +It supports Bank-Selective and Segment-Selective modes, as the more adapted to +modern OSes. + +At early boot stage, a representation of the physical DDR layout is built: + + Die 0 +_______________________________ +| I--------------------------I | +| I Bank or Segment 0 I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment 1 I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment ... I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment n I | +| I--------------------------I | +|______________________________| + ... + + Die n +_______________________________ +| I--------------------------I | +| I Bank or Segment 0 I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment 1 I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment ... I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment n I | +| I--------------------------I | +|______________________________| + +The first level is a table where elements represent a die: +* Base address, +* Number of segments, +* Table representing banks/segments, +* MR16/MR17 refresh mask, +* DDR Controller callback to update MR16/MR17 refresh mask. + +The second level is the section tables representing the banks or segments, +depending on hardware configuration: +* Base address, +* Unused memory size counter, +* Possible pointer to another section it depends on (E.g. Interleaving) + +When some memory becomes unused, the allocator owning this memory calls the PASR +Framework's pasr_put(phys_addr, size) function. The framework finds the +sections impacted and updates their counters accordingly. +If a section counter reach the section size, the refresh of the section is +masked. If the corresponding section has a dependency with another section +(E.g. because of DDR interleaving, see figure below), it checks the "paired" section is also +unused before updating the refresh mask. + +When some unused memory is requested by the allocator, the allocator owning +this memory calls the PASR Framework's pasr_get(phys_addr, size) function. The +framework find the section impacted and updates their counters accordingly. +If before the update, the section counter was to the section size, the refrewh +of the section is unmasked. If the corresponding section has a dependency with +another section, it also unmask the refresh of the other section. + +Interleaving example: + + Die 0 +_______________________________ +| I--------------------------I | +| I Bank or Segment 0 I |<----| +| I--------------------------I | | +| I--------------------------I | | +| I Bank or Segment 1 I | | +| I--------------------------I | | +| I--------------------------I | | +| I Bank or Segment ... I | | +| I--------------------------I | | +| I--------------------------I | | +| I Bank or Segment n I | | +| I--------------------------I | | +|______________________________| | + | + Die 1 | +_______________________________ | +| I--------------------------I | | +| I Bank or Segment 0 I |<----| +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment 1 I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment ... I | +| I--------------------------I | +| I--------------------------I | +| I Bank or Segment n I | +| I--------------------------I | +|______________________________| + +In the above example, bank 0 of die 0 is interleaved with bank0 of die 0. +The interleaving is done in HW by inverting some addresses lines. The goal is +to improve DDR bandwidth. +Practically, one buffer seen as contiguous by the kernel might be spread +into two DDR dies physically. + + +2. Command-line parameters + +To buid the DDR physical layout representation, two parameters are requested: + +* ddr_die (mandatory): Should be added for every DDR dies present in the system. + - Usage: ddr_die=xxx[M|G]@yyy[M|G] where xxx represents the size and yyy + the base address of the die. E.g.: ddr_die=512M@0 ddr_die=512M@512M + +* interleaved (optionnal): Should be added for every interleaved dependencies. + - Usage: interleaved=xxx[M|G]@yyy[M|G]:zzz[M|G] where xxx is the size of + the interleaved area between the adresses yyy and zzz. E.g + interleaved=256M@0:512M + + +3. Allocator patching + +Any allocators might call the PASR Framework for DDR power savings. Currently, +only Linux Buddy allocator is patched, but HWMEM and PMEM physically +contiguous memory allocators will follow. + +Linux Buddy allocator porting uses Buddy specificities to reduce the overhead +induced by the PASR Framework counter updates. Indeed, the PASR Framework is +called only when MAX_ORDER (4MB page blocs by default) buddies are +inserted/removed from the free lists. + +To port PASR FW into a new allocator: + +* Call pasr_put(phys_addr, size) each time a memory chunk becomes unused. +* Call pasr_get(phys_addr, size) each time a memory chunk becomes used. + +4. PASR platform drivers + +The MR16/MR17 PASR mask registers are generally accessible through the DDR +controller. At probe time, the DDR controller driver should register the +callback used by PASR Framework to apply the refresh mask for every DDR die +using pasr_register_mask_function(die_addr, callback, cookie). + +The callback passed to apply mask must not sleep since it can me called in +interrupt contexts. + diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt index ccd42589e124..9b34b1685078 100644 --- a/Documentation/sysctl/kernel.txt +++ b/Documentation/sysctl/kernel.txt @@ -289,13 +289,24 @@ Default value is "/sbin/hotplug". kptr_restrict: This toggle indicates whether restrictions are placed on -exposing kernel addresses via /proc and other interfaces. When -kptr_restrict is set to (0), there are no restrictions. When -kptr_restrict is set to (1), the default, kernel pointers -printed using the %pK format specifier will be replaced with 0's -unless the user has CAP_SYSLOG. When kptr_restrict is set to -(2), kernel pointers printed using %pK will be replaced with 0's -regardless of privileges. +exposing kernel addresses via /proc and other interfaces. + +When kptr_restrict is set to (0), the default, there are no restrictions. + +When kptr_restrict is set to (1), kernel pointers printed using the %pK +format specifier will be replaced with 0's unless the user has CAP_SYSLOG +and effective user and group ids are equal to the real ids. This is +because %pK checks are done at read() time rather than open() time, so +if permissions are elevated between the open() and the read() (e.g via +a setuid binary) then %pK will not leak kernel pointers to unprivileged +users. Note, this is a temporary solution only. The correct long-term +solution is to do the permission checks at open() time. Consider removing +world read permissions from files that use %pK, and using dmesg_restrict +to protect against uses of %pK in dmesg(8) if leaking kernel pointer +values to unprivileged users is a concern. + +When kptr_restrict is set to (2), kernel pointers printed using +%pK will be replaced with 0's regardless of privileges. ============================================================== diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index a71bd5b90fe8..87519cb379ee 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -134,6 +134,13 @@ temperature) and throttle appropriate devices. this thermal zone and cdev, for a particular trip point. If nth bit is set, then the cdev and thermal zone are bound for trip point n. + .limits: This is an array of cooling state limits. Must have exactly + 2 * thermal_zone.number_of_trip_points. It is an array consisting + of tuples <lower-state upper-state> of state limits. Each trip + will be associated with one state limit tuple when binding. + A NULL pointer means <THERMAL_NO_LIMITS THERMAL_NO_LIMITS> + on all trips. These limits are used when binding a cdev to a + trip point. .match: This call back returns success(0) if the 'tz and cdev' need to be bound, as per platform data. 1.4.2 struct thermal_zone_params @@ -142,6 +149,11 @@ temperature) and throttle appropriate devices. This is an optional feature where some platforms can choose not to provide this data. .governor_name: Name of the thermal governor used for this zone + .no_hwmon: a boolean to indicate if the thermal to hwmon sysfs interface + is required. when no_hwmon == false, a hwmon sysfs interface + will be created. when no_hwmon == true, nothing will be done. + In case the thermal_zone_params is NULL, the hwmon interface + will be created (for backward compatibility). .num_tbps: Number of thermal_bind_params entries for this zone .tbp: thermal_bind_params entries diff --git a/Documentation/trace/tracedump.txt b/Documentation/trace/tracedump.txt new file mode 100644 index 000000000000..cba0decc3fc3 --- /dev/null +++ b/Documentation/trace/tracedump.txt @@ -0,0 +1,58 @@ + Tracedump + + Documentation written by Alon Farchy + +1. Overview +============ + +The tracedump module provides additional mechanisms to retrieve tracing data. +It can be used to retrieve traces after a kernel panic or while the system +is running in either binary format or plaintext. The dumped data is compressed +with zlib to conserve space. + +2. Configuration Options +======================== + +CONFIG_TRACEDUMP - enable the tracedump module. +CONFIG_TRACEDUMP_PANIC - dump to console on kernel panic +CONFIG_TRACEDUMP_PROCFS - add file /proc/tracedump for userspace access. + +3. Module Parameters +==================== + +format_ascii + + If 1, data will dump in human-readable format, ordered by time. + If 0, data will be dumped as raw pages from the ring buffer, + ordered by CPU, followed by the saved cmdlines so that the + raw data can be decoded. Default: 0 + +panic_size + + Maximum amount of compressed data to dump during a kernel panic + in kilobytes. This only applies if format_ascii == 1. In this case, + tracedump will compress the data, check the size, and if it is too big + toss out some data, compress again, etc, until the size is below + panic_size. Default: 512KB + +compress_level + + Determines the compression level that zlib will use. Available levels + are 0-9, with 0 as no compression and 9 as maximum compression. + Default: 9. + +4. Usage +======== + +If configured with CONFIG_TRACEDUMP_PROCFS, the tracing data can be pulled +by reading from /proc/tracedump. For example: + + # cat /proc/tracedump > my_tracedump + +Tracedump will surround the dump with a magic word (TRACEDUMP). Between the +magic words is the compressed data, which can be decompressed with a standard +zlib implementation. After decompression, if format_ascii == 1, then the +output should be readable. + +If format_ascii == 0, the output should be in binary form, delimited by +CPU_END. After the last CPU should be the saved cmdlines, delimited by |. diff --git a/Documentation/trace/tracelevel.txt b/Documentation/trace/tracelevel.txt new file mode 100644 index 000000000000..b282dd2b329b --- /dev/null +++ b/Documentation/trace/tracelevel.txt @@ -0,0 +1,42 @@ + Tracelevel + + Documentation by Alon Farchy + +1. Overview +=========== + +Tracelevel allows subsystem authors to add trace priorities to +their tracing events. High priority traces will be enabled +automatically at boot time. + +This module is configured with CONFIG_TRACELEVEL. + +2. Usage +========= + +To give an event a priority, use the function tracelevel_register +at any time. + + tracelevel_register(my_event, level); + +my_event corresponds directly to the event name as defined in the +event header file. Available levels are: + + TRACELEVEL_ERR 3 + TRACELEVEL_WARN 2 + TRACELEVEL_INFO 1 + TRACELEVEL_DEBUG 0 + +Any event registered at boot time as TRACELEVEL_ERR will be enabled +by default. The header also exposes the function tracelevel_set_level +to change the trace level at runtime. Any trace event registered with the +specified level or higher will be enabled with this call. + +A userspace handle to tracelevel_set_level is available via the module +parameter 'level'. For example, + + echo 1 > /sys/module/tracelevel/parameters/level + +Is logically equivalent to: + + tracelevel_set_level(TRACELEVEL_INFO); diff --git a/Documentation/video/tegra_dc_ext.txt b/Documentation/video/tegra_dc_ext.txt new file mode 100644 index 000000000000..6fc3394c6652 --- /dev/null +++ b/Documentation/video/tegra_dc_ext.txt @@ -0,0 +1,83 @@ +The Tegra display controller (dc) driver has two frontends that implement +different interfaces: +1. The traditional fbdev interface, implemented in drivers/video/tegra/fb.c +2. A new interface that exposes the unique capabilities of the controller, + implemented in drivers/video/tegra/dc/ext + +The Tegra fbdev capabilities are documented in fb/tegrafb.c [TODO]. This +document will describe the new "extended" dc interface. + +The extended interface is only available when its frontend has been compiled +in, i.e., CONFIG_TEGRA_DC_EXTENSIONS=y. The dc_ext frontend can coexist with +tegrafb, but takes precedence (more on that later). + +The dc_ext frontend's interface to userspace is exposed through a set of +device nodes: one for each controller (generally /dev/tegra_dc_N), and one +"control" node (generally /dev/tegra_dc_ctrl). Communication through these +device nodes is done with special IOCTLs. There is also an event delivery +mechanism; userspace can wait for and receive events with read() or poll(). + +The tegra_dc_N interface is stateful; each fresh open() of the device node +creates a client instance. In order to prevent multiple processes from +"fighting" for the hardware, only one client instance is permitted to control +certain resources at a time, on a first-come, first-serve basis. + +Overview of tegra_dc_N IOCTLs: +SET_NVMAP_FD: This is used to associate your nvmap client with this dc_ext + client instance. This is necessary so that the kernel can + appropriately enforce permissions on nvmap buffers. + +GET_WINDOW: A dc_ext client must call this on each window that it wishes to + control. This strictly enforces a single dc_ext client on a + window at a time. + +PUT_WINDOW: A dc_ext client may call this to release a window previously + reserved with GET_WINDOW. + +FLIP: This ioctl is used to actually display an nvmap surface using one or + more window. Each time a dc_ext client performs a FLIP, the request is + put on a flip queue and executed asynchronously (the FLIP ioctl will + return immediately). Various parameters are available in the + tegra_dc_ext_flip structure. + A dc_ext client may only use this on windows that it has previously + reserved with a successful GET_WINDOW call. + +GET_CURSOR: This is analogous to GET_WINDOW, but for the hardware cursor + instead of a window. + +PUT_CURSOR: This is analogous to PUT_WINDOW, but for the hardware cursor + instead of a window. + +SET_CURSOR_IMAGE: This is used to change the hardware cursor image. May only + be used by a client who has successfully performed a + GET_CURSOR call. + +SET_CURSOR: This is used to actually place the hardware cursor on the screen. + May only be used by a client who has successfully performed a + GET_CURSOR call. + +SET_CSC: This may be used to set a color space conversion matrix on a window. + A dc_ext client may only use this on windows that it has previously + reserved with a successful GET_WINDOW call. + +GET_STATUS: This is used to retrieve general status about the dc. + +GET_VBLANK_SYNCPT: This is used to retrieve the auto-incrementing vblank + syncpoint for the head associated with this dc. + + +Overview of tegra_dc_ctrl IOCTLs: +GET_NUM_OUTPUTS: This returns the number of available output devices on the + system, which may exceed the number of display controllers. + +GET_OUTPUT_PROPERTIES: This returns data about the given output, such as what + kind of output it is, whether it's currently associated + with a head, etc. + +GET_OUTPUT_EDID: This returns the binary EDID read from the device connected + to the given output, if any. + +SET_EVENT_MASK: A dc_ext client may call this ioctl with a bitmask of events + that it wishes to receive. These events will then be + available to that client on a subsequent read() on the same + file descriptor. diff --git a/Documentation/video4linux/README.tegra b/Documentation/video4linux/README.tegra new file mode 100644 index 000000000000..610eeded2ae9 --- /dev/null +++ b/Documentation/video4linux/README.tegra @@ -0,0 +1,180 @@ +Theory of Operations +==================== + +There are three separate drivers within the V4L2 framework that are interesting +to Tegra-based platforms. They are as follows: + +Image Sensor driver +=================== +This driver communicates only with the image sensor hardware (typically via +I2C transactions), and is intentionally PLATFORM-AGNOSTIC. Existing image +sensor drivers can be found in drivers/media/video. For example, the ov9740 +driver communicates with the Omnivision OV9740 image sensor with built-in ISP. + +Some of the things that this driver is responsible for are: + +Setting up the proper output format of the image sensor, + +Setting up image output extents + +Setting up capture and crop regions + +Camera Host driver +================== +This driver communicates only with the camera controller on a given platform, +and is intentionally IMAGE-SENSOR-AGNOSTIC. Existing camera host drivers +can be found in drivers/media/video, of which tegra_v4l2_camera.c is the +example that is interesting to us. This camera host driver knows how to +program the CSI/VI block on Tegra2 and Tegra3 platforms. + +Some of the things that this driver is responsible for are: + +Setting up the proper input format (image frame data flowing from the image +sensor to the camera host), + +Setting up the proper output format (image frame data flowing from the +camera host to system memory), + +Programming the DMA destination to receive the image frame data, + +Starting and stopping the reception of image frame data. + +Videobuf driver +=============== +This driver is responsible for the allocation and deallocation of buffers that +are used to hold image frame data. Different camera hosts have different +DMA requirements, which makes it necessary to allow for different methods of +buffer allocation. For example, the Tegra2 and Tegra3 camera host cannot +DMA via a scatter-gather list, so the image frame buffers must be physically +contiguous. The videobuf-dma-contig.c videobuf driver can be found in +drivers/media/video, and contains a videobuf implementation that allocates +physically contiguous regions. One can also have a videobuf driver that +uses a different allocator like nvmap. + +The nvhost driver and Syncpts +============================= + +The camera host driver (tegra_v4l2_camera) has a dependency on the nvhost +driver/subsystem in order to make use of syncpts. In other words, the camera +host driver is a client of nvhost. + +A syncpt is essentially an incrementing hardware counter that triggers an +interrupt when a certain number (or threshold) is reached. The interrupt, +however, is hidden from clients of nvhost. Instead, asynchronous completion +notification is done via calling an nvhost routine that goes to sleep, and +wakes up upon completion. + +Tegra has a number of syncpts that serve various purposes. The two syncpts +that are used by the camera host driver are the VI and CSI syncpts. Other +syncpts are used in display, etc. + +A syncpt increments when a certain hardware condition is met. + +The public operations available for a syncpt are: + +nvhost_syncpt_read_ext(syncpt_id) - Read the current syncpt counter value. +nvhost_syncpt_wait_timeout_ext(syncpt_id, threshold, timeout) - Go to sleep + until the syncpt value reaches the threshold, or until the timeout + expires. +nvhost_syncpt_cpu_incr_ext(syncpt_id) - Manually increment a syncpt. + +Syncpts are used in the camera host driver in order to signify the completion +of an operation. The typical usage case can be illustrated by summarizing +the steps that the camera host driver takes in capturing a single frame +(this is called one-shot mode, where we program up each frame transfer +separately): + +0) At the very start, read the current syncpt values and remember them. See + tegra_camera_activate() -> tegra_camera_save_syncpts(), where we read + the current values and store them in pcdev->syncpt_csi and pcdev->syncpt_vi. + +1) Program the camera host registers to prepare to receive frames from the + image sensor using the proper input format. Note that we are at this + point NOT telling the camera host to DMA a frame. That comes later. See + tegra_camera_capture_setup(), where we do a whole bunch of magical + register writes depending on our input format, output format, image extents, + etc. + +2) Increment our remembered copies of the current syncpt values according to + how many syncpt increments we are expecting for the given operation we + want to perform. For capturing a single frame, we are expecting a single + increment on the CSI syncpt when the reception of the frame is complete, and + a single increment on the VI syncpt when the DMA of the frame is complete. + See tegra_camera_capture_start(), where we increment pcdev->syncpt_csi + and pcdev->syncpt_vi. + +3) Program the DMA destination registers, and toggle the bit in + TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND to do the DMA on the next available + frame. See tegra_camera_capture_start() for this. + +4) Call nvhost_syncpt_wait_timeout_ext() to wait on the CSI syncpt threshold. + Remember that we incremented our local syncpt values in step 2. Those + new values become the threshold to wait for. See + tegra_camera_capture_start(). + +5) When the frame finishes its transfer from the image sensor to the camera + host, the CSI syncpt hardware counter will be incremented by hardware. + Since the hardware syncpt value will now match the threshold, our call to + nvhost_syncpt_wait_timeout_ext() in step 4 wakes up. + +6) We now tell the camera host to get ready for the DMA to complete. We do + this by writing again to TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND. See + tegra_camera_capture_stop(). + +7) When the camera host finishes its DMA, we expect the hardware to increment + the VI syncpt. Therefore, we call nvhost_syncpt_wait_timeout_ext() on + the VI syncpt with our new threshold that we got by the incrementing in + step 2. See tegra_camera_capture_stop(). + +8) When the camera host finally finishes its DMA, the VI syncpt hardware + counter increments. Since our VI syncpt threshold is met, the call to + nvhost_syncpt_wait_timeout_ext() wakes up, and we are done. See + tegra_camera_capture_stop(). + +9) To capture the next frame, go back to step 2. The tegra_v4l2_camera driver + calls tegra_camera_capture_setup at the beginning, and then a worker thread + repeatedly calls tegra_camera_capture_start() and + tegra_camera_capture_stop(). See tegra_camera_work() -> + tegra_camera_capture_frame(). + +Note for VIP: Only a single syncpt is used for the VIP path. We use the +continuous VIP VSYNC syncpt to determine the completion of a frame transfer. +In addition, to start and finish the capture of a frame, the +VI_CAMERA_CONTROL register is used. See tegra_camera_capture_start() and +tegra_camera_capture_stop() to see how that register is used for the VIP path. +Essentially, steps 4, 5, and 6 are eliminated, and instead of writing to +TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND or TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, +we write to VI_CAMERA_CONTROL to achieve the same purpose for VIP. + +VIP versus CSI +============== +VI_VI_CORE_CONTROL bits 26:24 (INPUT_TO_CORE_EXT) should be set to 0 +(use INPUT_TO_CORE). + +VI_VI_INPUT_CONTROL bit 1 (VIP_INPUT_ENABLE) should be set to 1 (ENABLED), +bit 26:25 (SYNC_FORMAT) should be set to 1 (ITU656), and bit 27 (FIELD_DETECT) +should be set to 1 (ENABLED). + +VI_H_DOWNSCALE_CONTROL bit 0 (INPUT_H_SIZE_SEL) should be set to 0 (VIP), +and bits 3:2 (INPUT_H_SIZE_SEL_EXT) should be set to 0 (USE INPUT_H_SIZE_SEL). + +Rather than placing the image width and height into VI_CSI_PPA_H_ACTIVE and +VI_CSI_PPA_V_ACTIVE, respectively (or the CSI B counterparts), use +VI_VIP_H_ACTIVE and VI_VIP_V_ACTIVE bits 31:16. Bits 15:0 of VI_VIP_H_ACTIVE +and VI_VIP_V_ACTIVE are the number of clock cycles to wait after receiving +HSYNC or VSYNC before starting. This can be used to adjust the vertical and +horizontal back porches. + +VI_PIN_INPUT_ENABLE should be set to 0x00006fff, which enables input pins +VHS, VVS, and VD11..VD0. + +VI_PIN_INVERSION bits 1 and 2 can be used to invert input pins VHS and VVS, +respectively. + +VI_CONT_SYNCPT_VIP_VSYNC bit 8 (enable VIP_VSYNC) should be set to 1, and +bits 7:0 should hold the index of the syncpt to be used. When this syncpt +is enabled, the syncpt specified by the index will increment by 1 every +time a VSYNC occurs. We use this syncpt to signal frame completion. + +VI_CAMERA_CONTROL bit 0 should be set to 1 to start capturing. Writing a 0 +to this bit is ignored, so to stop capturing, write 1 to bit 2. |