summaryrefslogtreecommitdiff
path: root/arch/arm/Kconfig
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5aa77fe42b0..973dbbb63f11 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1312,6 +1312,15 @@ config ARM_ERRATA_720791
This workaround disables gating the Core clock when the Instruction
side is waiting for a Page Table Walk answer or linefill completion.
+config ARM_ERRATA_752520
+ bool "ARM errata: Faulty arbitration between PLD and Cacheable TLB requests may create a system deadlock"
+ depends on CPU_V7
+ help
+ Under rare circumstances, PLDs may interfere with a Cacheable page table walk,
+ creating a processor deadlock. The erratum can only happen when the Data Cache
+ and MMU are enabled, with the TLB descriptors marked as L1 cacheable,
+ so that Page Table Walks are performed as cache linefills.
+
endmenu
source "arch/arm/common/Kconfig"