diff options
Diffstat (limited to 'arch/arm/boot/dts/armada-370.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-370.dtsi | 65 |
1 files changed, 33 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 209caeb748fa..5c4fa655fc34 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -28,14 +28,15 @@ }; soc { - mpic: interrupt-controller@d0020000 { - reg = <0xd0020a00 0x1d0>, - <0xd0021870 0x58>; + + mpic: interrupt-controller@20000 { + reg = <0x20a00 0x1d0>, + <0x21870 0x58>; }; - system-controller@d0018200 { + system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; - reg = <0xd0018200 0x100>; + reg = <0x18200 0x100>; }; L2: l2-cache { @@ -47,7 +48,7 @@ pinctrl { compatible = "marvell,mv88f6710-pinctrl"; - reg = <0xd0018000 0x38>; + reg = <0x18000 0x38>; sdio_pins1: sdio-pins1 { marvell,pins = "mpp9", "mpp11", "mpp12", @@ -68,9 +69,9 @@ }; }; - gpio0: gpio@d0018100 { + gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; - reg = <0xd0018100 0x40>; + reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; @@ -79,9 +80,9 @@ interrupts = <82>, <83>, <84>, <85>; }; - gpio1: gpio@d0018140 { + gpio1: gpio@18140 { compatible = "marvell,orion-gpio"; - reg = <0xd0018140 0x40>; + reg = <0x18140 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; @@ -90,9 +91,9 @@ interrupts = <87>, <88>, <89>, <90>; }; - gpio2: gpio@d0018180 { + gpio2: gpio@18180 { compatible = "marvell,orion-gpio"; - reg = <0xd0018180 0x40>; + reg = <0x18180 0x40>; ngpios = <2>; gpio-controller; #gpio-cells = <2>; @@ -101,23 +102,23 @@ interrupts = <91>; }; - coreclk: mvebu-sar@d0018230 { + coreclk: mvebu-sar@18230 { compatible = "marvell,armada-370-core-clock"; - reg = <0xd0018230 0x08>; + reg = <0x18230 0x08>; #clock-cells = <1>; }; - gateclk: clock-gating-control@d0018220 { + gateclk: clock-gating-control@18220 { compatible = "marvell,armada-370-gating-clock"; - reg = <0xd0018220 0x4>; + reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; - xor@d0060800 { + xor@60800 { compatible = "marvell,orion-xor"; - reg = <0xd0060800 0x100 - 0xd0060A00 0x100>; + reg = <0x60800 0x100 + 0x60A00 0x100>; status = "okay"; xor00 { @@ -133,10 +134,10 @@ }; }; - xor@d0060900 { + xor@60900 { compatible = "marvell,orion-xor"; - reg = <0xd0060900 0x100 - 0xd0060b00 0x100>; + reg = <0x60900 0x100 + 0x60b00 0x100>; status = "okay"; xor10 { @@ -152,18 +153,18 @@ }; }; - usb@d0050000 { + usb@50000 { clocks = <&coreclk 0>; }; - usb@d0051000 { + usb@51000 { clocks = <&coreclk 0>; }; - thermal@d0018300 { + thermal@18300 { compatible = "marvell,armada370-thermal"; - reg = <0xd0018300 0x4 - 0xd0018304 0x4>; + reg = <0x18300 0x4 + 0x18304 0x4>; status = "okay"; }; @@ -177,18 +178,18 @@ bus-range = <0x00 0xff>; - reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>; + reg = <0x40000 0x2000>, <0x80000 0x2000>; reg-names = "pcie0.0", "pcie1.0"; - ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ pcie@1,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -204,7 +205,7 @@ pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; |