diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-apalis.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 227 |
1 files changed, 212 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index bcf5aaca94bb..ca75b8e4e1d7 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -59,7 +59,7 @@ disp_id = <1>; default_ifmt = "RGB24"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_5>; + pinctrl-0 = <&pinctrl_ipu1_t1>; status = "disabled"; }; @@ -242,7 +242,7 @@ disp_id = <0>; default_ifmt = "RGB565"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_2>; + pinctrl-0 = <&pinctrl_ipu2_t1>; status = "disabled"; }; @@ -254,7 +254,7 @@ &audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_4 &pinctrl_audmux_mclk_1>; + pinctrl-0 = <&pinctrl_audmux_t1 &pinctrl_audmux_mclk_1>; status = "okay"; }; @@ -263,7 +263,7 @@ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio5 25 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_3 &pinctrl_spi_cs1>; + pinctrl-0 = <&pinctrl_ecspi1_t1 &pinctrl_spi_cs1>; status = "disabled"; }; @@ -272,7 +272,7 @@ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio2 26 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_spi_cs2>; + pinctrl-0 = <&pinctrl_ecspi2_t1 &pinctrl_spi_cs2>; status = "disabled"; }; @@ -294,7 +294,7 @@ &flexcan1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_3>; + pinctrl-0 = <&pinctrl_flexcan1_t1>; status = "disabled"; }; @@ -421,6 +421,49 @@ #define PAD_CTRL_NO 0x80000000 &iomuxc { + audmux { + + pinctrl_audmux_t1: audmux-t1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi1 { + + pinctrl_ecspi1_t1: ecspi1grp-t1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 + >; + }; + }; + + ecspi2 { + pinctrl_ecspi2_t1: ecspi2grp-t1 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + >; + }; + }; + + flexcan1 { + + pinctrl_flexcan1_t1: flexcan1grp-t1 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 + >; + }; + }; + imx6q-apalis { pinctrl_apalis_gpio1: apalis_gpio1-1 { fsl,pins = < @@ -526,6 +569,151 @@ >; }; }; + + ipu1 { + + pinctrl_ipu1_t1: ipu1grp-t1 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 /* DE */ + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 /* HSync */ + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 /* VSync */ + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 + >; + }; + }; + + ipu2 { + + pinctrl_ipu2_t1: ipu2grp-t1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xD1 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xD1 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xD1 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xF9 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xF9 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xF9 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xF9 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xF9 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xF9 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xF9 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xF9 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xF9 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xF9 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xF9 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xF9 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xF9 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xF9 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xF9 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xF9 + >; + }; + }; + + uart1 { + + pinctrl_uart1_t1: uart1grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart1_t2: uart1grp-t2 { /* Additional DTR, DSR, DCD */ + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + }; + + uart2 { + + pinctrl_uart2_t1: uart2grp-t1 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_t2: uart2grp-t2 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + }; + + uart4 { + pinctrl_uart4_t1: uart4grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_t1: uart5grp-t1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + pinctrl_uart5_t2: uart5grp-t2 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + >; + }; + }; + + usdhc1 { + + pinctrl_usdhc1_t1: usdhc1grp-t1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 + >; + }; + }; }; &ldb { @@ -573,10 +761,11 @@ status = "okay"; }; +//#define USE_UART_IN_DTE_MODE /* on HW V1.1 */ &uart1 { pinctrl-names = "default"; -#if 0 - pinctrl-0 = <&pinctrl_uart1_3>; +#ifdef USE_UART_IN_DTE_MODE + pinctrl-0 = <&pinctrl_uart1_t1 &pinctrl_uart1_t2>; fsl,dte-mode; fsl,uart-has-rtscts; #else @@ -587,27 +776,35 @@ &uart2 { pinctrl-names = "default"; -#if 0 - pinctrl-0 = <&pinctrl_uart2_5>; +#ifdef USE_UART_IN_DTE_MODE + pinctrl-0 = <&pinctrl_uart2_t2>; fsl,dte-mode; fsl,uart-has-rtscts; #else - pinctrl-0 = <&pinctrl_uart2_4>; + pinctrl-0 = <&pinctrl_uart2_t1>; #endif status = "disabled"; }; &uart4 { pinctrl-names = "default"; +#ifdef USE_UART_IN_DTE_MODE + pinctrl-0 = <&pinctrl_uart4_t1>; + fsl,dte-mode; +#else pinctrl-0 = <&pinctrl_uart4_1>; -/* TODO fsl,dte-mode; */ +#endif status = "disabled"; }; &uart5 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5_1>; -/* TODO fsl,dte-mode; */ +#ifdef USE_UART_IN_DTE_MODE + pinctrl-0 = <&pinctrl_uart5_t2>; + fsl,dte-mode; +#else + pinctrl-0 = <&pinctrl_uart5_t1>; +#endif status = "disabled"; }; @@ -628,7 +825,7 @@ &usdhc1 { label = "MMC1"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_2 &pinctrl_mmc_cd>; + pinctrl-0 = <&pinctrl_usdhc1_t1 &pinctrl_mmc_cd>; cd-gpios = <&gpio4 20 0>; vmmc-supply = <®_3p3v>; bus-width = <8>; |