diff options
Diffstat (limited to 'arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts index 71c4cfb827fe..137c0699a1a8 100644 --- a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts @@ -80,6 +80,22 @@ arm-supply = <&sw1a_reg>; }; +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -237,6 +253,21 @@ pinctrl-0 = <&pinctrl_hog_1>; imx7d-12x12-lpddr3-arm2 { + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 @@ -281,7 +312,6 @@ MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x80000000 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x17059 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x17059 MX7D_PAD_SD1_WP__GPIO5_IO1 0x17059 |