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Diffstat (limited to 'arch/arm/boot/dts/pxa910.dtsi')
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi28
1 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 0247c622f580..0868f6729be1 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -7,7 +7,8 @@
* publishhed by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/marvell,pxa910.h>
/ {
aliases {
@@ -71,6 +72,8 @@
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <27>;
+ clocks = <&soc_clocks PXA910_CLK_UART0>;
+ resets = <&soc_clocks PXA910_CLK_UART0>;
status = "disabled";
};
@@ -78,6 +81,8 @@
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <28>;
+ clocks = <&soc_clocks PXA910_CLK_UART1>;
+ resets = <&soc_clocks PXA910_CLK_UART1>;
status = "disabled";
};
@@ -85,6 +90,8 @@
compatible = "mrvl,mmp-uart";
reg = <0xd4036000 0x1000>;
interrupts = <59>;
+ clocks = <&soc_clocks PXA910_CLK_UART2>;
+ resets = <&soc_clocks PXA910_CLK_UART2>;
status = "disabled";
};
@@ -97,6 +104,8 @@
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
+ clocks = <&soc_clocks PXA910_CLK_GPIO>;
+ resets = <&soc_clocks PXA910_CLK_GPIO>;
interrupt-controller;
#interrupt-cells = <1>;
ranges;
@@ -124,6 +133,8 @@
#size-cells = <0>;
reg = <0xd4011000 0x1000>;
interrupts = <7>;
+ clocks = <&soc_clocks PXA910_CLK_TWSI0>;
+ resets = <&soc_clocks PXA910_CLK_TWSI0>;
mrvl,i2c-fast-mode;
status = "disabled";
};
@@ -134,6 +145,8 @@
#size-cells = <0>;
reg = <0xd4037000 0x1000>;
interrupts = <54>;
+ clocks = <&soc_clocks PXA910_CLK_TWSI1>;
+ resets = <&soc_clocks PXA910_CLK_TWSI1>;
status = "disabled";
};
@@ -142,8 +155,21 @@
reg = <0xd4010000 0x1000>;
interrupts = <5 6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
+ clocks = <&soc_clocks PXA910_CLK_RTC>;
+ resets = <&soc_clocks PXA910_CLK_RTC>;
status = "disabled";
};
};
+
+ soc_clocks: clocks{
+ compatible = "marvell,pxa910-clock";
+ reg = <0xd4050000 0x1000>,
+ <0xd4282800 0x400>,
+ <0xd4015000 0x1000>,
+ <0xd403b000 0x1000>;
+ reg-names = "mpmu", "apmu", "apbc", "apbcp";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};