diff options
Diffstat (limited to 'arch/arm/mach-msm')
68 files changed, 3797 insertions, 1172 deletions
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index dbbcfeb919db..1516896e8d17 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -40,15 +40,29 @@ config ARCH_MSM8X60 bool "MSM8X60" select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ && !MACH_MSM8X60_FFA) + select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX + select MSM_SCM if SMP + +config ARCH_MSM8960 + bool "MSM8960" + select ARCH_MSM_SCORPIONMP + select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) + select ARM_GIC + select CPU_V7 + select MSM_V2_TLMM + select MSM_GPIOMUX + select MSM_SCM if SMP endchoice config MSM_SOC_REV_A bool +config ARCH_MSM_SCORPIONMP + bool config ARCH_MSM_ARM11 bool @@ -120,8 +134,36 @@ config MACH_MSM8X60_FFA help Support for the Qualcomm MSM8x60 FFA eval board. +config MACH_MSM8960_SIM + depends on ARCH_MSM8960 + bool "MSM8960 Simulator" + help + Support for the Qualcomm MSM8960 simulator. + +config MACH_MSM8960_RUMI3 + depends on ARCH_MSM8960 + bool "MSM8960 RUMI3" + help + Support for the Qualcomm MSM8960 RUMI3 emulator. + endmenu +config MSM_IOMMU + bool "MSM IOMMU Support" + depends on ARCH_MSM8X60 || ARCH_MSM8960 + select IOMMU_API + default n + help + Support for the IOMMUs found on certain Qualcomm SOCs. + These IOMMUs allow virtualization of the address space used by most + cores within the multimedia subsystem. + + If unsure, say N here. + +config IOMMU_PGTABLES_L2 + def_bool y + depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n + config MSM_DEBUG_UART int default 1 if MSM_DEBUG_UART1 @@ -162,4 +204,10 @@ config MSM_GPIOMUX config MSM_V2_TLMM bool + +config IOMMU_API + bool + +config MSM_SCM + bool endif diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index b5a7b07a44f5..9519fd28a025 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,33 +1,39 @@ obj-y += io.o idle.o timer.o -ifndef CONFIG_ARCH_MSM8X60 -obj-y += acpuclock-arm11.o -obj-y += dma.o -endif +obj-y += clock.o +obj-$(CONFIG_DEBUG_FS) += clock-debug.o -ifdef CONFIG_MSM_VIC -obj-y += irq-vic.o -else -ifndef CONFIG_ARCH_MSM8X60 -obj-y += irq.o -endif -endif +obj-$(CONFIG_MSM_VIC) += irq-vic.o +obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o + +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o +obj-$(CONFIG_ARCH_MSM7X30) += dma.o +obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o -obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o -obj-$(CONFIG_MSM_PROC_COMM) += clock.o -obj-$(CONFIG_ARCH_QSD8X50) += sirc.o + obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o +obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o + +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o +obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o +obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o -obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o +obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o -ifndef CONFIG_MSM_V2_TLMM +ifdef CONFIG_MSM_V2_TLMM +ifndef CONFIG_ARCH_MSM8960 +# TODO: TLMM Mapping issues need to be resolved +obj-y += gpio-v2.o +endif +else obj-y += gpio.o endif diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 75dabb16c802..18a3c97bc863 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -93,8 +93,6 @@ static void __init halibut_map_io(void) } MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = 0x10000100, .fixup = halibut_fixup, .map_io = halibut_map_io, diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index ef3ebf2f763b..7a9a03eb189c 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -74,8 +74,6 @@ static void __init mahimahi_map_io(void) extern struct sys_timer msm_timer; MACHINE_START(MAHIMAHI, "mahimahi") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = 0x20000100, .fixup = mahimahi_fixup, .map_io = mahimahi_map_io, diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index e7a76eff57d9..c03f269e2e4b 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c @@ -130,9 +130,7 @@ static void __init msm7x2x_map_io(void) } MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -140,9 +138,7 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") MACHINE_END MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -150,9 +146,7 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") MACHINE_END MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -160,9 +154,7 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") MACHINE_END MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 05241df3f9b6..b7a84966b711 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -22,28 +22,67 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/smsc911x.h> +#include <linux/usb/msm_hsusb.h> +#include <linux/clkdev.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/memory.h> #include <asm/setup.h> #include <mach/gpio.h> #include <mach/board.h> -#include <mach/memory.h> #include <mach/msm_iomap.h> #include <mach/dma.h> #include <mach/vreg.h> #include "devices.h" +#include "gpiomux.h" #include "proc_comm.h" extern struct sys_timer msm_timer; +static int hsusb_phy_init_seq[] = { + 0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */ + 0x02, 0x36, /* Disable CDR Auto Reset feature */ + -1 +}; + +static struct msm_otg_platform_data msm_otg_pdata = { + .phy_init_seq = hsusb_phy_init_seq, + .mode = USB_PERIPHERAL, + .otg_control = OTG_PHY_CONTROL, +}; + +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { +#ifdef CONFIG_SERIAL_MSM_CONSOLE + [49] = { /* UART2 RFR */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [50] = { /* UART2 CTS */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [51] = { /* UART2 RX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [52] = { /* UART2 TX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, +#endif +}; + static struct platform_device *devices[] __initdata = { #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) &msm_device_uart2, #endif &msm_device_smd, + &msm_device_otg, + &msm_device_hsusb, + &msm_device_hsusb_host, }; static void __init msm7x30_init_irq(void) @@ -53,6 +92,10 @@ static void __init msm7x30_init_irq(void) static void __init msm7x30_init(void) { + msm_device_otg.dev.platform_data = &msm_otg_pdata; + msm_device_hsusb.dev.parent = &msm_device_otg.dev; + msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; + platform_add_devices(devices, ARRAY_SIZE(devices)); } @@ -63,9 +106,7 @@ static void __init msm7x30_map_io(void) } MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, @@ -73,9 +114,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, @@ -83,9 +122,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c new file mode 100644 index 000000000000..1993721d472e --- /dev/null +++ b/arch/arm/mach-msm/board-msm8960.c @@ -0,0 +1,91 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/clkdev.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/hardware/gic.h> + +#include <mach/board.h> +#include <mach/msm_iomap.h> + +#include "devices.h" + +static void __init msm8960_map_io(void) +{ + msm_map_msm8960_io(); +} + +static void __init msm8960_init_irq(void) +{ + unsigned int i; + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); + + /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ + writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); + + if (machine_is_msm8960_rumi3()) + writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); + + /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet + * as they are configured as level, which does not play nice with + * handle_percpu_irq. + */ + for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { + if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) + set_irq_handler(i, handle_percpu_irq); + } +} + +static struct platform_device *sim_devices[] __initdata = { + &msm8960_device_uart_gsbi2, +}; + +static struct platform_device *rumi3_devices[] __initdata = { + &msm8960_device_uart_gsbi5, +}; + +static void __init msm8960_sim_init(void) +{ + platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); +} + +static void __init msm8960_rumi3_init(void) +{ + platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); +} + +MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") + .map_io = msm8960_map_io, + .init_irq = msm8960_init_irq, + .timer = &msm_timer, + .init_machine = msm8960_sim_init, +MACHINE_END + +MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") + .map_io = msm8960_map_io, + .init_irq = msm8960_init_irq, + .timer = &msm_timer, + .init_machine = msm8960_rumi3_init, +MACHINE_END + diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 7486a681cc71..b3c55f138fce 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -28,12 +28,6 @@ #include <mach/board.h> #include <mach/msm_iomap.h> -void __iomem *gic_cpu_base_addr; - -unsigned long clk_get_max_axi_khz(void) -{ - return 0; -} static void __init msm8x60_map_io(void) { @@ -44,9 +38,8 @@ static void __init msm8x60_init_irq(void) { unsigned int i; - gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START); - gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; - gic_cpu_init(0, MSM_QGIC_CPU_BASE); + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index ed2af4ad97ed..7f568611547e 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,6 +20,9 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/usb/msm_hsusb.h> +#include <linux/err.h> +#include <linux/clkdev.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -30,6 +33,8 @@ #include <mach/irqs.h> #include <mach/sirc.h> #include <mach/gpio.h> +#include <mach/vreg.h> +#include <mach/mmc.h> #include "devices.h" @@ -42,7 +47,7 @@ static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; * at run-time: they vary from board to board, and the true * configuration won't be known until boot. */ -static struct resource smc91x_resources[] __initdata = { +static struct resource smc91x_resources[] = { [0] = { .flags = IORESOURCE_MEM, }, @@ -51,7 +56,7 @@ static struct resource smc91x_resources[] __initdata = { }, }; -static struct platform_device smc91x_device __initdata = { +static struct platform_device smc91x_device = { .name = "smc91x", .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), @@ -74,11 +79,101 @@ static int __init msm_init_smc91x(void) } module_init(msm_init_smc91x); +static int hsusb_phy_init_seq[] = { + 0x08, 0x31, /* Increase HS Driver Amplitude */ + 0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */ + -1 +}; + +static struct msm_otg_platform_data msm_otg_pdata = { + .phy_init_seq = hsusb_phy_init_seq, + .mode = USB_PERIPHERAL, + .otg_control = OTG_PHY_CONTROL, +}; + static struct platform_device *devices[] __initdata = { &msm_device_uart3, &msm_device_smd, + &msm_device_otg, + &msm_device_hsusb, + &msm_device_hsusb_host, }; +static struct msm_mmc_gpio sdc1_gpio_cfg[] = { + {51, "sdc1_dat_3"}, + {52, "sdc1_dat_2"}, + {53, "sdc1_dat_1"}, + {54, "sdc1_dat_0"}, + {55, "sdc1_cmd"}, + {56, "sdc1_clk"} +}; + +static struct vreg *vreg_mmc; +static unsigned long vreg_sts; + +static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd) +{ + int rc = 0; + struct platform_device *pdev; + + pdev = container_of(dv, struct platform_device, dev); + + if (vdd == 0) { + if (!vreg_sts) + return 0; + + clear_bit(pdev->id, &vreg_sts); + + if (!vreg_sts) { + rc = vreg_disable(vreg_mmc); + if (rc) + pr_err("vreg_mmc disable failed for slot " + "%d: %d\n", pdev->id, rc); + } + return 0; + } + + if (!vreg_sts) { + rc = vreg_set_level(vreg_mmc, 2900); + if (rc) + pr_err("vreg_mmc set level failed for slot %d: %d\n", + pdev->id, rc); + rc = vreg_enable(vreg_mmc); + if (rc) + pr_err("vreg_mmc enable failed for slot %d: %d\n", + pdev->id, rc); + } + set_bit(pdev->id, &vreg_sts); + return 0; +} + +static struct msm_mmc_gpio_data sdc1_gpio = { + .gpio = sdc1_gpio_cfg, + .size = ARRAY_SIZE(sdc1_gpio_cfg), +}; + +static struct msm_mmc_platform_data qsd8x50_sdc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, + .translate_vdd = msm_sdcc_setup_power, + .gpio_data = &sdc1_gpio, +}; + +static void __init qsd8x50_init_mmc(void) +{ + if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa()) + vreg_mmc = vreg_get(NULL, "gp6"); + else + vreg_mmc = vreg_get(NULL, "gp5"); + + if (IS_ERR(vreg_mmc)) { + pr_err("vreg get for vreg_mmc failed (%ld)\n", + PTR_ERR(vreg_mmc)); + return; + } + + msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0); +} + static void __init qsd8x50_map_io(void) { msm_map_qsd8x50_io(); @@ -93,13 +188,15 @@ static void __init qsd8x50_init_irq(void) static void __init qsd8x50_init(void) { + msm_device_otg.dev.platform_data = &msm_otg_pdata; + msm_device_hsusb.dev.parent = &msm_device_otg.dev; + msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; platform_add_devices(devices, ARRAY_SIZE(devices)); + qsd8x50_init_mmc(); } MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, @@ -107,9 +204,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 8919ffb17196..68f930f07d77 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -105,9 +105,7 @@ static void __init sapphire_map_io(void) MACHINE_START(SAPPHIRE, "sapphire") /* Maintainer: Brian Swetland <swetland@google.com> */ -#ifdef CONFIG_MSM_DEBUG_UART -#endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .fixup = sapphire_fixup, .map_io = sapphire_map_io, .init_irq = sapphire_init_irq, diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index c50f3afc3134..31117a4499c4 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -72,6 +72,11 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, return 0; } +static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return TROUT_GPIO_TO_INT(offset + chip->base); +} + #define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \ { \ .chip = { \ @@ -80,6 +85,7 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, .direction_output = msm_gpiolib_direction_output, \ .get = msm_gpiolib_get, \ .set = msm_gpiolib_set, \ + .to_irq = trout_gpio_to_irq, \ .base = base_gpio, \ .ngpio = 8, \ }, \ @@ -105,52 +111,52 @@ static struct msm_gpio_chip msm_gpio_banks[] = { TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0), }; -static void trout_gpio_irq_ack(unsigned int irq) +static void trout_gpio_irq_ack(struct irq_data *d) { - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); int reg = TROUT_BANK_TO_STAT_REG(bank); - /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", irq);*/ + /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/ writeb(mask, TROUT_CPLD_BASE + reg); } -static void trout_gpio_irq_mask(unsigned int irq) +static void trout_gpio_irq_mask(struct irq_data *d) { unsigned long flags; uint8_t reg_val; - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); int reg = TROUT_BANK_TO_MASK_REG(bank); local_irq_save(flags); reg_val = trout_int_mask[bank] |= mask; /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n", - irq, bank, reg_val);*/ + d->irq, bank, reg_val);*/ writeb(reg_val, TROUT_CPLD_BASE + reg); local_irq_restore(flags); } -static void trout_gpio_irq_unmask(unsigned int irq) +static void trout_gpio_irq_unmask(struct irq_data *d) { unsigned long flags; uint8_t reg_val; - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); int reg = TROUT_BANK_TO_MASK_REG(bank); local_irq_save(flags); reg_val = trout_int_mask[bank] &= ~mask; /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n", - irq, bank, reg_val);*/ + d->irq, bank, reg_val);*/ writeb(reg_val, TROUT_CPLD_BASE + reg); local_irq_restore(flags); } -int trout_gpio_irq_set_wake(unsigned int irq, unsigned int on) +int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned long flags; - int bank = TROUT_INT_TO_BANK(irq); - uint8_t mask = TROUT_INT_TO_MASK(irq); + int bank = TROUT_INT_TO_BANK(d->irq); + uint8_t mask = TROUT_INT_TO_MASK(d->irq); local_irq_save(flags); if(on) @@ -190,15 +196,15 @@ static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } int_base += TROUT_INT_BANK0_COUNT; } - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static struct irq_chip trout_gpio_irq_chip = { - .name = "troutgpio", - .ack = trout_gpio_irq_ack, - .mask = trout_gpio_irq_mask, - .unmask = trout_gpio_irq_unmask, - .set_wake = trout_gpio_irq_set_wake, + .name = "troutgpio", + .irq_ack = trout_gpio_irq_ack, + .irq_mask = trout_gpio_irq_mask, + .irq_unmask = trout_gpio_irq_unmask, + .irq_set_wake = trout_gpio_irq_set_wake, }; /* diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c new file mode 100644 index 000000000000..729bb49a44ca --- /dev/null +++ b/arch/arm/mach-msm/board-trout-panel.c @@ -0,0 +1,297 @@ +/* linux/arch/arm/mach-msm/board-trout-mddi.c +** Author: Brian Swetland <swetland@google.com> +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/leds.h> +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/mach-types.h> + +#include <mach/msm_fb.h> +#include <mach/vreg.h> + +#include "board-trout.h" +#include "proc_comm.h" +#include "devices.h" + +#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255 + +#define MDDI_CLIENT_CORE_BASE 0x108000 +#define LCD_CONTROL_BLOCK_BASE 0x110000 +#define SPI_BLOCK_BASE 0x120000 +#define I2C_BLOCK_BASE 0x130000 +#define PWM_BLOCK_BASE 0x140000 +#define GPIO_BLOCK_BASE 0x150000 +#define SYSTEM_BLOCK1_BASE 0x160000 +#define SYSTEM_BLOCK2_BASE 0x170000 + + +#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) +#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C) +#define PWM0OFF (PWM_BLOCK_BASE|0x1C) + +#define V_VDDE2E_VDD2_GPIO 0 +#define MDDI_RST_N 82 + +#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) +#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) +#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) +#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) +#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) +#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) +#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) +#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) +#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) +#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) +#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) +#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) +#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) +#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) +#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) +#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) +#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) +#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) +#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) +#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) +#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) +#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) + +#define SRST (LCD_CONTROL_BLOCK_BASE|0x00) +#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) +#define START (LCD_CONTROL_BLOCK_BASE|0x08) +#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) +#define CMN (LCD_CONTROL_BLOCK_BASE|0x10) +#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) +#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) +#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) +#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) +#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) +#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) +#define PXL (LCD_CONTROL_BLOCK_BASE|0x30) +#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) +#define HSW (LCD_CONTROL_BLOCK_BASE|0x38) +#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) +#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) +#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) +#define VSW (LCD_CONTROL_BLOCK_BASE|0x48) +#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) +#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) +#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) +#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) +#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) +#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) +#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) +#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) +#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) +#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) +#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) +#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) +#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) +#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) +#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) +#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) +#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) + +#define SSICTL (SPI_BLOCK_BASE|0x00) +#define SSITIME (SPI_BLOCK_BASE|0x04) +#define SSITX (SPI_BLOCK_BASE|0x08) +#define SSIRX (SPI_BLOCK_BASE|0x0C) +#define SSIINTC (SPI_BLOCK_BASE|0x10) +#define SSIINTS (SPI_BLOCK_BASE|0x14) +#define SSIDBG1 (SPI_BLOCK_BASE|0x18) +#define SSIDBG2 (SPI_BLOCK_BASE|0x1C) +#define SSIID (SPI_BLOCK_BASE|0x20) + +#define WKREQ (SYSTEM_BLOCK1_BASE|0x00) +#define CLKENB (SYSTEM_BLOCK1_BASE|0x04) +#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) +#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) +#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) + +#define GPIODATA (GPIO_BLOCK_BASE|0x00) +#define GPIODIR (GPIO_BLOCK_BASE|0x04) +#define GPIOIS (GPIO_BLOCK_BASE|0x08) +#define GPIOIBE (GPIO_BLOCK_BASE|0x0C) +#define GPIOIEV (GPIO_BLOCK_BASE|0x10) +#define GPIOIE (GPIO_BLOCK_BASE|0x14) +#define GPIORIS (GPIO_BLOCK_BASE|0x18) +#define GPIOMIS (GPIO_BLOCK_BASE|0x1C) +#define GPIOIC (GPIO_BLOCK_BASE|0x20) +#define GPIOOMS (GPIO_BLOCK_BASE|0x24) +#define GPIOPC (GPIO_BLOCK_BASE|0x28) +#define GPIOID (GPIO_BLOCK_BASE|0x30) + +#define SPI_WRITE(reg, val) \ + { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \ + { 0, 5 }, + +#define SPI_WRITE1(reg) \ + { SSITX, (reg) & 0xff }, \ + { 0, 5 }, + +struct mddi_table { + uint32_t reg; + uint32_t value; +}; +static struct mddi_table mddi_toshiba_init_table[] = { + { DPSET0, 0x09e90046 }, + { DPSET1, 0x00000118 }, + { DPSUS, 0x00000000 }, + { DPRUN, 0x00000001 }, + { 1, 14 }, /* msleep 14 */ + { SYSCKENA, 0x00000001 }, + { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */ + + { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */ + { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */ + { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */ + { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */ + { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */ + + { GPIOIBE, 0x000003FF }, + { GPIOIS, 0x00000000 }, + { GPIOIC, 0x000003FF }, + { GPIOIE, 0x00000000 }, + + { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ + { 1, 1 }, /* msleep 1 */ + { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ + { DRAMPWR, 0x00000001 }, /* eDRAM power */ +}; + +#define GPIOSEL_VWAKEINT (1U << 0) +#define INTMASK_VWAKEOUT (1U << 0) + + +static struct clk *gp_clk; +static int trout_new_backlight = 1; +static struct vreg *vreg_mddi_1v5; +static struct vreg *vreg_lcm_2v85; + +static void trout_process_mddi_table(struct msm_mddi_client_data *client_data, + struct mddi_table *table, size_t count) +{ + int i; + for (i = 0; i < count; i++) { + uint32_t reg = table[i].reg; + uint32_t value = table[i].value; + + if (reg == 0) + udelay(value); + else if (reg == 1) + msleep(value); + else + client_data->remote_write(client_data, value, reg); + } +} + +static int trout_mddi_toshiba_client_init( + struct msm_mddi_bridge_platform_data *bridge_data, + struct msm_mddi_client_data *client_data) +{ + int panel_id; + + client_data->auto_hibernate(client_data, 0); + trout_process_mddi_table(client_data, mddi_toshiba_init_table, + ARRAY_SIZE(mddi_toshiba_init_table)); + client_data->auto_hibernate(client_data, 1); + panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3; + if (panel_id > 1) { + printk(KERN_WARNING "unknown panel id at mddi_enable\n"); + return -1; + } + return 0; +} + +static int trout_mddi_toshiba_client_uninit( + struct msm_mddi_bridge_platform_data *bridge_data, + struct msm_mddi_client_data *client_data) +{ + return 0; +} + +static struct resource resources_msm_fb[] = { + { + .start = MSM_FB_BASE, + .end = MSM_FB_BASE + MSM_FB_SIZE, + .flags = IORESOURCE_MEM, + }, +}; + +struct msm_mddi_bridge_platform_data toshiba_client_data = { + .init = trout_mddi_toshiba_client_init, + .uninit = trout_mddi_toshiba_client_uninit, + .fb_data = { + .xres = 320, + .yres = 480, + .width = 45, + .height = 67, + .output_format = 0, + }, +}; + +static struct msm_mddi_platform_data mddi_pdata = { + .clk_rate = 122880000, + .fb_resource = resources_msm_fb, + .num_clients = 1, + .client_platform_data = { + { + .product_id = (0xd263 << 16 | 0), + .name = "mddi_c_d263_0000", + .id = 0, + .client_data = &toshiba_client_data, + .clk_rate = 0, + }, + }, +}; + +int __init trout_init_panel(void) +{ + int rc; + + if (!machine_is_trout()) + return 0; + vreg_mddi_1v5 = vreg_get(0, "gp2"); + if (IS_ERR(vreg_mddi_1v5)) + return PTR_ERR(vreg_mddi_1v5); + vreg_lcm_2v85 = vreg_get(0, "gp4"); + if (IS_ERR(vreg_lcm_2v85)) + return PTR_ERR(vreg_lcm_2v85); + + trout_new_backlight = system_rev >= 5; + if (trout_new_backlight) { + uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT, + GPIO_NO_PULL, GPIO_8MA); + msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); + } else { + uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT, + GPIO_NO_PULL, GPIO_8MA); + msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); + + gp_clk = clk_get(NULL, "gp_clk"); + if (IS_ERR(gp_clk)) { + printk(KERN_ERR "trout_init_panel: could not get gp" + "clock\n"); + gp_clk = NULL; + } + rc = clk_set_rate(gp_clk, 19200000); + if (rc) + printk(KERN_ERR "trout_init_panel: set clock rate " + "failed\n"); + } + + rc = platform_device_register(&msm_device_mdp); + if (rc) + return rc; + msm_device_mddi0.dev.platform_data = &mddi_pdata; + return platform_device_register(&msm_device_mddi0); +} + +device_initcall(trout_init_panel); diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 73f146066542..814386772c66 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -17,6 +17,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/clkdev.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -92,8 +93,6 @@ static void __init trout_map_io(void) } MACHINE_START(TROUT, "HTC Dream") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = 0x10000100, .fixup = trout_fixup, .map_io = trout_map_io, diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h index e16f72f32829..14104453688b 100644 --- a/arch/arm/mach-msm/clock-7x30.h +++ b/arch/arm/mach-msm/clock-7x30.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H @@ -147,22 +130,26 @@ void pll_disable(uint32_t pll); extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = L_7X30_##clk_id, \ - .remote_id = P_##clk_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - .dbg_name = #clk_id, \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .id = L_7X30_##clk_id, \ + .remote_id = P_##clk_id, \ + .flags = clk_flags, \ + .dbg_name = #clk_id, \ + }, \ } #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = L_7X30_##l_id, \ - .remote_id = P_##r_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - .dbg_name = #l_id, \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .id = L_7X30_##l_id, \ + .remote_id = P_##r_id, \ + .flags = clk_flags, \ + .dbg_name = #l_id, \ + .ops = &clk_ops_pcom, \ + }, \ } #endif - diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c new file mode 100644 index 000000000000..4886404d42f5 --- /dev/null +++ b/arch/arm/mach-msm/clock-debug.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/ctype.h> +#include <linux/debugfs.h> +#include <linux/clk.h> +#include "clock.h" + +static int clock_debug_rate_set(void *data, u64 val) +{ + struct clk *clock = data; + int ret; + + /* Only increases to max rate will succeed, but that's actually good + * for debugging purposes so we don't check for error. */ + if (clock->flags & CLK_MAX) + clk_set_max_rate(clock, val); + if (clock->flags & CLK_MIN) + ret = clk_set_min_rate(clock, val); + else + ret = clk_set_rate(clock, val); + if (ret != 0) + printk(KERN_ERR "clk_set%s_rate failed (%d)\n", + (clock->flags & CLK_MIN) ? "_min" : "", ret); + return ret; +} + +static int clock_debug_rate_get(void *data, u64 *val) +{ + struct clk *clock = data; + *val = clk_get_rate(clock); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, + clock_debug_rate_set, "%llu\n"); + +static int clock_debug_enable_set(void *data, u64 val) +{ + struct clk *clock = data; + int rc = 0; + + if (val) + rc = clock->ops->enable(clock->id); + else + clock->ops->disable(clock->id); + + return rc; +} + +static int clock_debug_enable_get(void *data, u64 *val) +{ + struct clk *clock = data; + + *val = clock->ops->is_enabled(clock->id); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, + clock_debug_enable_set, "%llu\n"); + +static int clock_debug_local_get(void *data, u64 *val) +{ + struct clk *clock = data; + + *val = clock->ops->is_local(clock->id); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, + NULL, "%llu\n"); + +static struct dentry *debugfs_base; + +int __init clock_debug_init(void) +{ + debugfs_base = debugfs_create_dir("clk", NULL); + if (!debugfs_base) + return -ENOMEM; + return 0; +} + +int __init clock_debug_add(struct clk *clock) +{ + char temp[50], *ptr; + struct dentry *clk_dir; + + if (!debugfs_base) + return -ENOMEM; + + strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); + for (ptr = temp; *ptr; ptr++) + *ptr = tolower(*ptr); + + clk_dir = debugfs_create_dir(temp, debugfs_base); + if (!clk_dir) + return -ENOMEM; + + if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir, + clock, &clock_rate_fops)) + goto error; + + if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir, + clock, &clock_enable_fops)) + goto error; + + if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock, + &clock_local_fops)) + goto error; + return 0; +error: + debugfs_remove_recursive(clk_dir); + return -ENOMEM; +} diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index a3b45627eb4a..63b711311086 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -20,6 +20,7 @@ #include "proc_comm.h" #include "clock.h" +#include "clock-pcom.h" /* * glue for the proc_comm interface @@ -116,6 +117,11 @@ long pc_clk_round_rate(unsigned id, unsigned rate) return rate; } +static bool pc_clk_is_local(unsigned id) +{ + return false; +} + struct clk_ops clk_ops_pcom = { .enable = pc_clk_enable, .disable = pc_clk_disable, @@ -128,4 +134,5 @@ struct clk_ops clk_ops_pcom = { .get_rate = pc_clk_get_rate, .is_enabled = pc_clk_is_enabled, .round_rate = pc_clk_round_rate, + .is_local = pc_clk_is_local, }; diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h index 17d027b23501..974d0032f3a3 100644 --- a/arch/arm/mach-msm/clock-pcom.h +++ b/arch/arm/mach-msm/clock-pcom.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H @@ -132,8 +115,10 @@ #define P_CSI1_P_CLK 97 #define P_GSBI_CLK 98 #define P_GSBI_P_CLK 99 +#define P_CE_CLK 100 /* Crypto engine */ +#define P_CODEC_SSBI_CLK 101 -#define P_NR_CLKS 100 +#define P_NR_CLKS 102 struct clk_ops; extern struct clk_ops clk_ops_pcom; @@ -141,13 +126,15 @@ extern struct clk_ops clk_ops_pcom; int pc_clk_reset(unsigned id, enum clk_reset_action action); #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = P_##clk_id, \ - .remote_id = P_##clk_id, \ - .ops = &clk_ops_pcom, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - .dbg_name = #clk_id, \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .id = P_##clk_id, \ + .remote_id = P_##clk_id, \ + .ops = &clk_ops_pcom, \ + .flags = clk_flags, \ + .dbg_name = #clk_id, \ + }, \ } #endif diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index c57210f4f06a..22a537669624 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -15,74 +15,32 @@ */ #include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> #include <linux/list.h> #include <linux/err.h> -#include <linux/clk.h> #include <linux/spinlock.h> -#include <linux/debugfs.h> -#include <linux/ctype.h> #include <linux/pm_qos_params.h> -#include <mach/clk.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/string.h> +#include <linux/module.h> +#include <linux/clkdev.h> #include "clock.h" -#include "proc_comm.h" -#include "clock-7x30.h" static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); static LIST_HEAD(clocks); -struct clk *msm_clocks; -unsigned msm_num_clocks; - -/* - * Bitmap of enabled clocks, excluding ACPU which is always - * enabled - */ -static DECLARE_BITMAP(clock_map_enabled, NR_CLKS); -static DEFINE_SPINLOCK(clock_map_lock); /* * Standard clock functions defined in include/linux/clk.h */ -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *clk; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(clk, &clocks, list) - if (!strcmp(id, clk->name) && clk->dev == dev) - goto found_it; - - list_for_each_entry(clk, &clocks, list) - if (!strcmp(id, clk->name) && clk->dev == NULL) - goto found_it; - - clk = ERR_PTR(-ENOENT); -found_it: - mutex_unlock(&clocks_mutex); - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; spin_lock_irqsave(&clocks_lock, flags); clk->count++; - if (clk->count == 1) { + if (clk->count == 1) clk->ops->enable(clk->id); - spin_lock(&clock_map_lock); - clock_map_enabled[BIT_WORD(clk->id)] |= BIT_MASK(clk->id); - spin_unlock(&clock_map_lock); - } spin_unlock_irqrestore(&clocks_lock, flags); return 0; } @@ -94,20 +52,14 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); BUG_ON(clk->count == 0); clk->count--; - if (clk->count == 0) { + if (clk->count == 0) clk->ops->disable(clk->id); - spin_lock(&clock_map_lock); - clock_map_enabled[BIT_WORD(clk->id)] &= ~BIT_MASK(clk->id); - spin_unlock(&clock_map_lock); - } spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); int clk_reset(struct clk *clk, enum clk_reset_action action) { - if (!clk->ops->reset) - clk->ops->reset = &pc_clk_reset; return clk->ops->reset(clk->remote_id, action); } EXPORT_SYMBOL(clk_reset); @@ -120,6 +72,21 @@ EXPORT_SYMBOL(clk_get_rate); int clk_set_rate(struct clk *clk, unsigned long rate) { + int ret; + if (clk->flags & CLKFLAG_MAX) { + ret = clk->ops->set_max_rate(clk->id, rate); + if (ret) + return ret; + } + if (clk->flags & CLKFLAG_MIN) { + ret = clk->ops->set_min_rate(clk->id, rate); + if (ret) + return ret; + } + + if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN) + return ret; + return clk->ops->set_rate(clk->id, rate); } EXPORT_SYMBOL(clk_set_rate); @@ -169,25 +136,14 @@ EXPORT_SYMBOL(clk_set_flags); */ static struct clk *ebi1_clk; -static void __init set_clock_ops(struct clk *clk) -{ - if (!clk->ops) { - clk->ops = &clk_ops_pcom; - clk->id = clk->remote_id; - } -} - -void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) +void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks) { unsigned n; - spin_lock_init(&clocks_lock); mutex_lock(&clocks_mutex); - msm_clocks = clock_tbl; - msm_num_clocks = num_clocks; - for (n = 0; n < msm_num_clocks; n++) { - set_clock_ops(&msm_clocks[n]); - list_add_tail(&msm_clocks[n].list, &clocks); + for (n = 0; n < num_clocks; n++) { + clkdev_add(&clock_tbl[n]); + list_add_tail(&clock_tbl[n].clk->list, &clocks); } mutex_unlock(&clocks_mutex); @@ -196,115 +152,6 @@ void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) } -#if defined(CONFIG_DEBUG_FS) -static struct clk *msm_clock_get_nth(unsigned index) -{ - if (index < msm_num_clocks) - return msm_clocks + index; - else - return 0; -} - -static int clock_debug_rate_set(void *data, u64 val) -{ - struct clk *clock = data; - int ret; - - /* Only increases to max rate will succeed, but that's actually good - * for debugging purposes. So we don't check for error. */ - if (clock->flags & CLK_MAX) - clk_set_max_rate(clock, val); - if (clock->flags & CLK_MIN) - ret = clk_set_min_rate(clock, val); - else - ret = clk_set_rate(clock, val); - if (ret != 0) - printk(KERN_ERR "clk_set%s_rate failed (%d)\n", - (clock->flags & CLK_MIN) ? "_min" : "", ret); - return ret; -} - -static int clock_debug_rate_get(void *data, u64 *val) -{ - struct clk *clock = data; - *val = clk_get_rate(clock); - return 0; -} - -static int clock_debug_enable_set(void *data, u64 val) -{ - struct clk *clock = data; - int rc = 0; - - if (val) - rc = clock->ops->enable(clock->id); - else - clock->ops->disable(clock->id); - - return rc; -} - -static int clock_debug_enable_get(void *data, u64 *val) -{ - struct clk *clock = data; - - *val = clock->ops->is_enabled(clock->id); - - return 0; -} - -static int clock_debug_local_get(void *data, u64 *val) -{ - struct clk *clock = data; - - *val = clock->ops != &clk_ops_pcom; - - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, - clock_debug_rate_set, "%llu\n"); -DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, - clock_debug_enable_set, "%llu\n"); -DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, - NULL, "%llu\n"); - -static int __init clock_debug_init(void) -{ - struct dentry *dent_rate, *dent_enable, *dent_local; - struct clk *clock; - unsigned n = 0; - char temp[50], *ptr; - - dent_rate = debugfs_create_dir("clk_rate", 0); - if (IS_ERR(dent_rate)) - return PTR_ERR(dent_rate); - - dent_enable = debugfs_create_dir("clk_enable", 0); - if (IS_ERR(dent_enable)) - return PTR_ERR(dent_enable); - - dent_local = debugfs_create_dir("clk_local", NULL); - if (IS_ERR(dent_local)) - return PTR_ERR(dent_local); - - while ((clock = msm_clock_get_nth(n++)) != 0) { - strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); - for (ptr = temp; *ptr; ptr++) - *ptr = tolower(*ptr); - debugfs_create_file(temp, 0644, dent_rate, - clock, &clock_rate_fops); - debugfs_create_file(temp, 0644, dent_enable, - clock, &clock_enable_fops); - debugfs_create_file(temp, S_IRUGO, dent_local, - clock, &clock_local_fops); - } - return 0; -} - -device_initcall(clock_debug_init); -#endif - /* The bootloader and/or AMSS may have left various clocks enabled. * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have * not been explicitly enabled by a clk_enable() call. @@ -315,8 +162,10 @@ static int __init clock_late_init(void) struct clk *clk; unsigned count = 0; + clock_debug_init(); mutex_lock(&clocks_mutex); list_for_each_entry(clk, &clocks, list) { + clock_debug_add(clk); if (clk->flags & CLKFLAG_AUTO_OFF) { spin_lock_irqsave(&clocks_lock, flags); if (!clk->count) { diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index c270b552ed13..2c007f606d29 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -17,12 +17,10 @@ #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H #define __ARCH_ARM_MACH_MSM_CLOCK_H +#include <linux/init.h> #include <linux/list.h> #include <mach/clk.h> -#include "clock-pcom.h" -#include "clock-7x30.h" - #define CLKFLAG_INVERT 0x00000001 #define CLKFLAG_NOINVERT 0x00000002 #define CLKFLAG_NONEST 0x00000004 @@ -45,6 +43,7 @@ struct clk_ops { unsigned (*get_rate)(unsigned id); unsigned (*is_enabled)(unsigned id); long (*round_rate)(unsigned id, unsigned rate); + bool (*is_local)(unsigned id); }; struct clk { @@ -52,58 +51,22 @@ struct clk { uint32_t remote_id; uint32_t count; uint32_t flags; - const char *name; struct clk_ops *ops; const char *dbg_name; struct list_head list; - struct device *dev; }; -#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) -#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) -#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) - -#ifdef CONFIG_DEBUG_FS -#define CLOCK_DBG_NAME(x) .dbg_name = x, -#else -#define CLOCK_DBG_NAME(x) -#endif - -#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = clk_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - CLOCK_DBG_NAME(#clk_id) \ - } - #define OFF CLKFLAG_AUTO_OFF #define CLK_MIN CLKFLAG_MIN #define CLK_MAX CLKFLAG_MAX #define CLK_MINMAX (CLK_MIN | CLK_MAX) -#define NR_CLKS P_NR_CLKS - -enum { - PLL_0 = 0, - PLL_1, - PLL_2, - PLL_3, - PLL_4, - PLL_5, - PLL_6, - NUM_PLL -}; - -enum clkvote_client { - CLKVOTE_ACPUCLK = 0, - CLKVOTE_PMQOS, - CLKVOTE_MAX, -}; - -int msm_clock_require_tcxo(unsigned long *reason, int nbits); -int msm_clock_get_name(uint32_t id, char *name, uint32_t size); -int ebi1_clk_set_min_rate(enum clkvote_client client, unsigned long rate); -unsigned long clk_get_max_axi_khz(void); +#ifdef CONFIG_DEBUG_FS +int __init clock_debug_init(void); +int __init clock_debug_add(struct clk *clock); +#else +static inline int __init clock_debug_init(void) { return 0; } +static inline int __init clock_debug_add(struct clk *clock) { return 0; } #endif +#endif diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-iommu.c index 89b9d4437e92..24030d0da6e3 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-iommu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,15 +18,13 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/bootmem.h> - -#include <mach/msm_iomap-8x60.h> -#include <mach/irqs-8x60.h> +#include <mach/irqs.h> #include <mach/iommu.h> static struct resource msm_iommu_jpegd_resources[] = { { - .start = MSM_IOMMU_JPEGD_PHYS, - .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1, + .start = 0x07300000, + .end = 0x07300000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -46,8 +44,8 @@ static struct resource msm_iommu_jpegd_resources[] = { static struct resource msm_iommu_vpe_resources[] = { { - .start = MSM_IOMMU_VPE_PHYS, - .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1, + .start = 0x07400000, + .end = 0x07400000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -67,8 +65,8 @@ static struct resource msm_iommu_vpe_resources[] = { static struct resource msm_iommu_mdp0_resources[] = { { - .start = MSM_IOMMU_MDP0_PHYS, - .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1, + .start = 0x07500000, + .end = 0x07500000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -88,8 +86,8 @@ static struct resource msm_iommu_mdp0_resources[] = { static struct resource msm_iommu_mdp1_resources[] = { { - .start = MSM_IOMMU_MDP1_PHYS, - .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1, + .start = 0x07600000, + .end = 0x07600000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -109,8 +107,8 @@ static struct resource msm_iommu_mdp1_resources[] = { static struct resource msm_iommu_rot_resources[] = { { - .start = MSM_IOMMU_ROT_PHYS, - .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1, + .start = 0x07700000, + .end = 0x07700000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -130,8 +128,8 @@ static struct resource msm_iommu_rot_resources[] = { static struct resource msm_iommu_ijpeg_resources[] = { { - .start = MSM_IOMMU_IJPEG_PHYS, - .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1, + .start = 0x07800000, + .end = 0x07800000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -151,8 +149,8 @@ static struct resource msm_iommu_ijpeg_resources[] = { static struct resource msm_iommu_vfe_resources[] = { { - .start = MSM_IOMMU_VFE_PHYS, - .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1, + .start = 0x07900000, + .end = 0x07900000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -172,8 +170,8 @@ static struct resource msm_iommu_vfe_resources[] = { static struct resource msm_iommu_vcodec_a_resources[] = { { - .start = MSM_IOMMU_VCODEC_A_PHYS, - .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1, + .start = 0x07A00000, + .end = 0x07A00000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -193,8 +191,8 @@ static struct resource msm_iommu_vcodec_a_resources[] = { static struct resource msm_iommu_vcodec_b_resources[] = { { - .start = MSM_IOMMU_VCODEC_B_PHYS, - .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1, + .start = 0x07B00000, + .end = 0x07B00000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -214,8 +212,8 @@ static struct resource msm_iommu_vcodec_b_resources[] = { static struct resource msm_iommu_gfx3d_resources[] = { { - .start = MSM_IOMMU_GFX3D_PHYS, - .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1, + .start = 0x07C00000, + .end = 0x07C00000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -235,8 +233,8 @@ static struct resource msm_iommu_gfx3d_resources[] = { static struct resource msm_iommu_gfx2d0_resources[] = { { - .start = MSM_IOMMU_GFX2D0_PHYS, - .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1, + .start = 0x07D00000, + .end = 0x07D00000 + SZ_1M - 1, .name = "physbase", .flags = IORESOURCE_MEM, }, @@ -254,60 +252,93 @@ static struct resource msm_iommu_gfx2d0_resources[] = { }, }; +static struct resource msm_iommu_gfx2d1_resources[] = { + { + .start = 0x07E00000, + .end = 0x07E00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device msm_root_iommu_dev = { .name = "msm_iommu", .id = -1, }; -static struct msm_iommu_dev jpegd_smmu = { +static struct msm_iommu_dev jpegd_iommu = { .name = "jpegd", - .clk_rate = -1 + .ncb = 2, }; -static struct msm_iommu_dev vpe_smmu = { - .name = "vpe" +static struct msm_iommu_dev vpe_iommu = { + .name = "vpe", + .ncb = 2, }; -static struct msm_iommu_dev mdp0_smmu = { - .name = "mdp0" +static struct msm_iommu_dev mdp0_iommu = { + .name = "mdp0", + .ncb = 2, }; -static struct msm_iommu_dev mdp1_smmu = { - .name = "mdp1" +static struct msm_iommu_dev mdp1_iommu = { + .name = "mdp1", + .ncb = 2, }; -static struct msm_iommu_dev rot_smmu = { - .name = "rot" +static struct msm_iommu_dev rot_iommu = { + .name = "rot", + .ncb = 2, }; -static struct msm_iommu_dev ijpeg_smmu = { - .name = "ijpeg" +static struct msm_iommu_dev ijpeg_iommu = { + .name = "ijpeg", + .ncb = 2, }; -static struct msm_iommu_dev vfe_smmu = { +static struct msm_iommu_dev vfe_iommu = { .name = "vfe", - .clk_rate = -1 + .ncb = 2, }; -static struct msm_iommu_dev vcodec_a_smmu = { - .name = "vcodec_a" +static struct msm_iommu_dev vcodec_a_iommu = { + .name = "vcodec_a", + .ncb = 2, }; -static struct msm_iommu_dev vcodec_b_smmu = { - .name = "vcodec_b" +static struct msm_iommu_dev vcodec_b_iommu = { + .name = "vcodec_b", + .ncb = 2, }; -static struct msm_iommu_dev gfx3d_smmu = { +static struct msm_iommu_dev gfx3d_iommu = { .name = "gfx3d", - .clk_rate = 27000000 + .ncb = 3, }; -static struct msm_iommu_dev gfx2d0_smmu = { +static struct msm_iommu_dev gfx2d0_iommu = { .name = "gfx2d0", - .clk_rate = 27000000 + .ncb = 2, +}; + +static struct msm_iommu_dev gfx2d1_iommu = { + .name = "gfx2d1", + .ncb = 2, }; -static struct platform_device msm_device_smmu_jpegd = { +static struct platform_device msm_device_iommu_jpegd = { .name = "msm_iommu", .id = 0, .dev = { @@ -317,7 +348,7 @@ static struct platform_device msm_device_smmu_jpegd = { .resource = msm_iommu_jpegd_resources, }; -static struct platform_device msm_device_smmu_vpe = { +static struct platform_device msm_device_iommu_vpe = { .name = "msm_iommu", .id = 1, .dev = { @@ -327,7 +358,7 @@ static struct platform_device msm_device_smmu_vpe = { .resource = msm_iommu_vpe_resources, }; -static struct platform_device msm_device_smmu_mdp0 = { +static struct platform_device msm_device_iommu_mdp0 = { .name = "msm_iommu", .id = 2, .dev = { @@ -337,7 +368,7 @@ static struct platform_device msm_device_smmu_mdp0 = { .resource = msm_iommu_mdp0_resources, }; -static struct platform_device msm_device_smmu_mdp1 = { +static struct platform_device msm_device_iommu_mdp1 = { .name = "msm_iommu", .id = 3, .dev = { @@ -347,7 +378,7 @@ static struct platform_device msm_device_smmu_mdp1 = { .resource = msm_iommu_mdp1_resources, }; -static struct platform_device msm_device_smmu_rot = { +static struct platform_device msm_device_iommu_rot = { .name = "msm_iommu", .id = 4, .dev = { @@ -357,7 +388,7 @@ static struct platform_device msm_device_smmu_rot = { .resource = msm_iommu_rot_resources, }; -static struct platform_device msm_device_smmu_ijpeg = { +static struct platform_device msm_device_iommu_ijpeg = { .name = "msm_iommu", .id = 5, .dev = { @@ -367,7 +398,7 @@ static struct platform_device msm_device_smmu_ijpeg = { .resource = msm_iommu_ijpeg_resources, }; -static struct platform_device msm_device_smmu_vfe = { +static struct platform_device msm_device_iommu_vfe = { .name = "msm_iommu", .id = 6, .dev = { @@ -377,7 +408,7 @@ static struct platform_device msm_device_smmu_vfe = { .resource = msm_iommu_vfe_resources, }; -static struct platform_device msm_device_smmu_vcodec_a = { +static struct platform_device msm_device_iommu_vcodec_a = { .name = "msm_iommu", .id = 7, .dev = { @@ -387,7 +418,7 @@ static struct platform_device msm_device_smmu_vcodec_a = { .resource = msm_iommu_vcodec_a_resources, }; -static struct platform_device msm_device_smmu_vcodec_b = { +static struct platform_device msm_device_iommu_vcodec_b = { .name = "msm_iommu", .id = 8, .dev = { @@ -397,7 +428,7 @@ static struct platform_device msm_device_smmu_vcodec_b = { .resource = msm_iommu_vcodec_b_resources, }; -static struct platform_device msm_device_smmu_gfx3d = { +static struct platform_device msm_device_iommu_gfx3d = { .name = "msm_iommu", .id = 9, .dev = { @@ -407,7 +438,7 @@ static struct platform_device msm_device_smmu_gfx3d = { .resource = msm_iommu_gfx3d_resources, }; -static struct platform_device msm_device_smmu_gfx2d0 = { +static struct platform_device msm_device_iommu_gfx2d0 = { .name = "msm_iommu", .id = 10, .dev = { @@ -417,6 +448,16 @@ static struct platform_device msm_device_smmu_gfx2d0 = { .resource = msm_iommu_gfx2d0_resources, }; +struct platform_device msm_device_iommu_gfx2d1 = { + .name = "msm_iommu", + .id = 11, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), + .resource = msm_iommu_gfx2d1_resources, +}; + static struct msm_iommu_ctx_dev jpegd_src_ctx = { .name = "jpegd_src", .num = 0, @@ -519,41 +560,36 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} }; -static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = { - .name = "gfx3d_rbpa", +static struct msm_iommu_ctx_dev gfx3d_user_ctx = { + .name = "gfx3d_user", .num = 0, - .mids = {-1} + .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} }; -static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = { - .name = "gfx3d_cpvgttc", +static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { + .name = "gfx3d_priv", .num = 1, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = { - .name = "gfx3d_smmu", - .num = 2, - .mids = {8, 9, 10, 11, 12, -1} + .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, -1} }; -static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { - .name = "gfx2d0_pixv1_smmu", +static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { + .name = "gfx2d0_2d0", .num = 0, - .mids = {0, 3, 4, -1} + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; -static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = { - .name = "gfx2d0_texv3_smmu", - .num = 1, - .mids = {1, 6, 7, -1} +static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { + .name = "gfx2d1_2d1", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; static struct platform_device msm_device_jpegd_src_ctx = { .name = "msm_iommu_ctx", .id = 0, .dev = { - .parent = &msm_device_smmu_jpegd.dev, + .parent = &msm_device_iommu_jpegd.dev, }, }; @@ -561,7 +597,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = { .name = "msm_iommu_ctx", .id = 1, .dev = { - .parent = &msm_device_smmu_jpegd.dev, + .parent = &msm_device_iommu_jpegd.dev, }, }; @@ -569,7 +605,7 @@ static struct platform_device msm_device_vpe_src_ctx = { .name = "msm_iommu_ctx", .id = 2, .dev = { - .parent = &msm_device_smmu_vpe.dev, + .parent = &msm_device_iommu_vpe.dev, }, }; @@ -577,7 +613,7 @@ static struct platform_device msm_device_vpe_dst_ctx = { .name = "msm_iommu_ctx", .id = 3, .dev = { - .parent = &msm_device_smmu_vpe.dev, + .parent = &msm_device_iommu_vpe.dev, }, }; @@ -585,7 +621,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = { .name = "msm_iommu_ctx", .id = 4, .dev = { - .parent = &msm_device_smmu_mdp0.dev, + .parent = &msm_device_iommu_mdp0.dev, }, }; @@ -593,7 +629,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = { .name = "msm_iommu_ctx", .id = 5, .dev = { - .parent = &msm_device_smmu_mdp0.dev, + .parent = &msm_device_iommu_mdp0.dev, }, }; @@ -601,7 +637,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = { .name = "msm_iommu_ctx", .id = 6, .dev = { - .parent = &msm_device_smmu_mdp1.dev, + .parent = &msm_device_iommu_mdp1.dev, }, }; @@ -609,7 +645,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = { .name = "msm_iommu_ctx", .id = 7, .dev = { - .parent = &msm_device_smmu_mdp1.dev, + .parent = &msm_device_iommu_mdp1.dev, }, }; @@ -617,7 +653,7 @@ static struct platform_device msm_device_rot_src_ctx = { .name = "msm_iommu_ctx", .id = 8, .dev = { - .parent = &msm_device_smmu_rot.dev, + .parent = &msm_device_iommu_rot.dev, }, }; @@ -625,7 +661,7 @@ static struct platform_device msm_device_rot_dst_ctx = { .name = "msm_iommu_ctx", .id = 9, .dev = { - .parent = &msm_device_smmu_rot.dev, + .parent = &msm_device_iommu_rot.dev, }, }; @@ -633,7 +669,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = { .name = "msm_iommu_ctx", .id = 10, .dev = { - .parent = &msm_device_smmu_ijpeg.dev, + .parent = &msm_device_iommu_ijpeg.dev, }, }; @@ -641,7 +677,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = { .name = "msm_iommu_ctx", .id = 11, .dev = { - .parent = &msm_device_smmu_ijpeg.dev, + .parent = &msm_device_iommu_ijpeg.dev, }, }; @@ -649,7 +685,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = { .name = "msm_iommu_ctx", .id = 12, .dev = { - .parent = &msm_device_smmu_vfe.dev, + .parent = &msm_device_iommu_vfe.dev, }, }; @@ -657,7 +693,7 @@ static struct platform_device msm_device_vfe_misc_ctx = { .name = "msm_iommu_ctx", .id = 13, .dev = { - .parent = &msm_device_smmu_vfe.dev, + .parent = &msm_device_iommu_vfe.dev, }, }; @@ -665,7 +701,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = { .name = "msm_iommu_ctx", .id = 14, .dev = { - .parent = &msm_device_smmu_vcodec_a.dev, + .parent = &msm_device_iommu_vcodec_a.dev, }, }; @@ -673,7 +709,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = { .name = "msm_iommu_ctx", .id = 15, .dev = { - .parent = &msm_device_smmu_vcodec_a.dev, + .parent = &msm_device_iommu_vcodec_a.dev, }, }; @@ -681,76 +717,70 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = { .name = "msm_iommu_ctx", .id = 16, .dev = { - .parent = &msm_device_smmu_vcodec_b.dev, + .parent = &msm_device_iommu_vcodec_b.dev, }, }; -static struct platform_device msm_device_gfx3d_rbpa_ctx = { +static struct platform_device msm_device_gfx3d_user_ctx = { .name = "msm_iommu_ctx", .id = 17, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; -static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { +static struct platform_device msm_device_gfx3d_priv_ctx = { .name = "msm_iommu_ctx", .id = 18, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; -static struct platform_device msm_device_gfx3d_smmu_ctx = { +static struct platform_device msm_device_gfx2d0_2d0_ctx = { .name = "msm_iommu_ctx", .id = 19, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx2d0.dev, }, }; -static struct platform_device msm_device_gfx2d0_pixv1_ctx = { +static struct platform_device msm_device_gfx2d1_2d1_ctx = { .name = "msm_iommu_ctx", .id = 20, .dev = { - .parent = &msm_device_smmu_gfx2d0.dev, - }, -}; - -static struct platform_device msm_device_gfx2d0_texv3_ctx = { - .name = "msm_iommu_ctx", - .id = 21, - .dev = { - .parent = &msm_device_smmu_gfx2d0.dev, + .parent = &msm_device_iommu_gfx2d1.dev, }, }; static struct platform_device *msm_iommu_devs[] = { - &msm_device_smmu_jpegd, - &msm_device_smmu_vpe, - &msm_device_smmu_mdp0, - &msm_device_smmu_mdp1, - &msm_device_smmu_rot, - &msm_device_smmu_ijpeg, - &msm_device_smmu_vfe, - &msm_device_smmu_vcodec_a, - &msm_device_smmu_vcodec_b, - &msm_device_smmu_gfx3d, - &msm_device_smmu_gfx2d0, + &msm_device_iommu_jpegd, + &msm_device_iommu_vpe, + &msm_device_iommu_mdp0, + &msm_device_iommu_mdp1, + &msm_device_iommu_rot, + &msm_device_iommu_ijpeg, + &msm_device_iommu_vfe, + &msm_device_iommu_vcodec_a, + &msm_device_iommu_vcodec_b, + &msm_device_iommu_gfx3d, + &msm_device_iommu_gfx2d0, + &msm_device_iommu_gfx2d1, }; static struct msm_iommu_dev *msm_iommu_data[] = { - &jpegd_smmu, - &vpe_smmu, - &mdp0_smmu, - &mdp1_smmu, - &rot_smmu, - &ijpeg_smmu, - &vfe_smmu, - &vcodec_a_smmu, - &vcodec_b_smmu, - &gfx3d_smmu, - &gfx2d0_smmu, + &jpegd_iommu, + &vpe_iommu, + &mdp0_iommu, + &mdp1_iommu, + &rot_iommu, + &ijpeg_iommu, + &vfe_iommu, + &vcodec_a_iommu, + &vcodec_b_iommu, + &gfx3d_iommu, + &gfx2d0_iommu, + &gfx2d1_iommu, }; static struct platform_device *msm_iommu_ctx_devs[] = { @@ -771,11 +801,10 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_vcodec_a_stream_ctx, &msm_device_vcodec_a_mm1_ctx, &msm_device_vcodec_b_mm2_ctx, - &msm_device_gfx3d_rbpa_ctx, - &msm_device_gfx3d_cpvgttc_ctx, - &msm_device_gfx3d_smmu_ctx, - &msm_device_gfx2d0_pixv1_ctx, - &msm_device_gfx2d0_texv3_ctx, + &msm_device_gfx3d_user_ctx, + &msm_device_gfx3d_priv_ctx, + &msm_device_gfx2d0_2d0_ctx, + &msm_device_gfx2d1_2d1_ctx, }; static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { @@ -796,14 +825,13 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &vcodec_a_stream_ctx, &vcodec_a_mm1_ctx, &vcodec_b_mm2_ctx, - &gfx3d_rbpa_ctx, - &gfx3d_cpvgttc_ctx, - &gfx3d_smmu_ctx, - &gfx2d0_pixv1_ctx, - &gfx2d0_texv3_ctx, + &gfx3d_user_ctx, + &gfx3d_priv_ctx, + &gfx2d0_2d0_ctx, + &gfx2d1_2d1_ctx, }; -static int msm8x60_iommu_init(void) +static int __init msm8x60_iommu_init(void) { int ret, i; @@ -826,7 +854,7 @@ static int msm8x60_iommu_init(void) ret = platform_device_register(msm_iommu_devs[i]); if (ret != 0) { - pr_err("platform_device_register smmu failed, " + pr_err("platform_device_register iommu failed, " "i = %d\n", i); goto failure_unwind; } @@ -837,7 +865,7 @@ static int msm8x60_iommu_init(void) msm_iommu_ctx_data[i], sizeof(*msm_iommu_ctx_devs[i])); if (ret != 0) { - pr_err("platform_device_add_data smmu failed, " + pr_err("platform_device_add_data iommu failed, " "i = %d\n", i); goto failure_unwind2; } @@ -863,7 +891,7 @@ failure: return ret; } -static void msm8x60_iommu_exit(void) +static void __exit msm8x60_iommu_exit(void) { int i; diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index 4e8c0bcdc92d..c4f5e26feb4d 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> +#include <linux/clkdev.h> #include <mach/irqs.h> #include <mach/msm_iomap.h> @@ -24,8 +25,8 @@ #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> - #include "clock.h" +#include "clock-pcom.h" #include <mach/mmc.h> static struct resource resources_uart1[] = { @@ -38,6 +39,7 @@ static struct resource resources_uart1[] = { .start = MSM_UART1_PHYS, .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -51,6 +53,7 @@ static struct resource resources_uart2[] = { .start = MSM_UART2_PHYS, .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -64,6 +67,7 @@ static struct resource resources_uart3[] = { .start = MSM_UART3_PHYS, .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -347,7 +351,74 @@ int __init msm_add_sdcc(unsigned int controller, return platform_device_register(pdev); } -struct clk msm_clocks_7x01a[] = { +static struct resource resources_mddi0[] = { + { + .start = MSM_PMDH_PHYS, + .end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MDDI_PRI, + .end = INT_MDDI_PRI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource resources_mddi1[] = { + { + .start = MSM_EMDH_PHYS, + .end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MDDI_EXT, + .end = INT_MDDI_EXT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_mddi0 = { + .name = "msm_mddi", + .id = 0, + .num_resources = ARRAY_SIZE(resources_mddi0), + .resource = resources_mddi0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_mddi1 = { + .name = "msm_mddi", + .id = 1, + .num_resources = ARRAY_SIZE(resources_mddi1), + .resource = resources_mddi1, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource resources_mdp[] = { + { + .start = MSM_MDP_PHYS, + .end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1, + .name = "mdp", + .flags = IORESOURCE_MEM + }, + { + .start = INT_MDP, + .end = INT_MDP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_mdp = { + .name = "msm_mdp", + .id = 0, + .num_resources = ARRAY_SIZE(resources_mdp), + .resource = resources_mdp, +}; + +struct clk_lookup msm_clocks_7x01a[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), @@ -356,7 +427,7 @@ struct clk msm_clocks_7x01a[] = { CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF), CLK_PCOM("gp_clk", GP_CLK, NULL, 0), CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF), - CLK_PCOM("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0), + CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0), CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), @@ -364,27 +435,27 @@ struct clk msm_clocks_7x01a[] = { CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), - CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF ), + CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), - CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), - CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), - CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), - CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), - CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), - CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), - CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), - CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF), - CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), - CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("uart_clk", UART1_CLK, "msm_serial.0", OFF), + CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), + CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), - CLK_PCOM("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF), - CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, &msm_device_hsusb.dev, OFF), + CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF), + CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF), CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ), CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 7fcf2e3b7698..09b4f1403824 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -17,6 +17,7 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/clkdev.h> #include <mach/irqs.h> #include <mach/msm_iomap.h> #include <mach/dma.h> @@ -28,6 +29,7 @@ #include <asm/mach/flash.h> #include "clock-pcom.h" +#include "clock-7x30.h" #include <mach/mmc.h> @@ -41,6 +43,7 @@ static struct resource resources_uart2[] = { .start = MSM_UART2_PHYS, .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -56,11 +59,84 @@ struct platform_device msm_device_smd = { .id = -1, }; -struct clk msm_clocks_7x30[] = { +static struct resource resources_otg[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_otg = { + .name = "msm_otg", + .id = -1, + .num_resources = ARRAY_SIZE(resources_otg), + .resource = resources_otg, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource resources_hsusb[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_hsusb = { + .name = "msm_hsusb", + .id = -1, + .num_resources = ARRAY_SIZE(resources_hsusb), + .resource = resources_hsusb, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static u64 dma_mask = 0xffffffffULL; +static struct resource resources_hsusb_host[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_hsusb_host = { + .name = "msm_hsusb_host", + .id = -1, + .num_resources = ARRAY_SIZE(resources_hsusb_host), + .resource = resources_hsusb_host, + .dev = { + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, + }, +}; + +struct clk_lookup msm_clocks_7x30[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), + CLK_PCOM("ce_clk", CE_CLK, NULL, 0), + CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), @@ -106,7 +182,8 @@ struct clk msm_clocks_7x30[] = { CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), + CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), + CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c new file mode 100644 index 000000000000..d9e1f26475de --- /dev/null +++ b/arch/arm/mach-msm/devices-msm8960.c @@ -0,0 +1,85 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <linux/dma-mapping.h> +#include <mach/irqs-8960.h> +#include <mach/board.h> + +#include "devices.h" + +#define MSM_GSBI2_PHYS 0x16100000 +#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) + +#define MSM_GSBI5_PHYS 0x16400000 +#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000) + +static struct resource resources_uart_gsbi2[] = { + { + .start = GSBI2_UARTDM_IRQ, + .end = GSBI2_UARTDM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART2DM_PHYS, + .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, + .name = "uart_resource", + .flags = IORESOURCE_MEM, + }, + { + .start = MSM_GSBI2_PHYS, + .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1, + .name = "gsbi_resource", + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm8960_device_uart_gsbi2 = { + .name = "msm_serial", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart_gsbi2), + .resource = resources_uart_gsbi2, +}; + +static struct resource resources_uart_gsbi5[] = { + { + .start = GSBI5_UARTDM_IRQ, + .end = GSBI5_UARTDM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART5DM_PHYS, + .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1, + .name = "uart_resource", + .flags = IORESOURCE_MEM, + }, + { + .start = MSM_GSBI5_PHYS, + .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1, + .name = "gsbi_resource", + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm8960_device_uart_gsbi5 = { + .name = "msm_serial", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart_gsbi5), + .resource = resources_uart_gsbi5, +}; diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index 6fe67c5d1ae0..12d8deb78d9c 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,8 +15,9 @@ #include <linux/kernel.h> #include <linux/platform_device.h> - +#include <linux/clkdev.h> #include <linux/dma-mapping.h> + #include <mach/irqs.h> #include <mach/msm_iomap.h> #include <mach/dma.h> @@ -27,6 +28,7 @@ #include <asm/mach/flash.h> #include <mach/mmc.h> +#include "clock-pcom.h" static struct resource resources_uart3[] = { { @@ -38,6 +40,7 @@ static struct resource resources_uart3[] = { .start = MSM_UART3_PHYS, .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -53,14 +56,275 @@ struct platform_device msm_device_smd = { .id = -1, }; -struct clk msm_clocks_8x50[] = { +static struct resource resources_otg[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_otg = { + .name = "msm_otg", + .id = -1, + .num_resources = ARRAY_SIZE(resources_otg), + .resource = resources_otg, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource resources_hsusb[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_hsusb = { + .name = "msm_hsusb", + .id = -1, + .num_resources = ARRAY_SIZE(resources_hsusb), + .resource = resources_hsusb, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static u64 dma_mask = 0xffffffffULL; +static struct resource resources_hsusb_host[] = { + { + .start = MSM_HSUSB_PHYS, + .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_HS, + .end = INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_hsusb_host = { + .name = "msm_hsusb_host", + .id = -1, + .num_resources = ARRAY_SIZE(resources_hsusb_host), + .resource = resources_hsusb_host, + .dev = { + .dma_mask = &dma_mask, + .coherent_dma_mask = 0xffffffffULL, + }, +}; + +static struct resource resources_sdc1[] = { + { + .start = MSM_SDC1_PHYS, + .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC1_0, + .end = INT_SDC1_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC1_1, + .end = INT_SDC1_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc2[] = { + { + .start = MSM_SDC2_PHYS, + .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC2_0, + .end = INT_SDC2_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC2_1, + .end = INT_SDC2_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc3[] = { + { + .start = MSM_SDC3_PHYS, + .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC3_0, + .end = INT_SDC3_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC3_1, + .end = INT_SDC3_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc4[] = { + { + .start = MSM_SDC4_PHYS, + .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC4_0, + .end = INT_SDC4_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC4_1, + .end = INT_SDC4_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device msm_device_sdc1 = { + .name = "msm_sdcc", + .id = 1, + .num_resources = ARRAY_SIZE(resources_sdc1), + .resource = resources_sdc1, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc2 = { + .name = "msm_sdcc", + .id = 2, + .num_resources = ARRAY_SIZE(resources_sdc2), + .resource = resources_sdc2, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc3 = { + .name = "msm_sdcc", + .id = 3, + .num_resources = ARRAY_SIZE(resources_sdc3), + .resource = resources_sdc3, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc4 = { + .name = "msm_sdcc", + .id = 4, + .num_resources = ARRAY_SIZE(resources_sdc4), + .resource = resources_sdc4, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct platform_device *msm_sdcc_devices[] __initdata = { + &msm_device_sdc1, + &msm_device_sdc2, + &msm_device_sdc3, + &msm_device_sdc4, +}; + +int __init msm_add_sdcc(unsigned int controller, + struct msm_mmc_platform_data *plat, + unsigned int stat_irq, unsigned long stat_irq_flags) +{ + struct platform_device *pdev; + struct resource *res; + + if (controller < 1 || controller > 4) + return -EINVAL; + + pdev = msm_sdcc_devices[controller-1]; + pdev->dev.platform_data = plat; + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); + if (!res) + return -EINVAL; + else if (stat_irq) { + res->start = res->end = stat_irq; + res->flags &= ~IORESOURCE_DISABLED; + res->flags |= stat_irq_flags; + } + + return platform_device_register(pdev); +} + +struct clk_lookup msm_clocks_8x50[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("ce_clk", CE_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), CLK_PCOM("gp_clk", GP_CLK, NULL, 0), CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), + CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0), CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), @@ -73,12 +337,24 @@ struct clk msm_clocks_8x50[] = { CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF), + CLK_PCOM("uart_clk", UART2_CLK, NULL, 0), + CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), + CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF), + CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 568443e76423..9545c196c6e8 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -16,18 +16,25 @@ #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H #define __ARCH_ARM_MACH_MSM_DEVICES_H +#include <linux/clkdev.h> + #include "clock.h" extern struct platform_device msm_device_uart1; extern struct platform_device msm_device_uart2; extern struct platform_device msm_device_uart3; +extern struct platform_device msm8960_device_uart_gsbi2; +extern struct platform_device msm8960_device_uart_gsbi5; + extern struct platform_device msm_device_sdc1; extern struct platform_device msm_device_sdc2; extern struct platform_device msm_device_sdc3; extern struct platform_device msm_device_sdc4; extern struct platform_device msm_device_hsusb; +extern struct platform_device msm_device_otg; +extern struct platform_device msm_device_hsusb_host; extern struct platform_device msm_device_i2c; @@ -35,13 +42,17 @@ extern struct platform_device msm_device_smd; extern struct platform_device msm_device_nand; -extern struct clk msm_clocks_7x01a[]; +extern struct platform_device msm_device_mddi0; +extern struct platform_device msm_device_mddi1; +extern struct platform_device msm_device_mdp; + +extern struct clk_lookup msm_clocks_7x01a[]; extern unsigned msm_num_clocks_7x01a; -extern struct clk msm_clocks_7x30[]; +extern struct clk_lookup msm_clocks_7x30[]; extern unsigned msm_num_clocks_7x30; -extern struct clk msm_clocks_8x50[]; +extern struct clk_lookup msm_clocks_8x50[]; extern unsigned msm_num_clocks_8x50; #endif diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c new file mode 100644 index 000000000000..0de19ec74e34 --- /dev/null +++ b/arch/arm/mach-msm/gpio-v2.c @@ -0,0 +1,426 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/bitmap.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <mach/msm_iomap.h> +#include "gpiomux.h" + +/* Bits of interest in the GPIO_IN_OUT register. + */ +enum { + GPIO_IN = 0, + GPIO_OUT = 1 +}; + +/* Bits of interest in the GPIO_INTR_STATUS register. + */ +enum { + INTR_STATUS = 0, +}; + +/* Bits of interest in the GPIO_CFG register. + */ +enum { + GPIO_OE = 9, +}; + +/* Bits of interest in the GPIO_INTR_CFG register. + * When a GPIO triggers, two separate decisions are made, controlled + * by two separate flags. + * + * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS + * register for that GPIO will be updated to reflect the triggering of that + * gpio. If this bit is 0, this register will not be updated. + * - Second, INTR_ENABLE controls whether an interrupt is triggered. + * + * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt + * can be triggered but the status register will not reflect it. + */ +enum { + INTR_ENABLE = 0, + INTR_POL_CTL = 1, + INTR_DECT_CTL = 2, + INTR_RAW_STATUS_EN = 3, +}; + +/* Codes of interest in GPIO_INTR_CFG_SU. + */ +enum { + TARGET_PROC_SCORPION = 4, + TARGET_PROC_NONE = 7, +}; + + +#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) +#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) +#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) +#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) +#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) + +/** + * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure + * + * @enabled_irqs: a bitmap used to optimize the summary-irq handler. By + * keeping track of which gpios are unmasked as irq sources, we avoid + * having to do readl calls on hundreds of iomapped registers each time + * the summary interrupt fires in order to locate the active interrupts. + * + * @wake_irqs: a bitmap for tracking which interrupt lines are enabled + * as wakeup sources. When the device is suspended, interrupts which are + * not wakeup sources are disabled. + * + * @dual_edge_irqs: a bitmap used to track which irqs are configured + * as dual-edge, as this is not supported by the hardware and requires + * some special handling in the driver. + */ +struct msm_gpio_dev { + struct gpio_chip gpio_chip; + DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); + DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); + DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); +}; + +static DEFINE_SPINLOCK(tlmm_lock); + +static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) +{ + return container_of(chip, struct msm_gpio_dev, gpio_chip); +} + +static inline void set_gpio_bits(unsigned n, void __iomem *reg) +{ + writel(readl(reg) | n, reg); +} + +static inline void clear_gpio_bits(unsigned n, void __iomem *reg) +{ + writel(readl(reg) & ~n, reg); +} + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset)); +} + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int val) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + msm_gpio_set(chip, offset, val); + set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + return 0; +} + +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return msm_gpiomux_get(chip->base + offset); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + msm_gpiomux_put(chip->base + offset); +} + +static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return MSM_GPIO_TO_INT(chip->base + offset); +} + +static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) +{ + return irq - MSM_GPIO_TO_INT(chip->base); +} + +static struct msm_gpio_dev msm_gpio = { + .gpio_chip = { + .base = 0, + .ngpio = NR_GPIO_IRQS, + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .to_irq = msm_gpio_to_irq, + .request = msm_gpio_request, + .free = msm_gpio_free, + }, +}; + +/* For dual-edge interrupts in software, since the hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c. + */ +static void msm_gpio_update_dual_edge_pos(unsigned gpio) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + + do { + val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); + if (val) + clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); + else + set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); + val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); + intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); + if (intstat || val == val2) + return; + } while (loop_limit-- > 0); + pr_err("dual-edge irq failed to stabilize, " + "interrupts dropped. %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_ack(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + + writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); + if (test_bit(gpio, msm_gpio.dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(gpio); +} + +static void msm_gpio_irq_mask(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); + clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); + __clear_bit(gpio, msm_gpio.enabled_irqs); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); +} + +static void msm_gpio_irq_unmask(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + __set_bit(gpio, msm_gpio.enabled_irqs); + set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); + writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); +} + +static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + uint32_t bits; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + + bits = readl(GPIO_INTR_CFG(gpio)); + + if (flow_type & IRQ_TYPE_EDGE_BOTH) { + bits |= BIT(INTR_DECT_CTL); + irq_desc[irq].handle_irq = handle_edge_irq; + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + __set_bit(gpio, msm_gpio.dual_edge_irqs); + else + __clear_bit(gpio, msm_gpio.dual_edge_irqs); + } else { + bits &= ~BIT(INTR_DECT_CTL); + irq_desc[irq].handle_irq = handle_level_irq; + __clear_bit(gpio, msm_gpio.dual_edge_irqs); + } + + if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) + bits |= BIT(INTR_POL_CTL); + else + bits &= ~BIT(INTR_POL_CTL); + + writel(bits, GPIO_INTR_CFG(gpio)); + + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + msm_gpio_update_dual_edge_pos(gpio); + + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + + return 0; +} + +/* + * When the summary IRQ is raised, any number of GPIO lines may be high. + * It is the job of the summary handler to find all those GPIO lines + * which have been set as summary IRQ lines and which are triggered, + * and to call their interrupt handlers. + */ +static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long i; + + for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); + i < NR_GPIO_IRQS; + i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { + if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) + generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, + i)); + } + desc->chip->ack(irq); +} + +static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + + if (on) { + if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) + set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); + set_bit(gpio, msm_gpio.wake_irqs); + } else { + clear_bit(gpio, msm_gpio.wake_irqs); + if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) + set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); + } + + return 0; +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .mask = msm_gpio_irq_mask, + .unmask = msm_gpio_irq_unmask, + .ack = msm_gpio_irq_ack, + .set_type = msm_gpio_irq_set_type, + .set_wake = msm_gpio_irq_set_wake, +}; + +static int __devinit msm_gpio_probe(struct platform_device *dev) +{ + int i, irq, ret; + + bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); + bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); + bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); + msm_gpio.gpio_chip.label = dev->name; + ret = gpiochip_add(&msm_gpio.gpio_chip); + if (ret < 0) + return ret; + + for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { + irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); + set_irq_chip(irq, &msm_gpio_irq_chip); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, + msm_summary_irq_handler); + return 0; +} + +static int __devexit msm_gpio_remove(struct platform_device *dev) +{ + int ret = gpiochip_remove(&msm_gpio.gpio_chip); + + if (ret < 0) + return ret; + + set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); + + return 0; +} + +static struct platform_driver msm_gpio_driver = { + .probe = msm_gpio_probe, + .remove = __devexit_p(msm_gpio_remove), + .driver = { + .name = "msmgpio", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device msm_device_gpio = { + .name = "msmgpio", + .id = -1, +}; + +static int __init msm_gpio_init(void) +{ + int rc; + + rc = platform_driver_register(&msm_gpio_driver); + if (!rc) { + rc = platform_device_register(&msm_device_gpio); + if (rc) + platform_driver_unregister(&msm_gpio_driver); + } + + return rc; +} + +static void __exit msm_gpio_exit(void) +{ + platform_device_unregister(&msm_device_gpio); + platform_driver_unregister(&msm_gpio_driver); +} + +postcore_initcall(msm_gpio_init); +module_exit(msm_gpio_exit); + +MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>"); +MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:msmgpio"); diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 33051b509e88..176af9dcb8ee 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -225,21 +225,21 @@ struct msm_gpio_chip msm_gpio_chips[] = { #endif }; -static void msm_gpio_irq_ack(unsigned int irq) +static void msm_gpio_irq_ack(struct irq_data *d) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); spin_lock_irqsave(&msm_chip->lock, irq_flags); msm_gpio_clear_detect_status(msm_chip, - irq - gpio_to_irq(msm_chip->chip.base)); + d->irq - gpio_to_irq(msm_chip->chip.base)); spin_unlock_irqrestore(&msm_chip->lock, irq_flags); } -static void msm_gpio_irq_mask(unsigned int irq) +static void msm_gpio_irq_mask(struct irq_data *d) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); spin_lock_irqsave(&msm_chip->lock, irq_flags); /* level triggered interrupts are also latched */ @@ -250,11 +250,11 @@ static void msm_gpio_irq_mask(unsigned int irq) spin_unlock_irqrestore(&msm_chip->lock, irq_flags); } -static void msm_gpio_irq_unmask(unsigned int irq) +static void msm_gpio_irq_unmask(struct irq_data *d) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); spin_lock_irqsave(&msm_chip->lock, irq_flags); /* level triggered interrupts are also latched */ @@ -265,11 +265,11 @@ static void msm_gpio_irq_unmask(unsigned int irq) spin_unlock_irqrestore(&msm_chip->lock, irq_flags); } -static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); spin_lock_irqsave(&msm_chip->lock, irq_flags); @@ -282,21 +282,21 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned long irq_flags; - struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); - unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); + unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); unsigned val, mask = BIT(offset); spin_lock_irqsave(&msm_chip->lock, irq_flags); val = readl(msm_chip->regs.int_edge); if (flow_type & IRQ_TYPE_EDGE_BOTH) { writel(val | mask, msm_chip->regs.int_edge); - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } else { writel(val & ~mask, msm_chip->regs.int_edge); - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { msm_chip->both_edge_detect |= mask; @@ -333,16 +333,16 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) msm_chip->chip.base + j); } } - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static struct irq_chip msm_gpio_irq_chip = { - .name = "msmgpio", - .ack = msm_gpio_irq_ack, - .mask = msm_gpio_irq_mask, - .unmask = msm_gpio_irq_unmask, - .set_wake = msm_gpio_irq_set_wake, - .set_type = msm_gpio_irq_set_type, + .name = "msmgpio", + .irq_ack = msm_gpio_irq_ack, + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_set_wake = msm_gpio_irq_set_wake, + .irq_set_type = msm_gpio_irq_set_type, }; static int __init msm_init_gpio(void) diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c deleted file mode 100644 index 6ce41c5241a5..000000000000 --- a/arch/arm/mach-msm/gpiomux-7x30.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ -#include "gpiomux.h" - -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { -#ifdef CONFIG_SERIAL_MSM_CONSOLE - [49] = { /* UART2 RFR */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, - [50] = { /* UART2 CTS */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, - [51] = { /* UART2 RX */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, - [52] = { /* UART2 TX */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, -#endif -}; diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c index 4406e0f4ae95..f7a4ea593c95 100644 --- a/arch/arm/mach-msm/gpiomux-8x50.c +++ b/arch/arm/mach-msm/gpiomux-8x50.c @@ -16,6 +16,19 @@ */ #include "gpiomux.h" +#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE) + #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\ + | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) + #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\ + | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) +#else + #define SDCC_DAT_0_3_CMD_ACTV_CFG 0 + #define SDCC_CLK_ACTV_CFG 0 +#endif + +#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\ + | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA) + struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { [86] = { /* UART3 RX */ .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | @@ -25,4 +38,14 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | GPIOMUX_FUNC_1 | GPIOMUX_VALID, }, + /* SDC1 data[3:0] & CMD */ + [51 ... 55] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 CLK */ + [56] = { + .active = SDCC_CLK_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, }; diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S new file mode 100644 index 000000000000..0c631a9f8647 --- /dev/null +++ b/arch/arm/mach-msm/headsmp.S @@ -0,0 +1,40 @@ +/* + * linux/arch/arm/mach-realview/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __CPUINIT + +/* + * MSM specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(msm_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c new file mode 100644 index 000000000000..5a31f70dfb8e --- /dev/null +++ b/arch/arm/mach-msm/hotplug.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> + +extern volatile int pen_release; + +static inline void cpu_enter_lowpower(void) +{ + /* Just flush the cache. Changing the coherency is not yet + * available on msm. */ + flush_cache_all(); +} + +static inline void cpu_leave_lowpower(void) +{ +} + +static inline void platform_do_lowpower(unsigned int cpu) +{ + /* Just enter wfi for now. TODO: Properly shut off the cpu. */ + for (;;) { + /* + * here's the WFI + */ + asm("wfi" + : + : + : "memory", "cc"); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * The trouble is, letting people know about this is not really + * possible, since we are currently running incoherently, and + * therefore cannot safely call printk() or anything else + */ + pr_debug("CPU%u: spurious wakeup call\n", cpu); + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index 6abf4a6eadc1..2ce8f1f2fc4d 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h @@ -31,7 +31,7 @@ struct msm_acpu_clock_platform_data unsigned long wait_for_irq_khz; }; -struct clk; +struct clk_lookup; extern struct sys_timer msm_timer; @@ -41,7 +41,7 @@ void __init msm_add_devices(void); void __init msm_map_common_io(void); void __init msm_init_irq(void); void __init msm_init_gpio(void); -void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks); +void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); int __init msm_add_sdcc(unsigned int controller, struct msm_mmc_platform_data *plat, diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h index c05ca40478c7..e8d38428d813 100644 --- a/arch/arm/mach-msm/include/mach/clk.h +++ b/arch/arm/mach-msm/include/mach/clk.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __MACH_CLK_H #define __MACH_CLK_H diff --git a/arch/arm/mach-msm/include/mach/clkdev.h b/arch/arm/mach-msm/include/mach/clkdev.h new file mode 100644 index 000000000000..f87a57b59534 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/clkdev.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_MSM_CLKDEV_H +#define __ASM_ARCH_MSM_CLKDEV_H + +struct clk; + +static inline int __clk_get(struct clk *clk) { return 1; } +static inline void __clk_put(struct clk *clk) { } +#endif diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h new file mode 100644 index 000000000000..a9481b08d5c7 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/cpu.h @@ -0,0 +1,54 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef __ARCH_ARM_MACH_MSM_CPU_H__ +#define __ARCH_ARM_MACH_MSM_CPU_H__ + +/* TODO: For now, only one CPU can be compiled at a time. */ + +#define cpu_is_msm7x01() 0 +#define cpu_is_msm7x30() 0 +#define cpu_is_qsd8x50() 0 +#define cpu_is_msm8x60() 0 +#define cpu_is_msm8960() 0 + +#ifdef CONFIG_ARCH_MSM7X00A +# undef cpu_is_msm7x01 +# define cpu_is_msm7x01() 1 +#endif + +#ifdef CONFIG_ARCH_MSM7X30 +# undef cpu_is_msm7x30 +# define cpu_is_msm7x30() 1 +#endif + +#ifdef CONFIG_ARCH_QSD8X50 +# undef cpu_is_qsd8x50 +# define cpu_is_qsd8x50() 1 +#endif + +#ifdef CONFIG_ARCH_MSM8X60 +# undef cpu_is_msm8x60 +# define cpu_is_msm8x60() 1 +#endif + +#ifdef CONFIG_ARCH_MSM8960 +# undef cpu_is_msm8960 +# define cpu_is_msm8960() 1 +#endif + +#endif diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S index 4dc99aa65d07..12467157afb9 100644 --- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S +++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S @@ -26,7 +26,7 @@ * The interrupt numbering scheme is defined in the * interrupt controller spec. To wit: * - * Migrated the code from ARM MP port to be more consistant + * Migrated the code from ARM MP port to be more consistent * with interrupt processing , the following still holds true * however, all interrupts are treated the same regardless of * if they are local IPI or PPI diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h index 7386e732baad..dc1b928745e9 100644 --- a/arch/arm/mach-msm/include/mach/io.h +++ b/arch/arm/mach-msm/include/mach/io.h @@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m void msm_map_qsd8x50_io(void); void msm_map_msm7x30_io(void); void msm_map_msm8x60_io(void); +void msm_map_msm8960_io(void); extern unsigned int msm_shared_ram_phys; diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 218ef5732a24..5c7c955e6d25 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,6 +19,20 @@ #define MSM_IOMMU_H #include <linux/interrupt.h> +#include <linux/clk.h> + +/* Sharability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NON_SH 0x0 +#define MSM_IOMMU_ATTR_SH 0x4 + +/* Cacheability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NONCACHED 0x0 +#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 +#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 +#define MSM_IOMMU_ATTR_CACHED_WT 0x3 + +/* Mask for the cache policy attribute */ +#define MSM_IOMMU_CP_MASK 0x03 /* Maximum number of Machine IDs that we are allowing to be mapped to the same * context bank. The number of MIDs mapped to the same CB does not affect @@ -26,19 +40,16 @@ * be present. These mappings are typically determined at design time and are * not expected to change at run time. */ -#define MAX_NUM_MIDS 16 +#define MAX_NUM_MIDS 32 /** * struct msm_iommu_dev - a single IOMMU hardware instance * name Human-readable name given to this IOMMU HW instance - * clk_rate Rate to set for this IOMMU's clock, if applicable to this - * particular IOMMU. 0 means don't set a rate. - * -1 means it is an AXI clock with no valid rate - * + * ncb Number of context banks present on this IOMMU HW instance */ struct msm_iommu_dev { const char *name; - int clk_rate; + int ncb; }; /** @@ -60,14 +71,20 @@ struct msm_iommu_ctx_dev { /** * struct msm_iommu_drvdata - A single IOMMU hardware instance * @base: IOMMU config port base address (VA) + * @ncb The number of contexts on this IOMMU * @irq: Interrupt number - * + * @clk: The bus clock for this IOMMU hardware instance + * @pclk: The clock for the IOMMU bus interconnect + * * A msm_iommu_drvdata holds the global driver data about a single piece * of an IOMMU hardware instance. */ struct msm_iommu_drvdata { void __iomem *base; int irq; + int ncb; + struct clk *clk; + struct clk *pclk; }; /** diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index f9386d3a2f77..fc160101dead 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -54,6 +54,7 @@ do { \ #define NUM_FL_PTE 4096 #define NUM_SL_PTE 256 +#define NUM_TEX_CLASS 8 /* First-level page table bits */ #define FL_BASE_MASK 0xFFFFFC00 @@ -63,7 +64,11 @@ do { \ #define FL_AP_WRITE (1 << 10) #define FL_AP_READ (1 << 11) #define FL_SHARED (1 << 16) +#define FL_BUFFERABLE (1 << 2) +#define FL_CACHEABLE (1 << 3) +#define FL_TEX0 (1 << 12) #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) +#define FL_NG (1 << 17) /* Second-level page table bits */ #define SL_BASE_MASK_LARGE 0xFFFF0000 @@ -73,7 +78,20 @@ do { \ #define SL_AP0 (1 << 4) #define SL_AP1 (2 << 4) #define SL_SHARED (1 << 10) +#define SL_BUFFERABLE (1 << 2) +#define SL_CACHEABLE (1 << 3) +#define SL_TEX0 (1 << 6) #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) +#define SL_NG (1 << 11) + +/* Memory type and cache policy attributes */ +#define MT_SO 0 +#define MT_DEV 1 +#define MT_NORMAL 2 +#define CP_NONCACHED 0 +#define CP_WB_WA 1 +#define CP_WT 2 +#define CP_WB_NWA 3 /* Global register setters / getters */ #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) @@ -607,20 +625,6 @@ do { \ #define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) -/* V2Pxx UW UR PW PR */ -#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v) -#define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v) - -#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v) -#define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v) - -#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v) -#define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v) - -#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v) -#define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v) - - /* Context Register getters */ /* ACTLR */ #define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) @@ -706,7 +710,9 @@ do { \ #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) - +#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) +#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ + ((n) * 2 + 16)) /* PAR */ #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) @@ -750,6 +756,8 @@ do { \ #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) +#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) +#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) /* RESUME */ @@ -804,20 +812,6 @@ do { \ #define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) -/* V2Pxx UW UR PW PR */ -#define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX) -#define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA) - -#define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX) -#define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA) - -#define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX) -#define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA) - -#define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX) -#define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA) - - /* Global Registers */ #define M2VCBR_N (0xFF000) #define CBACR_N (0xFF800) diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h index 67c5396514fe..1f15902655fd 100644 --- a/arch/arm/mach-msm/include/mach/irqs-7x30.h +++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_IRQS_7X30_H diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h new file mode 100644 index 000000000000..81ab2a6792bd --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8960.h @@ -0,0 +1,277 @@ +/* Copyright (c) 2011 Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MSM_IRQS_8960_H +#define __ASM_ARCH_MSM_IRQS_8960_H + +/* MSM ACPU Interrupt Numbers */ + +/* 0-15: STI/SGI (software triggered/generated interrupts) + 16-31: PPI (private peripheral interrupts) + 32+: SPI (shared peripheral interrupts) */ + +#define GIC_PPI_START 16 +#define GIC_SPI_START 32 + +#define INT_VGIC (GIC_PPI_START + 0) +#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) +#define INT_GP_TIMER_EXP (GIC_PPI_START + 2) +#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) +#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) +#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) +#define AVS_SVICINT (GIC_PPI_START + 6) +#define AVS_SVICINTSWDONE (GIC_PPI_START + 7) +#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) +#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) +#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10) +#define SC_AVSCPUXDOWN (GIC_PPI_START + 11) +#define SC_AVSCPUXUP (GIC_PPI_START + 12) +#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) +#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) +/* PPI 15 is unused */ + +#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) +#define SC_SICL2IRPTREQ (GIC_SPI_START + 1) +#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2) +#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3) +#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) +#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) +#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) +#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) +#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) +#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) +#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) +#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) +#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) +#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) +#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14) +#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15) +#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16) +#define SPDM_RT_1_IRQ (GIC_SPI_START + 17) +#define SPDM_DIAG_IRQ (GIC_SPI_START + 18) +#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) +#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) +#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) +#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) +#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) +#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) +#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) +#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) +#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27) +#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28) +#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) +#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) +#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) +#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) +#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) +#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) +#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35) +#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36) +#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) +#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) +#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) +#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) +#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) +#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) +#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) +#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) +#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) +#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) +#define VPE_IRQ (GIC_SPI_START + 47) +#define VFE_IRQ (GIC_SPI_START + 48) +#define VCODEC_IRQ (GIC_SPI_START + 49) +#define TV_ENC_IRQ (GIC_SPI_START + 50) +#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) +#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) +#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) +#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) +#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) +#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) +#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) +#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) +#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) +#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) +#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) +#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) +#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) +#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) +#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) +#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) +#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) +#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) +#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) +#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) +#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) +#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) +#define ROT_IRQ (GIC_SPI_START + 73) +#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) +#define MDP_IRQ (GIC_SPI_START + 75) +#define JPEGD_IRQ (GIC_SPI_START + 76) +#define JPEG_IRQ (GIC_SPI_START + 77) +#define MMSS_IMEM_IRQ (GIC_SPI_START + 78) +#define HDMI_IRQ (GIC_SPI_START + 79) +#define GFX3D_IRQ (GIC_SPI_START + 80) +#define GFX2D0_IRQ (GIC_SPI_START + 81) +#define DSI1_IRQ (GIC_SPI_START + 82) +#define CSI_1_IRQ (GIC_SPI_START + 83) +#define CSI_0_IRQ (GIC_SPI_START + 84) +#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) +#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) +#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) +#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) +#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) +#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) +#define TOP_IMEM_IRQ (GIC_SPI_START + 91) +#define FABRIC_SYS_IRQ (GIC_SPI_START + 92) +#define FABRIC_APPS_IRQ (GIC_SPI_START + 93) +#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) +#define SDC4_BAM_IRQ (GIC_SPI_START + 95) +#define SDC3_BAM_IRQ (GIC_SPI_START + 96) +#define SDC2_BAM_IRQ (GIC_SPI_START + 97) +#define SDC1_BAM_IRQ (GIC_SPI_START + 98) +#define FABRIC_SPS_IRQ (GIC_SPI_START + 99) +#define USB1_HS_IRQ (GIC_SPI_START + 100) +#define SDC4_IRQ_0 (GIC_SPI_START + 101) +#define SDC3_IRQ_0 (GIC_SPI_START + 102) +#define SDC2_IRQ_0 (GIC_SPI_START + 103) +#define SDC1_IRQ_0 (GIC_SPI_START + 104) +#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) +#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) +#define SPS_MTI_0 (GIC_SPI_START + 107) +#define SPS_MTI_1 (GIC_SPI_START + 108) +#define SPS_MTI_2 (GIC_SPI_START + 109) +#define SPS_MTI_3 (GIC_SPI_START + 110) +#define SPS_MTI_4 (GIC_SPI_START + 111) +#define SPS_MTI_5 (GIC_SPI_START + 112) +#define SPS_MTI_6 (GIC_SPI_START + 113) +#define SPS_MTI_7 (GIC_SPI_START + 114) +#define SPS_MTI_8 (GIC_SPI_START + 115) +#define SPS_MTI_9 (GIC_SPI_START + 116) +#define SPS_MTI_10 (GIC_SPI_START + 117) +#define SPS_MTI_11 (GIC_SPI_START + 118) +#define SPS_MTI_12 (GIC_SPI_START + 119) +#define SPS_MTI_13 (GIC_SPI_START + 120) +#define SPS_MTI_14 (GIC_SPI_START + 121) +#define SPS_MTI_15 (GIC_SPI_START + 122) +#define SPS_MTI_16 (GIC_SPI_START + 123) +#define SPS_MTI_17 (GIC_SPI_START + 124) +#define SPS_MTI_18 (GIC_SPI_START + 125) +#define SPS_MTI_19 (GIC_SPI_START + 126) +#define SPS_MTI_20 (GIC_SPI_START + 127) +#define SPS_MTI_21 (GIC_SPI_START + 128) +#define SPS_MTI_22 (GIC_SPI_START + 129) +#define SPS_MTI_23 (GIC_SPI_START + 130) +#define SPS_MTI_24 (GIC_SPI_START + 131) +#define SPS_MTI_25 (GIC_SPI_START + 132) +#define SPS_MTI_26 (GIC_SPI_START + 133) +#define SPS_MTI_27 (GIC_SPI_START + 134) +#define SPS_MTI_28 (GIC_SPI_START + 135) +#define SPS_MTI_29 (GIC_SPI_START + 136) +#define SPS_MTI_30 (GIC_SPI_START + 137) +#define SPS_MTI_31 (GIC_SPI_START + 138) +#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139) +#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140) +#define USB2_IRQ (GIC_SPI_START + 141) +#define USB1_IRQ (GIC_SPI_START + 142) +#define TSSC_SSBI_IRQ (GIC_SPI_START + 143) +#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) +#define TSSC_PENUP_IRQ (GIC_SPI_START + 145) +#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146) +#define GSBI1_QUP_IRQ (GIC_SPI_START + 147) +#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148) +#define GSBI2_QUP_IRQ (GIC_SPI_START + 149) +#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) +#define GSBI3_QUP_IRQ (GIC_SPI_START + 151) +#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) +#define GSBI4_QUP_IRQ (GIC_SPI_START + 153) +#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) +#define GSBI5_QUP_IRQ (GIC_SPI_START + 155) +#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156) +#define GSBI6_QUP_IRQ (GIC_SPI_START + 157) +#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158) +#define GSBI7_QUP_IRQ (GIC_SPI_START + 159) +#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160) +#define GSBI8_QUP_IRQ (GIC_SPI_START + 161) +#define TSIF_TSPP_IRQ (GIC_SPI_START + 162) +#define TSIF_BAM_IRQ (GIC_SPI_START + 163) +#define TSIF2_IRQ (GIC_SPI_START + 164) +#define TSIF1_IRQ (GIC_SPI_START + 165) +#define DSI2_IRQ (GIC_SPI_START + 166) +#define ISPIF_IRQ (GIC_SPI_START + 167) +#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) +#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) +#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170) +#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171) +#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172) +#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173) +#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) +#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) +#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) +#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) +#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) +#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) +#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) +#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) +#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) +#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) +#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) +#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) +#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186) +#define SDC5_BAM_IRQ (GIC_SPI_START + 187) +#define SDC5_IRQ_0 (GIC_SPI_START + 188) +#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189) +#define GSBI9_QUP_IRQ (GIC_SPI_START + 190) +#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191) +#define GSBI10_QUP_IRQ (GIC_SPI_START + 192) +#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193) +#define GSBI11_QUP_IRQ (GIC_SPI_START + 194) +#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195) +#define GSBI12_QUP_IRQ (GIC_SPI_START + 196) +#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197) +#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198) +#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199) +#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200) +#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201) +#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202) +#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203) +#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204) +#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205) +#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206) +#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207) +#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208) +#define A2_BAM_IRQ (GIC_SPI_START + 209) +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) +#define GFX2D1_IRQ (GIC_SPI_START + 212) +#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213) +#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214) +#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215) +#define QDSS_ETB_IRQ (GIC_SPI_START + 216) +#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217) +#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) +#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) +#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) +#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) +#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) +#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) +#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) +#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225) +#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226) + +/* For now, use the maximum number of interrupts until a pending GIC issue + * is sorted out */ +#define NR_MSM_IRQS 1020 +#define NR_BOARD_IRQS 0 +#define NR_GPIO_IRQS 0 + +#endif + diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h index de3d8fe24e4e..26adbe0e9406 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x50.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h @@ -1,30 +1,13 @@ /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h index 36074cfc9ad2..f65841c74c0b 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -237,7 +237,12 @@ #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) #define INT_UART12DM_IRQ (GIC_SPI_START + 195) #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) -/*SPI 197 to 216 arent used in 8x60*/ + +/*SPI 197 to 209 arent used in 8x60*/ +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) + +/*SPI 212 to 216 arent used in 8x60*/ #define SMPSS_SPARE_1 (GIC_SPI_START + 217) #define SMPSS_SPARE_2 (GIC_SPI_START + 218) #define SMPSS_SPARE_3 (GIC_SPI_START + 219) diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 8679a4564744..3cd78b165abb 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h @@ -26,6 +26,9 @@ #include "sirc.h" #elif defined(CONFIG_ARCH_MSM8X60) #include "irqs-8x60.h" +#elif defined(CONFIG_ARCH_MSM8960) +/* TODO: Make these not generic. */ +#include "irqs-8960.h" #elif defined(CONFIG_ARCH_MSM_ARM11) #include "irqs-7x00.h" #else diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 070e17d237f1..f2f8d299ba95 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -18,15 +18,17 @@ /* physical offset of RAM */ #if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #elif defined(CONFIG_ARCH_QSD8X50) -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #elif defined(CONFIG_ARCH_MSM7X30) -#define PHYS_OFFSET UL(0x00200000) +#define PLAT_PHYS_OFFSET UL(0x00200000) #elif defined(CONFIG_ARCH_MSM8X60) -#define PHYS_OFFSET UL(0x40200000) +#define PLAT_PHYS_OFFSET UL(0x40200000) +#elif defined(CONFIG_ARCH_MSM8960) +#define PLAT_PHYS_OFFSET UL(0x40200000) #else -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #endif #endif diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h index d54b6b086cff..5631b51cec46 100644 --- a/arch/arm/mach-msm/include/mach/mmc.h +++ b/arch/arm/mach-msm/include/mach/mmc.h @@ -15,12 +15,23 @@ struct embedded_sdio_data { int num_funcs; }; +struct msm_mmc_gpio { + unsigned no; + const char *name; +}; + +struct msm_mmc_gpio_data { + struct msm_mmc_gpio *gpio; + u8 size; +}; + struct msm_mmc_platform_data { unsigned int ocr_mask; /* available voltages */ u32 (*translate_vdd)(struct device *, unsigned int); unsigned int (*status)(struct device *); struct embedded_sdio_data *embedded_sdio; int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); + struct msm_mmc_gpio_data *gpio_data; }; #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index cfff0e74f128..8f99d97615a0 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -1,6 +1,7 @@ /* arch/arm/mach-msm/include/mach/msm_iomap.h * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -47,13 +48,8 @@ #define MSM_VIC_PHYS 0xC0000000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xC0100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_GPT_PHYS MSM_CSR_PHYS -#define MSM_GPT_BASE MSM_CSR_BASE -#define MSM_GPT_SIZE SZ_4K +#define MSM7X00_CSR_PHYS 0xC0100000 +#define MSM7X00_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xA9700000 @@ -130,10 +126,4 @@ #define MSM_AD5_SIZE (SZ_1M*13) -#if defined(CONFIG_ARCH_MSM7X30) -#define MSM_GCC_BASE IOMEM(0xF8009000) -#define MSM_GCC_PHYS 0xC0182000 -#define MSM_GCC_SIZE SZ_4K -#endif - #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 8a00c2defbc1..4d84be15955e 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -39,16 +39,8 @@ #define MSM_VIC_PHYS 0xC0080000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xC0100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_TMR_PHYS MSM_CSR_PHYS -#define MSM_TMR_BASE MSM_CSR_BASE -#define MSM_TMR_SIZE SZ_4K - -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) +#define MSM7X30_CSR_PHYS 0xC0100000 +#define MSM7X30_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xAC400000 @@ -119,4 +111,7 @@ #define MSM_AD5_PHYS 0xA7000000 #define MSM_AD5_SIZE (SZ_1M*13) +#define MSM_HSUSB_PHYS 0xA3600000 +#define MSM_HSUSB_SIZE SZ_1K + #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h new file mode 100644 index 000000000000..3c9d9602a318 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_8960_H +#define __ASM_ARCH_MSM_IOMAP_8960_H + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + + +#define MSM8960_QGIC_DIST_PHYS 0x02000000 +#define MSM8960_QGIC_DIST_SIZE SZ_4K + +#define MSM8960_QGIC_CPU_PHYS 0x02002000 +#define MSM8960_QGIC_CPU_SIZE SZ_4K + +#define MSM8960_TMR_PHYS 0x0200A000 +#define MSM8960_TMR_SIZE SZ_4K + +#define MSM8960_TMR0_PHYS 0x0208A000 +#define MSM8960_TMR0_SIZE SZ_4K + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index acc819eb76e5..d4143201999f 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -39,16 +39,8 @@ #define MSM_VIC_PHYS 0xAC000000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xAC100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_TMR_PHYS MSM_CSR_PHYS -#define MSM_TMR_BASE MSM_CSR_BASE -#define MSM_TMR_SIZE SZ_4K - -#define MSM_GPT_BASE MSM_TMR_BASE -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10) +#define QSD8X50_CSR_PHYS 0xAC100000 +#define QSD8X50_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xA9700000 @@ -132,16 +124,16 @@ #define MSM_UART2DM_PHYS 0xA0900000 -#define MSM_SDC1_PHYS 0xA0400000 +#define MSM_SDC1_PHYS 0xA0300000 #define MSM_SDC1_SIZE SZ_4K -#define MSM_SDC2_PHYS 0xA0500000 +#define MSM_SDC2_PHYS 0xA0400000 #define MSM_SDC2_SIZE SZ_4K -#define MSM_SDC3_PHYS 0xA0600000 +#define MSM_SDC3_PHYS 0xA0500000 #define MSM_SDC3_SIZE SZ_4K -#define MSM_SDC4_PHYS 0xA0700000 +#define MSM_SDC4_PHYS 0xA0600000 #define MSM_SDC4_SIZE SZ_4K #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 45bab50e3ee6..3b19b8f244b8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -35,13 +35,11 @@ * */ -#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) -#define MSM_QGIC_DIST_PHYS 0x02080000 -#define MSM_QGIC_DIST_SIZE SZ_4K +#define MSM8X60_QGIC_DIST_PHYS 0x02080000 +#define MSM8X60_QGIC_DIST_SIZE SZ_4K -#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) -#define MSM_QGIC_CPU_PHYS 0x02081000 -#define MSM_QGIC_CPU_SIZE SZ_4K +#define MSM8X60_QGIC_CPU_PHYS 0x02081000 +#define MSM8X60_QGIC_CPU_SIZE SZ_4K #define MSM_ACC_BASE IOMEM(0xF0002000) #define MSM_ACC_PHYS 0x02001000 @@ -58,44 +56,10 @@ #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) #define MSM_SHARED_RAM_SIZE SZ_1M -#define MSM_TMR_BASE IOMEM(0xF0200000) -#define MSM_TMR_PHYS 0x02000000 -#define MSM_TMR_SIZE (SZ_1M) +#define MSM8X60_TMR_PHYS 0x02000000 +#define MSM8X60_TMR_SIZE SZ_4K -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) - -#define MSM_IOMMU_JPEGD_PHYS 0x07300000 -#define MSM_IOMMU_JPEGD_SIZE SZ_1M - -#define MSM_IOMMU_VPE_PHYS 0x07400000 -#define MSM_IOMMU_VPE_SIZE SZ_1M - -#define MSM_IOMMU_MDP0_PHYS 0x07500000 -#define MSM_IOMMU_MDP0_SIZE SZ_1M - -#define MSM_IOMMU_MDP1_PHYS 0x07600000 -#define MSM_IOMMU_MDP1_SIZE SZ_1M - -#define MSM_IOMMU_ROT_PHYS 0x07700000 -#define MSM_IOMMU_ROT_SIZE SZ_1M - -#define MSM_IOMMU_IJPEG_PHYS 0x07800000 -#define MSM_IOMMU_IJPEG_SIZE SZ_1M - -#define MSM_IOMMU_VFE_PHYS 0x07900000 -#define MSM_IOMMU_VFE_SIZE SZ_1M - -#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000 -#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M - -#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000 -#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M - -#define MSM_IOMMU_GFX3D_PHYS 0x07C00000 -#define MSM_IOMMU_GFX3D_SIZE SZ_1M - -#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 -#define MSM_IOMMU_GFX2D0_SIZE SZ_1M +#define MSM8X60_TMR0_PHYS 0x02040000 +#define MSM8X60_TMR0_SIZE SZ_4K #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 8e24dd812139..c98c7591f3b8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -53,6 +53,13 @@ #include "msm_iomap-7x00.h" #endif +#include "msm_iomap-8960.h" +/* Virtual addressses shared across all MSM targets. */ +#define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) +#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) +#define MSM_TMR_BASE IOMEM(0xF0200000) +#define MSM_TMR0_BASE IOMEM(0xF0201000) #endif diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h index 7281337ee28d..ef55868a5b8a 100644 --- a/arch/arm/mach-msm/include/mach/sirc.h +++ b/arch/arm/mach-msm/include/mach/sirc.h @@ -1,30 +1,13 @@ /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_SIRC_H diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h index 3ff7bf5e679e..3c01000ecc80 100644 --- a/arch/arm/mach-msm/include/mach/smp.h +++ b/arch/arm/mach-msm/include/mach/smp.h @@ -1,29 +1,13 @@ /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Code Aurora nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_SMP_H @@ -31,9 +15,9 @@ #include <asm/hardware/gic.h> -static inline void smp_cross_call(const struct cpumask *mask) +static inline void smp_cross_call(const struct cpumask *mask, int ipi) { - gic_raise_softirq(mask, 1); + gic_raise_softirq(mask, ipi); } #endif diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index d36b61074146..cec6ed1c91d3 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -3,7 +3,7 @@ * MSM7K, QSD io support * * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -28,19 +28,20 @@ #include <mach/board.h> -#define MSM_DEVICE(name) { \ +#define MSM_CHIP_DEVICE(name, chip) { \ .virtual = (unsigned long) MSM_##name##_BASE, \ - .pfn = __phys_to_pfn(MSM_##name##_PHYS), \ - .length = MSM_##name##_SIZE, \ + .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ + .length = chip##_##name##_SIZE, \ .type = MT_DEVICE_NONSHARED, \ } +#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) + #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ || defined(CONFIG_ARCH_MSM7X25) static struct map_desc msm_io_desc[] __initdata = { MSM_DEVICE(VIC), - MSM_DEVICE(CSR), - MSM_DEVICE(GPT), + MSM_CHIP_DEVICE(CSR, MSM7X00), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), @@ -73,8 +74,7 @@ void __init msm_map_common_io(void) #ifdef CONFIG_ARCH_QSD8X50 static struct map_desc qsd8x50_io_desc[] __initdata = { MSM_DEVICE(VIC), - MSM_DEVICE(CSR), - MSM_DEVICE(TMR), + MSM_CHIP_DEVICE(CSR, QSD8X50), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), @@ -102,9 +102,10 @@ void __init msm_map_qsd8x50_io(void) #ifdef CONFIG_ARCH_MSM8X60 static struct map_desc msm8x60_io_desc[] __initdata = { - MSM_DEVICE(QGIC_DIST), - MSM_DEVICE(QGIC_CPU), - MSM_DEVICE(TMR), + MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), + MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), + MSM_CHIP_DEVICE(TMR, MSM8X60), + MSM_CHIP_DEVICE(TMR0, MSM8X60), MSM_DEVICE(ACC), MSM_DEVICE(GCC), }; @@ -115,11 +116,24 @@ void __init msm_map_msm8x60_io(void) } #endif /* CONFIG_ARCH_MSM8X60 */ +#ifdef CONFIG_ARCH_MSM8960 +static struct map_desc msm8960_io_desc[] __initdata = { + MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), + MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), + MSM_CHIP_DEVICE(TMR, MSM8960), + MSM_CHIP_DEVICE(TMR0, MSM8960), +}; + +void __init msm_map_msm8960_io(void) +{ + iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc)); +} +#endif /* CONFIG_ARCH_MSM8960 */ + #ifdef CONFIG_ARCH_MSM7X30 static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), - MSM_DEVICE(CSR), - MSM_DEVICE(TMR), + MSM_CHIP_DEVICE(CSR, MSM7X30), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), @@ -153,7 +167,7 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) { if (mtype == MT_DEVICE) { /* The peripherals in the 88000000 - D0000000 range - * are only accessable by type MT_DEVICE_NONSHARED. + * are only accessible by type MT_DEVICE_NONSHARED. * Adjust mtype as necessary to make this "just work." */ if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000)) @@ -163,3 +177,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) return __arm_ioremap_caller(phys_addr, size, mtype, __builtin_return_address(0)); } +EXPORT_SYMBOL(__msm_ioremap); diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index f71747db3bee..1a584e077c61 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -26,6 +26,7 @@ #include <linux/spinlock.h> #include <linux/slab.h> #include <linux/iommu.h> +#include <linux/clk.h> #include <asm/cacheflush.h> #include <asm/sizes.h> @@ -33,6 +34,16 @@ #include <mach/iommu_hw-8xxx.h> #include <mach/iommu.h> +#define MRC(reg, processor, op1, crn, crm, op2) \ +__asm__ __volatile__ ( \ +" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ +: "=r" (reg)) + +#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0) +#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1) + +static int msm_iommu_tex_class[4]; + DEFINE_SPINLOCK(msm_iommu_lock); struct msm_priv { @@ -40,23 +51,50 @@ struct msm_priv { struct list_head list_attached; }; -static void __flush_iotlb(struct iommu_domain *domain) +static int __enable_clocks(struct msm_iommu_drvdata *drvdata) +{ + int ret; + + ret = clk_enable(drvdata->pclk); + if (ret) + goto fail; + + if (drvdata->clk) { + ret = clk_enable(drvdata->clk); + if (ret) + clk_disable(drvdata->pclk); + } +fail: + return ret; +} + +static void __disable_clocks(struct msm_iommu_drvdata *drvdata) +{ + if (drvdata->clk) + clk_disable(drvdata->clk); + clk_disable(drvdata->pclk); +} + +static int __flush_iotlb(struct iommu_domain *domain) { struct msm_priv *priv = domain->priv; struct msm_iommu_drvdata *iommu_drvdata; struct msm_iommu_ctx_drvdata *ctx_drvdata; - + int ret = 0; #ifndef CONFIG_IOMMU_PGTABLES_L2 unsigned long *fl_table = priv->pgtable; int i; - dmac_flush_range(fl_table, fl_table + SZ_16K); + if (!list_empty(&priv->list_attached)) { + dmac_flush_range(fl_table, fl_table + SZ_16K); - for (i = 0; i < NUM_FL_PTE; i++) - if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { - void *sl_table = __va(fl_table[i] & FL_BASE_MASK); - dmac_flush_range(sl_table, sl_table + SZ_4K); - } + for (i = 0; i < NUM_FL_PTE; i++) + if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { + void *sl_table = __va(fl_table[i] & + FL_BASE_MASK); + dmac_flush_range(sl_table, sl_table + SZ_4K); + } + } #endif list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) { @@ -64,8 +102,17 @@ static void __flush_iotlb(struct iommu_domain *domain) BUG(); iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); + BUG_ON(!iommu_drvdata); + + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); + __disable_clocks(iommu_drvdata); } +fail: + return ret; } static void __reset_context(void __iomem *base, int ctx) @@ -90,11 +137,11 @@ static void __reset_context(void __iomem *base, int ctx) SET_TLBLKCR(base, ctx, 0); SET_PRRR(base, ctx, 0); SET_NMRR(base, ctx, 0); - SET_CONTEXTIDR(base, ctx, 0); } static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) { + unsigned int prrr, nmrr; __reset_context(base, ctx); /* Set up HTW mode */ @@ -127,11 +174,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) /* Turn on TEX Remap */ SET_TRE(base, ctx, 1); - /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume - * TEX class 0 for everything until attributes are properly worked out - */ - SET_PRRR(base, ctx, 0); - SET_NMRR(base, ctx, 0); + /* Set TEX remap attributes */ + RCP15_PRRR(prrr); + RCP15_NMRR(nmrr); + SET_PRRR(base, ctx, prrr); + SET_NMRR(base, ctx, nmrr); /* Turn on BFB prefetch */ SET_BFBDFE(base, ctx, 1); @@ -238,17 +285,27 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) goto fail; } + if (!list_empty(&ctx_drvdata->attached_elm)) { + ret = -EBUSY; + goto fail; + } + list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm) if (tmp_drvdata == ctx_drvdata) { ret = -EBUSY; goto fail; } + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + __program_context(iommu_drvdata->base, ctx_dev->num, __pa(priv->pgtable)); + __disable_clocks(iommu_drvdata); list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); - __flush_iotlb(domain); + ret = __flush_iotlb(domain); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); @@ -263,6 +320,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, struct msm_iommu_drvdata *iommu_drvdata; struct msm_iommu_ctx_drvdata *ctx_drvdata; unsigned long flags; + int ret; spin_lock_irqsave(&msm_iommu_lock, flags); priv = domain->priv; @@ -277,8 +335,16 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) goto fail; - __flush_iotlb(domain); + ret = __flush_iotlb(domain); + if (ret) + goto fail; + + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + __reset_context(iommu_drvdata->base, ctx_dev->num); + __disable_clocks(iommu_drvdata); list_del_init(&ctx_drvdata->attached_elm); fail: @@ -296,12 +362,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, unsigned long *sl_table; unsigned long *sl_pte; unsigned long sl_offset; + unsigned int pgprot; size_t len = 0x1000UL << order; - int ret = 0; + int ret = 0, tex, sh; spin_lock_irqsave(&msm_iommu_lock, flags); - priv = domain->priv; + sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0; + tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK]; + + if (tex < 0 || tex > NUM_TEX_CLASS - 1) { + ret = -EINVAL; + goto fail; + } + + priv = domain->priv; if (!priv) { ret = -EINVAL; goto fail; @@ -322,6 +397,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, goto fail; } + if (len == SZ_16M || len == SZ_1M) { + pgprot = sh ? FL_SHARED : 0; + pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0; + pgprot |= tex & 0x02 ? FL_CACHEABLE : 0; + pgprot |= tex & 0x04 ? FL_TEX0 : 0; + } else { + pgprot = sh ? SL_SHARED : 0; + pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0; + pgprot |= tex & 0x02 ? SL_CACHEABLE : 0; + pgprot |= tex & 0x04 ? SL_TEX0 : 0; + } + fl_offset = FL_OFFSET(va); /* Upper 12 bits */ fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */ @@ -330,17 +417,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, for (i = 0; i < 16; i++) *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | - FL_SHARED; + FL_SHARED | FL_NG | pgprot; } if (len == SZ_1M) - *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | - FL_TYPE_SECT | FL_SHARED; + *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG | + FL_TYPE_SECT | FL_SHARED | pgprot; /* Need a 2nd level table */ if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) { unsigned long *sl; - sl = (unsigned long *) __get_free_pages(GFP_KERNEL, + sl = (unsigned long *) __get_free_pages(GFP_ATOMIC, get_order(SZ_4K)); if (!sl) { @@ -359,18 +446,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, if (len == SZ_4K) - *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | - SL_SHARED | SL_TYPE_SMALL; + *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG | + SL_SHARED | SL_TYPE_SMALL | pgprot; if (len == SZ_64K) { int i; for (i = 0; i < 16; i++) *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | - SL_AP1 | SL_SHARED | SL_TYPE_LARGE; + SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; } - __flush_iotlb(domain); + ret = __flush_iotlb(domain); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -455,7 +542,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va, } } - __flush_iotlb(domain); + ret = __flush_iotlb(domain); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -486,12 +573,13 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, base = iommu_drvdata->base; ctx = ctx_drvdata->num; + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + /* Invalidate context TLB */ SET_CTX_TLBIALL(base, ctx, 0); - SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); - - if (GET_FAULT(base, ctx)) - goto fail; + SET_V2PPR(base, ctx, va & V2Pxx_VA); par = GET_PAR(base, ctx); @@ -501,6 +589,10 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, else /* Upper 20 bits from PAR, lower 12 from VA */ ret = (par & 0xFFFFF000) | (va & 0x00000FFF); + if (GET_FAULT(base, ctx)) + ret = 0; + + __disable_clocks(iommu_drvdata); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -543,8 +635,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) { struct msm_iommu_drvdata *drvdata = dev_id; void __iomem *base; - unsigned int fsr = 0; - int ncb = 0, i = 0; + unsigned int fsr; + int i, ret; spin_lock(&msm_iommu_lock); @@ -555,12 +647,14 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) base = drvdata->base; - pr_err("===== WOAH! =====\n"); pr_err("Unexpected IOMMU page fault!\n"); pr_err("base = %08x\n", (unsigned int) base); - ncb = GET_NCB(base)+1; - for (i = 0; i < ncb; i++) { + ret = __enable_clocks(drvdata); + if (ret) + goto fail; + + for (i = 0; i < drvdata->ncb; i++) { fsr = GET_FSR(base, i); if (fsr) { pr_err("Fault occurred in context %d.\n", i); @@ -569,6 +663,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) SET_FSR(base, i, 0x4000000F); } } + __disable_clocks(drvdata); fail: spin_unlock(&msm_iommu_lock); return 0; @@ -585,8 +680,47 @@ static struct iommu_ops msm_iommu_ops = { .domain_has_cap = msm_iommu_domain_has_cap }; -static int msm_iommu_init(void) +static int __init get_tex_class(int icp, int ocp, int mt, int nos) +{ + int i = 0; + unsigned int prrr = 0; + unsigned int nmrr = 0; + int c_icp, c_ocp, c_mt, c_nos; + + RCP15_PRRR(prrr); + RCP15_NMRR(nmrr); + + for (i = 0; i < NUM_TEX_CLASS; i++) { + c_nos = PRRR_NOS(prrr, i); + c_mt = PRRR_MT(prrr, i); + c_icp = NMRR_ICP(nmrr, i); + c_ocp = NMRR_OCP(nmrr, i); + + if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos) + return i; + } + + return -ENODEV; +} + +static void __init setup_iommu_tex_classes(void) +{ + msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] = + get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1); + + msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] = + get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1); + + msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] = + get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1); + + msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] = + get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1); +} + +static int __init msm_iommu_init(void) { + setup_iommu_tex_classes(); register_iommu(&msm_iommu_ops); return 0; } diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index 9019cee2907b..8e8fb079852d 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -29,6 +29,7 @@ #include <mach/iommu_hw-8xxx.h> #include <mach/iommu.h> +#include <mach/clk.h> struct iommu_ctx_iter_data { /* input */ @@ -84,9 +85,9 @@ fail: } EXPORT_SYMBOL(msm_iommu_get_ctx); -static void msm_iommu_reset(void __iomem *base) +static void msm_iommu_reset(void __iomem *base, int ncb) { - int ctx, ncb; + int ctx; SET_RPUE(base, 0); SET_RPUEIE(base, 0); @@ -99,7 +100,6 @@ static void msm_iommu_reset(void __iomem *base) SET_GLOBAL_TLBIALL(base, 0); SET_RPU_ACR(base, 0); SET_TLBLKCRWE(base, 1); - ncb = GET_NCB(base)+1; for (ctx = 0; ctx < ncb; ctx++) { SET_BPRCOSH(base, ctx, 0); @@ -130,117 +130,140 @@ static int msm_iommu_probe(struct platform_device *pdev) { struct resource *r, *r2; struct clk *iommu_clk; + struct clk *iommu_pclk; struct msm_iommu_drvdata *drvdata; struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data; void __iomem *regs_base; resource_size_t len; - int ret = 0, ncb, nm2v, irq; + int ret, irq, par; - if (pdev->id != -1) { - drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); + if (pdev->id == -1) { + msm_iommu_root_dev = pdev; + return 0; + } - if (!drvdata) { - ret = -ENOMEM; - goto fail; - } + drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); - if (!iommu_dev) { - ret = -ENODEV; - goto fail; - } + if (!drvdata) { + ret = -ENOMEM; + goto fail; + } - if (iommu_dev->clk_rate != 0) { - iommu_clk = clk_get(&pdev->dev, "iommu_clk"); - - if (IS_ERR(iommu_clk)) { - ret = -ENODEV; - goto fail; - } - - if (iommu_dev->clk_rate > 0) { - ret = clk_set_rate(iommu_clk, - iommu_dev->clk_rate); - if (ret) { - clk_put(iommu_clk); - goto fail; - } - } - - ret = clk_enable(iommu_clk); - if (ret) { - clk_put(iommu_clk); - goto fail; - } + if (!iommu_dev) { + ret = -ENODEV; + goto fail; + } + + iommu_pclk = clk_get(NULL, "smmu_pclk"); + if (IS_ERR(iommu_pclk)) { + ret = -ENODEV; + goto fail; + } + + ret = clk_enable(iommu_pclk); + if (ret) + goto fail_enable; + + iommu_clk = clk_get(&pdev->dev, "iommu_clk"); + + if (!IS_ERR(iommu_clk)) { + if (clk_get_rate(iommu_clk) == 0) + clk_set_min_rate(iommu_clk, 1); + + ret = clk_enable(iommu_clk); + if (ret) { clk_put(iommu_clk); + goto fail_pclk; } + } else + iommu_clk = NULL; - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "physbase"); - if (!r) { - ret = -ENODEV; - goto fail; - } + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "physbase"); - len = r->end - r->start + 1; + if (!r) { + ret = -ENODEV; + goto fail_clk; + } - r2 = request_mem_region(r->start, len, r->name); - if (!r2) { - pr_err("Could not request memory region: " - "start=%p, len=%d\n", (void *) r->start, len); - ret = -EBUSY; - goto fail; - } + len = resource_size(r); - regs_base = ioremap(r2->start, len); + r2 = request_mem_region(r->start, len, r->name); + if (!r2) { + pr_err("Could not request memory region: start=%p, len=%d\n", + (void *) r->start, len); + ret = -EBUSY; + goto fail_clk; + } - if (!regs_base) { - pr_err("Could not ioremap: start=%p, len=%d\n", - (void *) r2->start, len); - ret = -EBUSY; - goto fail_mem; - } + regs_base = ioremap(r2->start, len); - irq = platform_get_irq_byname(pdev, "secure_irq"); - if (irq < 0) { - ret = -ENODEV; - goto fail_io; - } + if (!regs_base) { + pr_err("Could not ioremap: start=%p, len=%d\n", + (void *) r2->start, len); + ret = -EBUSY; + goto fail_mem; + } - mb(); + irq = platform_get_irq_byname(pdev, "secure_irq"); + if (irq < 0) { + ret = -ENODEV; + goto fail_io; + } - if (GET_IDR(regs_base) == 0) { - pr_err("Invalid IDR value detected\n"); - ret = -ENODEV; - goto fail_io; - } + msm_iommu_reset(regs_base, iommu_dev->ncb); - ret = request_irq(irq, msm_iommu_fault_handler, 0, - "msm_iommu_secure_irpt_handler", drvdata); - if (ret) { - pr_err("Request IRQ %d failed with ret=%d\n", irq, ret); - goto fail_io; - } + SET_M(regs_base, 0, 1); + SET_PAR(regs_base, 0, 0); + SET_V2PCFG(regs_base, 0, 1); + SET_V2PPR(regs_base, 0, 0); + par = GET_PAR(regs_base, 0); + SET_V2PCFG(regs_base, 0, 0); + SET_M(regs_base, 0, 0); - msm_iommu_reset(regs_base); - drvdata->base = regs_base; - drvdata->irq = irq; + if (!par) { + pr_err("%s: Invalid PAR value detected\n", iommu_dev->name); + ret = -ENODEV; + goto fail_io; + } - nm2v = GET_NM2VCBMT((unsigned long) regs_base); - ncb = GET_NCB((unsigned long) regs_base); + ret = request_irq(irq, msm_iommu_fault_handler, 0, + "msm_iommu_secure_irpt_handler", drvdata); + if (ret) { + pr_err("Request IRQ %d failed with ret=%d\n", irq, ret); + goto fail_io; + } - pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", - iommu_dev->name, regs_base, irq, ncb+1); - platform_set_drvdata(pdev, drvdata); - } else - msm_iommu_root_dev = pdev; + drvdata->pclk = iommu_pclk; + drvdata->clk = iommu_clk; + drvdata->base = regs_base; + drvdata->irq = irq; + drvdata->ncb = iommu_dev->ncb; - return 0; + pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", + iommu_dev->name, regs_base, irq, iommu_dev->ncb); + + platform_set_drvdata(pdev, drvdata); + + if (iommu_clk) + clk_disable(iommu_clk); + + clk_disable(iommu_pclk); + return 0; fail_io: iounmap(regs_base); fail_mem: release_mem_region(r->start, len); +fail_clk: + if (iommu_clk) { + clk_disable(iommu_clk); + clk_put(iommu_clk); + } +fail_pclk: + clk_disable(iommu_pclk); +fail_enable: + clk_put(iommu_pclk); fail: kfree(drvdata); return ret; @@ -252,7 +275,10 @@ static int msm_iommu_remove(struct platform_device *pdev) drv = platform_get_drvdata(pdev); if (drv) { - memset(drv, 0, sizeof(struct msm_iommu_drvdata)); + if (drv->clk) + clk_put(drv->clk); + clk_put(drv->pclk); + memset(drv, 0, sizeof(*drv)); kfree(drv); platform_set_drvdata(pdev, NULL); } @@ -264,7 +290,7 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) struct msm_iommu_ctx_dev *c = pdev->dev.platform_data; struct msm_iommu_drvdata *drvdata; struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL; - int i, ret = 0; + int i, ret; if (!c || !pdev->dev.parent) { ret = -EINVAL; goto fail; @@ -288,6 +314,18 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) INIT_LIST_HEAD(&ctx_drvdata->attached_elm); platform_set_drvdata(pdev, ctx_drvdata); + ret = clk_enable(drvdata->pclk); + if (ret) + goto fail; + + if (drvdata->clk) { + ret = clk_enable(drvdata->clk); + if (ret) { + clk_disable(drvdata->pclk); + goto fail; + } + } + /* Program the M2V tables for this context */ for (i = 0; i < MAX_NUM_MIDS; i++) { int mid = c->mids[i]; @@ -297,21 +335,27 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) SET_M2VCBR_N(drvdata->base, mid, 0); SET_CBACR_N(drvdata->base, c->num, 0); - /* Set VMID = MID */ - SET_VMID(drvdata->base, mid, mid); + /* Set VMID = 0 */ + SET_VMID(drvdata->base, mid, 0); /* Set the context number for that MID to this context */ SET_CBNDX(drvdata->base, mid, c->num); - /* Set MID associated with this context bank */ - SET_CBVMID(drvdata->base, c->num, mid); + /* Set MID associated with this context bank to 0*/ + SET_CBVMID(drvdata->base, c->num, 0); + + /* Set the ASID for TLB tagging for this context */ + SET_CONTEXTIDR_ASID(drvdata->base, c->num, c->num); /* Set security bit override to be Non-secure */ SET_NSCFG(drvdata->base, mid, 3); } - pr_info("context device %s with bank index %d\n", c->name, c->num); + if (drvdata->clk) + clk_disable(drvdata->clk); + clk_disable(drvdata->pclk); + dev_info(&pdev->dev, "context %s using bank %d\n", c->name, c->num); return 0; fail: kfree(ctx_drvdata); @@ -346,7 +390,7 @@ static struct platform_driver msm_iommu_ctx_driver = { .remove = msm_iommu_ctx_remove, }; -static int msm_iommu_driver_init(void) +static int __init msm_iommu_driver_init(void) { int ret; ret = platform_driver_register(&msm_iommu_driver); @@ -365,7 +409,7 @@ error: return ret; } -static void msm_iommu_driver_exit(void) +static void __exit msm_iommu_driver_exit(void) { platform_driver_unregister(&msm_iommu_ctx_driver); platform_driver_unregister(&msm_iommu_driver); diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 99f2c3473033..68c28bbdc969 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c @@ -226,19 +226,18 @@ static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val) writel(val, base + (i * 4)); } -static void msm_irq_ack(unsigned int irq) +static void msm_irq_ack(struct irq_data *d) { - void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq); - irq = 1 << (irq & 31); - writel(irq, reg); + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq); + writel(1 << (d->irq & 31), reg); } -static void msm_irq_mask(unsigned int irq) +static void msm_irq_mask(struct irq_data *d) { - void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq); - unsigned index = VIC_INT_TO_REG_INDEX(irq); - uint32_t mask = 1UL << (irq & 31); - int smsm_irq = msm_irq_to_smsm[irq]; + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq); + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + uint32_t mask = 1UL << (d->irq & 31); + int smsm_irq = msm_irq_to_smsm[d->irq]; msm_irq_shadow_reg[index].int_en[0] &= ~mask; writel(mask, reg); @@ -250,12 +249,12 @@ static void msm_irq_mask(unsigned int irq) } } -static void msm_irq_unmask(unsigned int irq) +static void msm_irq_unmask(struct irq_data *d) { - void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq); - unsigned index = VIC_INT_TO_REG_INDEX(irq); - uint32_t mask = 1UL << (irq & 31); - int smsm_irq = msm_irq_to_smsm[irq]; + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq); + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + uint32_t mask = 1UL << (d->irq & 31); + int smsm_irq = msm_irq_to_smsm[d->irq]; msm_irq_shadow_reg[index].int_en[0] |= mask; writel(mask, reg); @@ -268,14 +267,14 @@ static void msm_irq_unmask(unsigned int irq) } } -static int msm_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_irq_set_wake(struct irq_data *d, unsigned int on) { - unsigned index = VIC_INT_TO_REG_INDEX(irq); - uint32_t mask = 1UL << (irq & 31); - int smsm_irq = msm_irq_to_smsm[irq]; + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + uint32_t mask = 1UL << (d->irq & 31); + int smsm_irq = msm_irq_to_smsm[d->irq]; if (smsm_irq == 0) { - printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq); + printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq); return -EINVAL; } if (on) @@ -294,12 +293,12 @@ static int msm_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) { - void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq); - void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq); - unsigned index = VIC_INT_TO_REG_INDEX(irq); - int b = 1 << (irq & 31); + void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq); + void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq); + unsigned index = VIC_INT_TO_REG_INDEX(d->irq); + int b = 1 << (d->irq & 31); uint32_t polarity; uint32_t type; @@ -314,11 +313,11 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) type = msm_irq_shadow_reg[index].int_type; if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { type |= b; - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { type &= ~b; - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } writel(type, treg); msm_irq_shadow_reg[index].int_type = type; @@ -326,13 +325,13 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) } static struct irq_chip msm_irq_chip = { - .name = "msm", - .disable = msm_irq_mask, - .ack = msm_irq_ack, - .mask = msm_irq_mask, - .unmask = msm_irq_unmask, - .set_wake = msm_irq_set_wake, - .set_type = msm_irq_set_type, + .name = "msm", + .irq_disable = msm_irq_mask, + .irq_ack = msm_irq_ack, + .irq_mask = msm_irq_mask, + .irq_unmask = msm_irq_unmask, + .irq_set_wake = msm_irq_set_wake, + .irq_set_type = msm_irq_set_type, }; void __init msm_init_irq(void) diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 6c8d5f8caef3..0b27d899f40e 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c @@ -64,35 +64,34 @@ #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) #define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4)) -static void msm_irq_ack(unsigned int irq) +static void msm_irq_ack(struct irq_data *d) { - void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0); - irq = 1 << (irq & 31); - writel(irq, reg); + void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0); + writel(1 << (d->irq & 31), reg); } -static void msm_irq_mask(unsigned int irq) +static void msm_irq_mask(struct irq_data *d) { - void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0); - writel(1 << (irq & 31), reg); + void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0); + writel(1 << (d->irq & 31), reg); } -static void msm_irq_unmask(unsigned int irq) +static void msm_irq_unmask(struct irq_data *d) { - void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0); - writel(1 << (irq & 31), reg); + void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0); + writel(1 << (d->irq & 31), reg); } -static int msm_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_irq_set_wake(struct irq_data *d, unsigned int on) { return -EINVAL; } -static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) { - void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0); - void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0); - int b = 1 << (irq & 31); + void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0); + void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0); + int b = 1 << (d->irq & 31); if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) writel(readl(preg) | b, preg); @@ -101,22 +100,22 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { writel(readl(treg) | b, treg); - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { writel(readl(treg) & (~b), treg); - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } return 0; } static struct irq_chip msm_irq_chip = { - .name = "msm", - .ack = msm_irq_ack, - .mask = msm_irq_mask, - .unmask = msm_irq_unmask, - .set_wake = msm_irq_set_wake, - .set_type = msm_irq_set_type, + .name = "msm", + .irq_ack = msm_irq_ack, + .irq_mask = msm_irq_mask, + .irq_unmask = msm_irq_unmask, + .irq_set_wake = msm_irq_set_wake, + .irq_set_type = msm_irq_set_type, }; void __init msm_init_irq(void) diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c new file mode 100644 index 000000000000..0f427bc94447 --- /dev/null +++ b/arch/arm/mach-msm/platsmp.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/hardware/gic.h> +#include <asm/cacheflush.h> +#include <asm/mach-types.h> + +#include <mach/msm_iomap.h> + +#include "scm-boot.h" + +#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 +#define SCSS_CPU1CORE_RESET 0xD80 +#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 + +/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ +#define GIC_PPI_EDGE_MASK 0xFFFFD7FF + +extern void msm_secondary_startup(void); +/* + * control for which core is the next to come out of the secondary + * boot "holding pen". + */ +volatile int pen_release = -1; + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + /* Configure edge-triggered PPIs */ + writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); + + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +static __cpuinit void prepare_cold_cpu(unsigned int cpu) +{ + int ret; + ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), + SCM_FLAG_COLDBOOT_CPU1); + if (ret == 0) { + void *sc1_base_ptr; + sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); + if (sc1_base_ptr) { + writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); + writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); + writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); + iounmap(sc1_base_ptr); + } + } else + printk(KERN_DEBUG "Failed to set secondary core boot " + "address\n"); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + static int cold_boot_done; + + /* Only need to bring cpu out of reset this way once */ + if (cold_boot_done == false) { + prepare_cold_cpu(cpu); + cold_boot_done = true; + } + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + pen_release = cpu; + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + smp_cross_call(cpumask_of(cpu), 1); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. The msm8x60 + * does not support the ARM SCU, so just set the possible cpu mask to + * NR_CPUS. + */ +void __init smp_init_cpus(void) +{ + unsigned int i; + + for (i = 0; i < NR_CPUS; i++) + set_cpu_possible(i, true); +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); +} diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/scm-boot.c index 1250d22082ee..45cee3e469a5 100644 --- a/arch/arm/mach-msm/clock-dummy.c +++ b/arch/arm/mach-msm/scm-boot.c @@ -13,42 +13,27 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA * 02110-1301, USA. - * */ -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/module.h> - -struct clk *clk_get(struct device *dev, const char *id) -{ - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return -ENOENT; -} -EXPORT_SYMBOL(clk_enable); -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); +#include <linux/module.h> +#include <linux/slab.h> -unsigned long clk_get_rate(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_get_rate); +#include "scm.h" +#include "scm-boot.h" -int clk_set_rate(struct clk *clk, unsigned long rate) +/* + * Set the cold/warm boot address for one of the CPU cores. + */ +int scm_set_boot_addr(phys_addr_t addr, int flags) { - return -ENOENT; -} -EXPORT_SYMBOL(clk_set_rate); + struct { + unsigned int flags; + phys_addr_t addr; + } cmd; -void clk_put(struct clk *clk) -{ + cmd.addr = addr; + cmd.flags = flags; + return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); } -EXPORT_SYMBOL(clk_put); +EXPORT_SYMBOL(scm_set_boot_addr); diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h new file mode 100644 index 000000000000..7be32ff5d687 --- /dev/null +++ b/arch/arm/mach-msm/scm-boot.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MACH_SCM_BOOT_H +#define __MACH_SCM_BOOT_H + +#define SCM_BOOT_ADDR 0x1 +#define SCM_FLAG_COLDBOOT_CPU1 0x1 +#define SCM_FLAG_WARMBOOT_CPU1 0x2 +#define SCM_FLAG_WARMBOOT_CPU0 0x4 + +int scm_set_boot_addr(phys_addr_t addr, int flags); + +#endif diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c new file mode 100644 index 000000000000..cfa808dd4897 --- /dev/null +++ b/arch/arm/mach-msm/scm.c @@ -0,0 +1,293 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/errno.h> +#include <linux/err.h> + +#include <asm/cacheflush.h> + +#include "scm.h" + +/* Cache line size for msm8x60 */ +#define CACHELINESIZE 32 + +#define SCM_ENOMEM -5 +#define SCM_EOPNOTSUPP -4 +#define SCM_EINVAL_ADDR -3 +#define SCM_EINVAL_ARG -2 +#define SCM_ERROR -1 +#define SCM_INTERRUPTED 1 + +static DEFINE_MUTEX(scm_lock); + +/** + * struct scm_command - one SCM command buffer + * @len: total available memory for command and response + * @buf_offset: start of command buffer + * @resp_hdr_offset: start of response buffer + * @id: command to be executed + * @buf: buffer returned from scm_get_command_buffer() + * + * An SCM command is layed out in memory as follows: + * + * ------------------- <--- struct scm_command + * | command header | + * ------------------- <--- scm_get_command_buffer() + * | command buffer | + * ------------------- <--- struct scm_response and + * | response header | scm_command_to_response() + * ------------------- <--- scm_get_response_buffer() + * | response buffer | + * ------------------- + * + * There can be arbitrary padding between the headers and buffers so + * you should always use the appropriate scm_get_*_buffer() routines + * to access the buffers in a safe manner. + */ +struct scm_command { + u32 len; + u32 buf_offset; + u32 resp_hdr_offset; + u32 id; + u32 buf[0]; +}; + +/** + * struct scm_response - one SCM response buffer + * @len: total available memory for response + * @buf_offset: start of response data relative to start of scm_response + * @is_complete: indicates if the command has finished processing + */ +struct scm_response { + u32 len; + u32 buf_offset; + u32 is_complete; +}; + +/** + * alloc_scm_command() - Allocate an SCM command + * @cmd_size: size of the command buffer + * @resp_size: size of the response buffer + * + * Allocate an SCM command, including enough room for the command + * and response headers as well as the command and response buffers. + * + * Returns a valid &scm_command on success or %NULL if the allocation fails. + */ +static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size) +{ + struct scm_command *cmd; + size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size + + resp_size; + + cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL); + if (cmd) { + cmd->len = len; + cmd->buf_offset = offsetof(struct scm_command, buf); + cmd->resp_hdr_offset = cmd->buf_offset + cmd_size; + } + return cmd; +} + +/** + * free_scm_command() - Free an SCM command + * @cmd: command to free + * + * Free an SCM command. + */ +static inline void free_scm_command(struct scm_command *cmd) +{ + kfree(cmd); +} + +/** + * scm_command_to_response() - Get a pointer to a scm_response + * @cmd: command + * + * Returns a pointer to a response for a command. + */ +static inline struct scm_response *scm_command_to_response( + const struct scm_command *cmd) +{ + return (void *)cmd + cmd->resp_hdr_offset; +} + +/** + * scm_get_command_buffer() - Get a pointer to a command buffer + * @cmd: command + * + * Returns a pointer to the command buffer of a command. + */ +static inline void *scm_get_command_buffer(const struct scm_command *cmd) +{ + return (void *)cmd->buf; +} + +/** + * scm_get_response_buffer() - Get a pointer to a response buffer + * @rsp: response + * + * Returns a pointer to a response buffer of a response. + */ +static inline void *scm_get_response_buffer(const struct scm_response *rsp) +{ + return (void *)rsp + rsp->buf_offset; +} + +static int scm_remap_error(int err) +{ + switch (err) { + case SCM_ERROR: + return -EIO; + case SCM_EINVAL_ADDR: + case SCM_EINVAL_ARG: + return -EINVAL; + case SCM_EOPNOTSUPP: + return -EOPNOTSUPP; + case SCM_ENOMEM: + return -ENOMEM; + } + return -EINVAL; +} + +static u32 smc(u32 cmd_addr) +{ + int context_id; + register u32 r0 asm("r0") = 1; + register u32 r1 asm("r1") = (u32)&context_id; + register u32 r2 asm("r2") = cmd_addr; + do { + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2) + : "r3"); + } while (r0 == SCM_INTERRUPTED); + + return r0; +} + +static int __scm_call(const struct scm_command *cmd) +{ + int ret; + u32 cmd_addr = virt_to_phys(cmd); + + /* + * Flush the entire cache here so callers don't have to remember + * to flush the cache when passing physical addresses to the secure + * side in the buffer. + */ + flush_cache_all(); + ret = smc(cmd_addr); + if (ret < 0) + ret = scm_remap_error(ret); + + return ret; +} + +/** + * scm_call() - Send an SCM command + * @svc_id: service identifier + * @cmd_id: command identifier + * @cmd_buf: command buffer + * @cmd_len: length of the command buffer + * @resp_buf: response buffer + * @resp_len: length of the response buffer + * + * Sends a command to the SCM and waits for the command to finish processing. + */ +int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len, + void *resp_buf, size_t resp_len) +{ + int ret; + struct scm_command *cmd; + struct scm_response *rsp; + + cmd = alloc_scm_command(cmd_len, resp_len); + if (!cmd) + return -ENOMEM; + + cmd->id = (svc_id << 10) | cmd_id; + if (cmd_buf) + memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len); + + mutex_lock(&scm_lock); + ret = __scm_call(cmd); + mutex_unlock(&scm_lock); + if (ret) + goto out; + + rsp = scm_command_to_response(cmd); + do { + u32 start = (u32)rsp; + u32 end = (u32)scm_get_response_buffer(rsp) + resp_len; + start &= ~(CACHELINESIZE - 1); + while (start < end) { + asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) + : "memory"); + start += CACHELINESIZE; + } + } while (!rsp->is_complete); + + if (resp_buf) + memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len); +out: + free_scm_command(cmd); + return ret; +} +EXPORT_SYMBOL(scm_call); + +u32 scm_get_version(void) +{ + int context_id; + static u32 version = -1; + register u32 r0 asm("r0"); + register u32 r1 asm("r1"); + + if (version != -1) + return version; + + mutex_lock(&scm_lock); + + r0 = 0x1 << 8; + r1 = (u32)&context_id; + do { + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r1") + __asmeq("%2", "r0") + __asmeq("%3", "r1") + "smc #0 @ switch to secure world\n" + : "=r" (r0), "=r" (r1) + : "r" (r0), "r" (r1) + : "r2", "r3"); + } while (r0 == SCM_INTERRUPTED); + + version = r1; + mutex_unlock(&scm_lock); + + return version; +} +EXPORT_SYMBOL(scm_get_version); diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h new file mode 100644 index 000000000000..00b31ea58f29 --- /dev/null +++ b/arch/arm/mach-msm/scm.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MACH_SCM_H +#define __MACH_SCM_H + +#define SCM_SVC_BOOT 0x1 +#define SCM_SVC_PIL 0x2 + +extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len, + void *resp_buf, size_t resp_len); + +#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) + +extern u32 scm_get_version(void); + +#endif diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index b0794524ba6e..11b54c7aeb09 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -40,17 +40,13 @@ static struct sirc_cascade_regs sirc_reg_table[] = { } }; -static unsigned int save_type; -static unsigned int save_polarity; - /* Mask off the given interrupt. Keep the int_enable mask in sync with the enable reg, so it can be restored after power collapse. */ -static void sirc_irq_mask(unsigned int irq) +static void sirc_irq_mask(struct irq_data *d) { unsigned int mask; - - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); writel(mask, sirc_regs.int_enable_clear); int_enable &= ~mask; return; @@ -58,31 +54,31 @@ static void sirc_irq_mask(unsigned int irq) /* Unmask the given interrupt. Keep the int_enable mask in sync with the enable reg, so it can be restored after power collapse. */ -static void sirc_irq_unmask(unsigned int irq) +static void sirc_irq_unmask(struct irq_data *d) { unsigned int mask; - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); writel(mask, sirc_regs.int_enable_set); int_enable |= mask; return; } -static void sirc_irq_ack(unsigned int irq) +static void sirc_irq_ack(struct irq_data *d) { unsigned int mask; - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); writel(mask, sirc_regs.int_clear); return; } -static int sirc_irq_set_wake(unsigned int irq, unsigned int on) +static int sirc_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int mask; /* Used to set the interrupt enable mask during power collapse. */ - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); if (on) wake_enable |= mask; else @@ -91,12 +87,12 @@ static int sirc_irq_set_wake(unsigned int irq, unsigned int on) return 0; } -static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type) +static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned int mask; unsigned int val; - mask = 1 << (irq - FIRST_SIRC_IRQ); + mask = 1 << (d->irq - FIRST_SIRC_IRQ); val = readl(sirc_regs.int_polarity); if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) @@ -109,10 +105,10 @@ static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type) val = readl(sirc_regs.int_type); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { val |= mask; - irq_desc[irq].handle_irq = handle_edge_irq; + irq_desc[d->irq].handle_irq = handle_edge_irq; } else { val &= ~mask; - irq_desc[irq].handle_irq = handle_level_irq; + irq_desc[d->irq].handle_irq = handle_level_irq; } writel(val, sirc_regs.int_type); @@ -142,16 +138,16 @@ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc) ; generic_handle_irq(sirq+FIRST_SIRC_IRQ); - desc->chip->ack(irq); + desc->irq_data.chip->irq_ack(&desc->irq_data); } static struct irq_chip sirc_irq_chip = { - .name = "sirc", - .ack = sirc_irq_ack, - .mask = sirc_irq_mask, - .unmask = sirc_irq_unmask, - .set_wake = sirc_irq_set_wake, - .set_type = sirc_irq_set_type, + .name = "sirc", + .irq_ack = sirc_irq_ack, + .irq_mask = sirc_irq_mask, + .irq_unmask = sirc_irq_unmask, + .irq_set_wake = sirc_irq_set_wake, + .irq_set_type = sirc_irq_set_type, }; void __init msm_init_sirc(void) diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index f07dc7c738f0..657be73297db 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c @@ -14,6 +14,8 @@ * */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include <linux/platform_device.h> #include <linux/module.h> #include <linux/fs.h> @@ -89,7 +91,7 @@ static void smd_diag(void) x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); if (x != 0) { x[SZ_DIAG_ERR_MSG - 1] = 0; - pr_info("smem: DIAG '%s'\n", x); + pr_debug("DIAG '%s'\n", x); } } @@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch, { ch->last_state = next; - pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next); + pr_debug("ch %d %d -> %d\n", ch->n, last, next); switch (next) { case SMD_SS_OPENING: @@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type) ch->pdev.name = ch->name; ch->pdev.id = -1; - pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n", + pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n", ch->n, ch->fifo_size, ch->name); mutex_lock(&smd_creation_mutex); @@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work) shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); if (!shared) { - pr_err("smd: cannot find allocation table\n"); + pr_err("cannot find allocation table\n"); return; } for (n = 0; n < 64; n++) { @@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch) { unsigned long flags; - pr_info("smd_close(%p)\n", ch); - if (ch == 0) return -1; @@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay) int smd_core_init(void) { int r; - pr_info("smd_core_init()\n"); /* wait for essential items to be initialized */ for (;;) { @@ -992,15 +991,11 @@ int smd_core_init(void) smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0); #endif - pr_info("smd_core_init() done\n"); - return 0; } static int __devinit msm_smd_probe(struct platform_device *pdev) { - pr_info("smd_init()\n"); - /* * If we haven't waited for the ARM9 to boot up till now, * then we need to wait here. Otherwise this should just diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index f91c3b7bc655..8736afff82f3 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c @@ -270,8 +270,10 @@ void smsm_print_sleep_info(void) { unsigned long flags; uint32_t *ptr; +#ifndef CONFIG_ARCH_MSM_SCORPION struct tramp_gpio_smem *gpio; struct smsm_interrupt_info *int_info; +#endif spin_lock_irqsave(&smem_lock, flags); diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 950100f19d07..e7f8e5a4d48f 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -24,10 +24,7 @@ #include <asm/mach/time.h> #include <mach/msm_iomap.h> - -#ifndef MSM_DGT_BASE -#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) -#endif +#include <mach/cpu.h> #define TIMER_MATCH_VAL 0x0000 #define TIMER_COUNT_VAL 0x0004 @@ -47,10 +44,19 @@ enum { #define GPT_HZ 32768 +enum timer_location { + LOCAL_TIMER = 0, + GLOBAL_TIMER = 1, +}; + +#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT + +/* TODO: Remove these ifdefs */ #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) -#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) +#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ + defined(CONFIG_ARCH_MSM8960) #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ #define MSM_DGT_SHIFT (0) #else @@ -65,49 +71,67 @@ struct msm_clock { void __iomem *regbase; uint32_t freq; uint32_t shift; + void __iomem *global_counter; + void __iomem *local_counter; }; +enum { + MSM_CLOCK_GPT, + MSM_CLOCK_DGT, + NR_TIMERS, +}; + + +static struct msm_clock msm_clocks[]; +static struct clock_event_device *local_clock_event; + static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; + if (smp_processor_id() != 0) + evt = local_clock_event; + if (evt->event_handler == NULL) + return IRQ_HANDLED; evt->event_handler(evt); return IRQ_HANDLED; } -static cycle_t msm_gpt_read(struct clocksource *cs) +static cycle_t msm_read_timer_count(struct clocksource *cs) { - return readl(MSM_GPT_BASE + TIMER_COUNT_VAL); + struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); + + return readl(clk->global_counter); } -static cycle_t msm_dgt_read(struct clocksource *cs) +static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) { - return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT; +#ifdef CONFIG_SMP + int i; + for (i = 0; i < NR_TIMERS; i++) + if (evt == &(msm_clocks[i].clockevent)) + return &msm_clocks[i]; + return &msm_clocks[MSM_GLOBAL_TIMER]; +#else + return container_of(evt, struct msm_clock, clockevent); +#endif } static int msm_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); - uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL); + struct msm_clock *clock = clockevent_to_clock(evt); + uint32_t now = readl(clock->local_counter); uint32_t alarm = now + (cycles << clock->shift); - int late; writel(alarm, clock->regbase + TIMER_MATCH_VAL); - now = readl(clock->regbase + TIMER_COUNT_VAL); - late = now - alarm; - if (late >= (-2 << clock->shift) && late < DGT_HZ*5) { - printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, " - "alarm already expired, now %x, alarm %x, late %d\n", - cycles, clock->clockevent.name, now, alarm, late); - return -ETIME; - } return 0; } static void msm_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); + struct msm_clock *clock = clockevent_to_clock(evt); + switch (mode) { case CLOCK_EVT_MODE_RESUME: case CLOCK_EVT_MODE_PERIODIC: @@ -123,7 +147,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode, } static struct msm_clock msm_clocks[] = { - { + [MSM_CLOCK_GPT] = { .clockevent = { .name = "gp_timer", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -135,9 +159,8 @@ static struct msm_clock msm_clocks[] = { .clocksource = { .name = "gp_timer", .rating = 200, - .read = msm_gpt_read, + .read = msm_read_timer_count, .mask = CLOCKSOURCE_MASK(32), - .shift = 17, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }, .irq = { @@ -147,10 +170,9 @@ static struct msm_clock msm_clocks[] = { .dev_id = &msm_clocks[0].clockevent, .irq = INT_GP_TIMER_EXP }, - .regbase = MSM_GPT_BASE, - .freq = GPT_HZ + .freq = GPT_HZ, }, - { + [MSM_CLOCK_DGT] = { .clockevent = { .name = "dg_timer", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -162,9 +184,8 @@ static struct msm_clock msm_clocks[] = { .clocksource = { .name = "dg_timer", .rating = 300, - .read = msm_dgt_read, + .read = msm_read_timer_count, .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), - .shift = 24 - MSM_DGT_SHIFT, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }, .irq = { @@ -174,9 +195,8 @@ static struct msm_clock msm_clocks[] = { .dev_id = &msm_clocks[1].clockevent, .irq = INT_DEBUG_TIMER_EXP }, - .regbase = MSM_DGT_BASE, .freq = DGT_HZ >> MSM_DGT_SHIFT, - .shift = MSM_DGT_SHIFT + .shift = MSM_DGT_SHIFT, } }; @@ -184,8 +204,27 @@ static void __init msm_timer_init(void) { int i; int res; + int global_offset = 0; + + if (cpu_is_msm7x01()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; + } else if (cpu_is_msm7x30()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; + } else if (cpu_is_qsd8x50()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; + } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; -#ifdef CONFIG_ARCH_MSM8X60 + /* Use CPU0's timer as the global timer. */ + global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; + } else + BUG(); + +#ifdef CONFIG_ARCH_MSM_SCORPIONMP writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); #endif @@ -193,6 +232,10 @@ static void __init msm_timer_init(void) struct msm_clock *clock = &msm_clocks[i]; struct clock_event_device *ce = &clock->clockevent; struct clocksource *cs = &clock->clocksource; + + clock->local_counter = clock->regbase + TIMER_COUNT_VAL; + clock->global_counter = clock->local_counter + global_offset; + writel(0, clock->regbase + TIMER_ENABLE); writel(0, clock->regbase + TIMER_CLEAR); writel(~0, clock->regbase + TIMER_MATCH_VAL); @@ -205,8 +248,7 @@ static void __init msm_timer_init(void) ce->min_delta_ns = clockevent_delta2ns(4, ce); ce->cpumask = cpumask_of(0); - cs->mult = clocksource_hz2mult(clock->freq, cs->shift); - res = clocksource_register(cs); + res = clocksource_register_hz(cs, clock->freq); if (res) printk(KERN_ERR "msm_timer_init: clocksource_register " "failed for %s\n", cs->name); @@ -220,6 +262,48 @@ static void __init msm_timer_init(void) } } +#ifdef CONFIG_SMP +void __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER]; + + /* Use existing clock_event for cpu 0 */ + if (!smp_processor_id()) + return; + + writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); + + if (!local_clock_event) { + writel(0, clock->regbase + TIMER_ENABLE); + writel(0, clock->regbase + TIMER_CLEAR); + writel(~0, clock->regbase + TIMER_MATCH_VAL); + } + evt->irq = clock->irq.irq; + evt->name = "local_timer"; + evt->features = CLOCK_EVT_FEAT_ONESHOT; + evt->rating = clock->clockevent.rating; + evt->set_mode = msm_timer_set_mode; + evt->set_next_event = msm_timer_set_next_event; + evt->shift = clock->clockevent.shift; + evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift); + evt->max_delta_ns = + clockevent_delta2ns(0xf0000000 >> clock->shift, evt); + evt->min_delta_ns = clockevent_delta2ns(4, evt); + + local_clock_event = evt; + + gic_enable_ppi(clock->irq.irq); + + clockevents_register_device(evt); +} + +inline int local_timer_ack(void) +{ + return 1; +} + +#endif + struct sys_timer msm_timer = { .init = msm_timer_init }; |