diff options
Diffstat (limited to 'arch/arm/mach-mx5/cpu.c')
| -rw-r--r-- | arch/arm/mach-mx5/cpu.c | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 44440569f041..5abba44d25ad 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -19,7 +19,6 @@ * @ingroup MSL_MX51 */ -#include <linux/proc_fs.h> #include <linux/types.h> #include <linux/err.h> #include <linux/kernel.h> @@ -29,7 +28,6 @@ #include <linux/clk.h> #include <mach/common.h> #include <mach/hardware.h> -#include <asm/mach/map.h> #define CORTEXA8_PLAT_AMC 0x18 #define SRPG_NEON_PUPSCR 0x284 @@ -43,12 +41,6 @@ void __iomem *arm_plat_base; void __iomem *gpc_base; -void __iomem *ccm_base; -void __iomem *databahn_base; -void *wait_in_iram_base; -void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); - -extern void mx50_wait(u32 ccm_base, u32 databahn_addr); struct cpu_wp *(*get_cpu_wp)(int *wp); void (*set_num_cpu_wp)(int num); @@ -138,8 +130,6 @@ static int __init post_cpu_init(void) } gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K); - ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K); - clk_enable(gpcclk); /* Setup the number of clock cycles to wait for SRPG @@ -192,42 +182,6 @@ static int __init post_cpu_init(void) iounmap(base); } - databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); - - if (cpu_is_mx50()) { - struct clk *ddr_clk = clk_get(NULL, "ddr_clk"); - unsigned long iram_paddr; - - iram_alloc(SZ_4K, &iram_paddr); - /* Need to remap the area here since we want the memory region - to be executable. */ - wait_in_iram_base = __arm_ioremap(iram_paddr, - SZ_4K, MT_HIGH_VECTORS); - memcpy(wait_in_iram_base, mx50_wait, SZ_4K); - wait_in_iram = (void *)wait_in_iram_base; - - clk_enable(ddr_clk); - - /* Set the DDR to enter automatic self-refresh. */ - /* Set the DDR to automatically enter lower power mode 4. */ - reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22); - reg &= ~LOWPOWER_AUTOENABLE_MASK; - reg |= 1 << 1; - __raw_writel(reg, databahn_base + DATABAHN_CTL_REG22); - - /* set the counter for entering mode 4. */ - reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21); - reg &= ~LOWPOWER_EXTERNAL_CNT_MASK; - reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET; - __raw_writel(reg, databahn_base + DATABAHN_CTL_REG21); - - /* Enable low power mode 4 */ - reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20); - reg &= ~LOWPOWER_CONTROL_MASK; - reg |= 1 << 1; - __raw_writel(reg, databahn_base + DATABAHN_CTL_REG20); - clk_disable(ddr_clk); - } return 0; } |