diff options
Diffstat (limited to 'arch/arm/mach-mx5/crm_regs.h')
| -rwxr-xr-x | arch/arm/mach-mx5/crm_regs.h | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c32d19f6ddb9..fb53cbb4c95f 100755 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -492,6 +492,10 @@ /* MX53 */ #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9) #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6) #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0) @@ -787,18 +791,16 @@ #define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0) #define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300) -/* CORTEXA8 platform */ -extern void __iomem *arm_plat_base; -#define MXC_CORTEXA8_BASE (arm_plat_base) -#define MXC_CORTEXA8_PLAT_PVID (arm_plat_base + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (arm_plat_base + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (arm_plat_base + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (arm_plat_base + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (arm_plat_base + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (arm_plat_base + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (arm_plat_base + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (arm_plat_base + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (arm_plat_base + 0x24) +/* CORTEXA8 platform offsets */ +#define MXC_CORTEXA8_PLAT_PVID (0x0) +#define MXC_CORTEXA8_PLAT_GPC (0x4) +#define MXC_CORTEXA8_PLAT_PIC (0x8) +#define MXC_CORTEXA8_PLAT_LPC (0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (0x10) +#define MXC_CORTEXA8_PLAT_ICGC (0x14) +#define MXC_CORTEXA8_PLAT_AMC (0x18) +#define MXC_CORTEXA8_PLAT_NMC (0x20) +#define MXC_CORTEXA8_PLAT_NMS (0x24) /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) |