diff options
Diffstat (limited to 'arch/arm/mach-mx5/mx53_evk_gpio.c')
| -rw-r--r-- | arch/arm/mach-mx5/mx53_evk_gpio.c | 730 |
1 files changed, 579 insertions, 151 deletions
diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c index 450280e2d96a..caeee73ea414 100644 --- a/arch/arm/mach-mx5/mx53_evk_gpio.c +++ b/arch/arm/mach-mx5/mx53_evk_gpio.c @@ -50,15 +50,21 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { }, { MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH, + MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + INPUT_CTL_PATH3, }, { MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH, + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + INPUT_CTL_PATH3, }, { - MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT2, + MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH, + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + INPUT_CTL_PATH3, }, { MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT3, @@ -73,9 +79,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_EIM_D26, IOMUX_CONFIG_GPIO, }, { - MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT3, - }, - { MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT3, }, { @@ -85,12 +88,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT4, }, { - MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3, - }, - { - MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3, - }, - { MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3, (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), @@ -166,31 +163,7 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2, }, { - MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4, - }, - { - MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT5, - }, - { - MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT5, - }, - { - MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT5, - }, - { - MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5, + MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT1, }, { /* UART1 Tx */ MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2, @@ -205,19 +178,31 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { INPUT_CTL_PATH1, }, { - MX53_PIN_GPIO_2, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT7, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_360K_PD), + MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT, + INPUT_CTL_PATH2, }, { - MX53_PIN_GPIO_3, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT7, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_360K_PD), + MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT, + INPUT_CTL_PATH2, }, { MX53_PIN_GPIO_4, IOMUX_CONFIG_GPIO, }, { - MX53_PIN_GPIO_5, IOMUX_CONFIG_GPIO, - }, - { - MX53_PIN_GPIO_6, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_6, IOMUX_CONFIG_ALT7, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_360K_PD), + MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT, + INPUT_CTL_PATH2, }, { MX53_PIN_GPIO_7, IOMUX_CONFIG_GPIO, @@ -228,29 +213,79 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { { MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO, }, - { - MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO, + { /* CAN1-TX */ + MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), }, - { - MX53_PIN_GPIO_12, IOMUX_CONFIG_GPIO, + { /* CAN1-RX */ + MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* CAN1 -- EN */ + MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN1 -- STBY */ + MX53_PIN_GPIO_17, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN1 -- NERR */ + MX53_PIN_GPIO_5, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT, + INPUT_CTL_PATH1, }, - { - MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO, + { /* CAN2-TX */ + MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), }, - { - MX53_PIN_GPIO_14, IOMUX_CONFIG_GPIO, + { /* CAN2-RX */ + MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* CAN2 -- EN */ + MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN2 -- STBY */ + MX53_PIN_GPIO_14, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN2 -- NERR */ + MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), }, { - MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1, + MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO, + }, + { /* ESAI reset */ + MX53_PIN_GPIO_12, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_SRE_FAST), }, { - MX53_PIN_GPIO_17, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO, }, { - MX53_PIN_GPIO_18, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1, }, { - MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3, + MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1, }, { /* DI0 display clock */ MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0, @@ -392,6 +427,36 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW), }, + { + MX53_PIN_LVDS0_TX3_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_CLK_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_TX2_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_TX1_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_TX0_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX3_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_CLK_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX2_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX1_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX0_P, IOMUX_CONFIG_ALT1, + }, { /* audio and CSI clock out */ MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3, }, @@ -450,68 +515,100 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { /* esdhc1 */ { MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, /* esdhc3 */ { MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { /* FEC pins */ MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0, @@ -556,6 +653,38 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, }, + { /* I2C1 SDA */ + MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* I2C1 SCL */ + MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* I2C2 SDA */ + MX53_PIN_KEY_ROW3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* I2C1 SCL */ + MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, }; static struct mxc_iomux_pin_cfg __initdata mx53_evk_iomux_pins[] = { @@ -631,11 +760,87 @@ static int __initdata enable_w1 = { 0 }; static int __init w1_setup(char *__unused) { enable_w1 = 1; - return 1; + return cpu_is_mx53(); } __setup("w1", w1_setup); +static struct mxc_iomux_pin_cfg __initdata nand_iomux_pins[] = { + { + MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU, + }, + { + MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU, + }, + { + MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, +}; + +static int __initdata enable_spdif = { 0 }; +static int __init spdif_setup(char *__unused) +{ + enable_spdif = 1; + return 1; +} + +__setup("spdif", spdif_setup); + void __init mx53_evk_io_init(void) { int i; @@ -665,12 +870,12 @@ void __init mx53_evk_io_init(void) mx53_arm2_iomux_pins[i].in_mode); } - /* Enable OTG VBus with GPIO low */ + /* Config GPIO for OTG VBus */ mxc_iomux_set_pad(MX53_PIN_EIM_D22, PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), "gpio3_22"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1); gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1"); gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); /* SD1 CD */ @@ -696,6 +901,9 @@ void __init mx53_evk_io_init(void) PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + /* shutdown the Host1 Vbus when system bring up, + * Vbus will be opened in Host1 driver's probe function */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); /* USB HUB RESET - De-assert USB HUB RESET_N */ mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH | @@ -708,12 +916,16 @@ void __init mx53_evk_io_init(void) msleep(1); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1); - /* Enable OTG VBus with GPIO low */ + /* Config GPIO for OTG VBus */ mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + + if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1); + else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13"); gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); /* SD1 CD */ @@ -735,70 +947,42 @@ void __init mx53_evk_io_init(void) msleep(1); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1); - /* DVI Detect */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31"); - gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31)); - /* DVI Reset - Assert for i2c disabled mode */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0"); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); - /* DVI Power-down */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24"); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1); - /* DVI I2C enable */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28"); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); + /* CS42888 reset GPIO */ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0); + } + /* DVI Detect */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31)); + /* DVI Reset - Assert for i2c disabled mode */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0"); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); + /* DVI Power-down */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1); + /* DVI I2C enable */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); + + for (i = 0; i < ARRAY_SIZE(nand_iomux_pins); i++) { + mxc_request_iomux(nand_iomux_pins[i].pin, + nand_iomux_pins[i].mux_mode); + if (nand_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(nand_iomux_pins[i].pin, + nand_iomux_pins[i].pad_cfg); + if (nand_iomux_pins[i].in_select) + mxc_iomux_set_input(nand_iomux_pins[i].in_select, + nand_iomux_pins[i].in_mode); + } gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11"); gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16)); /*PMIC_INT*/ - - /* i2c1 SDA */ - mxc_request_iomux(MX53_PIN_CSI0_D8, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - - /* i2c1 SCL */ - mxc_request_iomux(MX53_PIN_CSI0_D9, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - - /* i2c2 SDA */ - mxc_request_iomux(MX53_PIN_KEY_ROW3, - IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, - PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - - /* i2c2 SCL */ - mxc_request_iomux(MX53_PIN_KEY_COL3, - IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_KEY_COL3, - PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - /* headphone_det_b */ mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU); @@ -814,36 +998,82 @@ void __init mx53_evk_io_init(void) gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1); - /* Camera low power */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23"); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); + /* TVIN reset */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), "gpio5_25"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0); + msleep(5); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 1); + + /* CAN1 enable GPIO*/ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0); + + /* CAN2 enable GPIO*/ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0); + + if (enable_spdif) { + mxc_free_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_GPIO_19, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | + PAD_CTL_PKE_ENABLE); + } else { + /* GPIO for CAN 12V */ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0); + } } /* workaround for ecspi chipselect pin may not keep correct level when idle */ void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, int chipselect) { - u32 gpio; - switch (cspi_mode) { case 1: switch (chipselect) { case 0x1: - mxc_request_iomux(MX53_PIN_EIM_D19, - IOMUX_CONFIG_ALT4); + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1); mxc_iomux_set_pad(MX53_PIN_EIM_D19, PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + + /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + INPUT_CTL_PATH3); break; case 0x2: - gpio = IOMUX_TO_GPIO(MX53_PIN_EIM_D19); - mxc_request_iomux(MX53_PIN_EIM_D19, - IOMUX_CONFIG_GPIO); - gpio_request(gpio, "cspi1_ss1"); - gpio_direction_output(gpio, 0); - gpio_set_value(gpio, 1 & (~status)); + /* de-select SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + INPUT_CTL_PATH3); + break; default: break; @@ -870,9 +1100,14 @@ void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); break; case 0x2: - mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_EIM_EB2, + IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); break; default: break; @@ -888,8 +1123,201 @@ void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, } EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_inactive); +void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + if (id < 0 || id > 1) + return; + + if (en) { + if (!(pwdn++)) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 1); + + if (id == 0) { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 1); + } else { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 1); + } + + } else { + if (!(--pwdn)) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0); + + if (id == 0) { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0); + } else { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0); + } + } +} +EXPORT_SYMBOL(flexcan_xcvr_enable); + void gpio_lcd_active(void) { /* TO DO */ } EXPORT_SYMBOL(gpio_lcd_active); + +void gpio_activate_esai_ports(void) +{ + unsigned int pad_val; + + /* ESAI1-HCKR */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT2); + /* ESAI1-SCKR */ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT2); + /* ESAI1-FSR */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT2); + /* ESAI1-HCKT */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT2); + /* ESAI1-SCKT */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT2); + /* ESAI1-FST */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT2); + /* ESAI1-TX5-RX0 */ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT2); + /* ESAI1-TX4-RX1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT2); + /* ESAI1-TX3-RX2 */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT2); + /* ESAI1-TX2-RX3 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT2); + /* ESAI1-TX1 */ + mxc_request_iomux(MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3); + /* ESAI1-TX0 */ + mxc_request_iomux(MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3); + + pad_val = PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE; + + /* ESAI1-HCKR */ + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, pad_val); + /* ESAI1-SCKR */ + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, pad_val); + /* ESAI1-FSR */ + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, pad_val); + /* ESAI1-HCKT */ + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, pad_val); + /* ESAI1-SCKT */ + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, pad_val); + /* ESAI1-FST */ + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, pad_val); + /* ESAI1-TX5-RX0 */ + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, pad_val); + /* ESAI1-TX4-RX1 */ + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, pad_val); + /* ESAI1-TX3-RX2 */ + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, pad_val); + /* ESAI1-TX2-RX3 */ + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, pad_val); + /* ESAI1-TX1 */ + mxc_iomux_set_pad(MX53_PIN_NANDF_CS3, pad_val); + /* ESAI1-TX0 */ + mxc_iomux_set_pad(MX53_PIN_NANDF_CS2, pad_val); + + /* ESAI1-HCKR */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-SCKR */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-FSR */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-HCKT */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-SCKT */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-FST */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX5-RX0 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX4-RX1 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX3-RX2 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX2-RX3 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX1 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX0 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT, + INPUT_CTL_PATH0); + +} +EXPORT_SYMBOL(gpio_activate_esai_ports); + +void gpio_cs42888_pdwn(int pdwn) +{ + if (pdwn) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0); + else + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 1); +} +EXPORT_SYMBOL(gpio_cs42888_pdwn); + +static void gpio_usbotg_vbus_active(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Enable OTG VBus with GPIO high */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1); + } +} + +static void gpio_usbotg_vbus_inactive(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Disable OTG VBus with GPIO low */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + } +} + + +void mx53_gpio_usbotg_driver_vbus(bool on) +{ + if (on) + gpio_usbotg_vbus_active(); + else + gpio_usbotg_vbus_inactive(); +} +EXPORT_SYMBOL(mx53_gpio_usbotg_driver_vbus); + +void mx53_gpio_host1_driver_vbus(bool on) +{ + if (on) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + else + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); +} +EXPORT_SYMBOL(mx53_gpio_host1_driver_vbus); |