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Diffstat (limited to 'arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c')
-rw-r--r--arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c b/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c
index 6e7ea3e27a2e..14f28a9ceeda 100644
--- a/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c
+++ b/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c
@@ -395,6 +395,36 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
},
/* TODO: Enable CTS/RTS if selected */
#endif
+#if defined(CONFIG_SMSC911X)
+ {MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0,
+ (PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_MEDIUM), },
+ {MX51_PIN_EIM_OE, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA0, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA1, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA2, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA3, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA4, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA5, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA6, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_DA7, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D24, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D28, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D29, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D30, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_EIM_D31, IOMUX_CONFIG_ALT0,},
+ {MX51_PIN_GPIO1_9, IOMUX_CONFIG_ALT0, (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), },
+#endif
};
void __init mx51_ccwmx51js_io_init(void)