13 files changed, 814 insertions, 217 deletions

diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
index 8c1d754f02a2..5acdcb3a5435 100644
--- a/arch/arm/mach-mx6/Makefile
+++ b/arch/arm/mach-mx6/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
 obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
-obj-$(CONFIG_MACH_MX6Q_HDMIDONGLE) += board-mx6q_hdmidongle.o
+obj-$(CONFIG_MACH_MX6Q_HDMIDONGLE) += board-mx6q_hdmidongle.o mx6q_hdmidongle_pmic_wm831x.o
 obj-$(CONFIG_SMP) += plat_hotplug.o platsmp.o headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_IMX_PCIE) += pcie.o
diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index 97b601de2ddd..8a2687d04f36 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -45,6 +45,7 @@
 #include <linux/fec.h>
 #include <linux/memblock.h>
 #include <linux/gpio.h>
+#include <linux/ion.h>
 #include <linux/etherdevice.h>
 #include <linux/regulator/anatop-regulator.h>
 #include <linux/regulator/consumer.h>
@@ -1270,7 +1271,7 @@ static void __init mx6_arm2_init_usb(void)
 }
 
 static struct viv_gpu_platform_data imx6_gpu_pdata __initdata = {
-	.reserved_mem_size = SZ_128M,
+	.reserved_mem_size = SZ_128M + SZ_64M,
 };
 
 /* HW Initialization, if return 0, initialization is successful. */
@@ -1518,6 +1519,17 @@ static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data = {
 	.pwm_period_ns	= 50000,
 };
 
+static struct ion_platform_data imx_ion_data = {
+	.nr = 1,
+	.heaps = {
+		{
+		.type = ION_HEAP_TYPE_CARVEOUT,
+		.name = "vpu_ion",
+		.size = SZ_64M,
+		},
+	},
+};
+
 static struct gpio mx6_flexcan_gpios[] = {
 	{ MX6_ARM2_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
 	{ MX6_ARM2_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" },
@@ -1941,6 +1953,21 @@ static struct mxc_dvfs_platform_data arm2_dvfscore_data = {
 static void __init mx6_arm2_fixup(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
+	char *str;
+	struct tag *t;
+
+	for_each_tag(t, tags) {
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			/* GPU reserved memory */
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "gpumem=");
+			if (str != NULL) {
+				str += 7;
+				imx6_gpu_pdata.reserved_mem_size = memparse(str, &str);
+			}
+			break;
+		}
+	}
 }
 
 static int __init early_enable_sgtl5000(char *p)
@@ -2235,6 +2262,9 @@ static void __init mx6_arm2_init(void)
 
 	imx6q_add_dvfs_core(&arm2_dvfscore_data);
 
+	imx6q_add_ion(0, &imx_ion_data,
+		sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
+
 	imx6q_add_mxc_pwm(0);
 	imx6q_add_mxc_pwm_backlight(0, &mx6_arm2_pwm_backlight_data);
 
@@ -2295,9 +2325,8 @@ static struct sys_timer mxc_timer = {
 
 static void __init mx6_arm2_reserve(void)
 {
-#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	phys_addr_t phys;
-
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	if (imx6_gpu_pdata.reserved_mem_size) {
 		phys = memblock_alloc_base(
 			imx6_gpu_pdata.reserved_mem_size, SZ_4K, SZ_2G);
@@ -2305,6 +2334,15 @@ static void __init mx6_arm2_reserve(void)
 		imx6_gpu_pdata.reserved_mem_base = phys;
 	}
 #endif
+
+#if defined(CONFIG_ION)
+	if (imx_ion_data.heaps[0].size) {
+		phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K);
+		memblock_free(phys, imx_ion_data.heaps[0].size);
+		memblock_remove(phys, imx_ion_data.heaps[0].size);
+		imx_ion_data.heaps[0].base = phys;
+	}
+#endif
 }
 
 MACHINE_START(MX6Q_ARM2, "Freescale i.MX 6Quad/Solo/DualLite Armadillo2 Board")
diff --git a/arch/arm/mach-mx6/board-mx6q_hdmidongle.c b/arch/arm/mach-mx6/board-mx6q_hdmidongle.c
index ffd8d9afef6a..e88383b339dd 100644
--- a/arch/arm/mach-mx6/board-mx6q_hdmidongle.c
+++ b/arch/arm/mach-mx6/board-mx6q_hdmidongle.c
@@ -45,6 +45,7 @@
 #include <linux/fec.h>
 #include <linux/memblock.h>
 #include <linux/gpio.h>
+#include <linux/ion.h>
 #include <linux/etherdevice.h>
 #include <linux/regulator/anatop-regulator.h>
 #include <linux/regulator/consumer.h>
@@ -67,12 +68,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <mach/common.h>
 
-#ifdef CONFIG_MFD_WM831X
-#include <linux/mfd/wm831x/core.h>
-#include <linux/mfd/wm831x/pdata.h>
-#include <linux/mfd/wm831x/regulator.h>
-#include <linux/mfd/wm831x/gpio.h>
+#ifdef CONFIG_IMX_PCIE
+#include <linux/wakelock.h>
 #endif
 
 #include "usb.h"
@@ -98,7 +97,7 @@
 
 #ifdef CONFIG_IMX_PCIE
 #define HDMIDONGLE_PCIE_PWR_EN	IMX_GPIO_NR(3, 7) /*fake pcie power enable */
-#define HDMIDONGLE_PCIE_RST     IMX_GPIO_NR(3, 9)
+#define HDMIDONGLE_PCIE_RST 	IMX_GPIO_NR(3, 9)
 #define HDMIDONGLE_PCIE_WAKE	IMX_GPIO_NR(3, 22)
 #define HDMIDONGLE_PCIE_DIS		IMX_GPIO_NR(3, 10)
 #endif
@@ -185,115 +184,6 @@ static inline void mx6q_hdmidongle_init_uart(void)
 	imx6q_add_imx_uart(3, NULL);
 }
 
-static int mx6q_hdmidongle_spi_cs[] = {
-	HDMIDONGLE_ECSPI2_CS0,
-};
-
-static const struct spi_imx_master mx6q_hdmidongle_spi_data __initconst = {
-	.chipselect     = mx6q_hdmidongle_spi_cs,
-	.num_chipselect = ARRAY_SIZE(mx6q_hdmidongle_spi_cs),
-};
-
-
-
-#ifdef CONFIG_MFD_WM831X
-#if 0
-/* 1.4125, 1.4125. 1.5 */
-#define WM831X_DC1_ON_CONFIG_VAL            (0x48<<WM831X_DC1_ON_VSEL_SHIFT)
-#define WM831X_DC2_ON_CONFIG_VAL            (0x48<<WM831X_DC2_ON_VSEL_SHIFT)
-#define WM831X_DC3_ON_CONFIG_VAL            (0x1A<<WM831X_DC3_ON_VSEL_SHIFT)
-#else
-/* 1.375, 1.375. 1.5 */
-
-#define WM831X_DC1_ON_CONFIG_VAL            (0x44<<WM831X_DC1_ON_VSEL_SHIFT)
-#define WM831X_DC2_ON_CONFIG_VAL            (0x44<<WM831X_DC2_ON_VSEL_SHIFT)
-#define WM831X_DC3_ON_CONFIG_VAL            (0x1A<<WM831X_DC3_ON_VSEL_SHIFT)
-
-#endif
-
-#define WM831X_DC1_DVS_MODE_VAL             (0x02<<WM831X_DC1_DVS_SRC_SHIFT)
-#define WM831X_DC2_DVS_MODE_VAL             (0x02<<WM831X_DC2_DVS_SRC_SHIFT)
-
-#define WM831X_DC1_DVS_CONTROL_VAL           (0x20<<WM831X_DC1_DVS_VSEL_SHIFT)
-#define WM831X_DC2_DVS_CONTROL_VAL           (0x20<<WM831X_DC2_DVS_VSEL_SHIFT)
-
-#define WM831X_DC1_DVS_MASK                  (WM831X_DC1_DVS_SRC_MASK|WM831X_DC1_DVS_VSEL_MASK)
-#define WM831X_DC2_DVS_MASK                  (WM831X_DC2_DVS_SRC_MASK|WM831X_DC1_DVS_VSEL_MASK)
-
-#define WM831X_DC1_DVS_VAL                   (WM831X_DC1_DVS_MODE_VAL|WM831X_DC1_DVS_CONTROL_VAL)
-#define WM831X_DC2_DVS_VAL                   (WM831X_DC2_DVS_MODE_VAL|WM831X_DC2_DVS_CONTROL_VAL)
-
-#define WM831X_GPN_FN_VAL_HW_EN              (0x0A<<WM831X_GPN_FN_SHIFT)
-#define WM831X_GPN_FN_VAL_HW_CTL             (0x0C<<WM831X_GPN_FN_SHIFT)
-#define WM831X_GPN_FN_VAL_DVS1               (0x08<<WM831X_GPN_FN_SHIFT)
-
-#define WM831X_GPN_DIR_VAL                   (0x1<<WM831X_GPN_DIR_SHIFT)
-#define WM831X_GPN_PULL_VAL                  (0x3<<WM831X_GPN_PULL_SHIFT)
-#define WM831X_GPN_INT_MODE_VAL              (0x1<<WM831X_GPN_INT_MODE_SHIFT)
-#define WM831X_GPN_POL_VAL                   (0x1<<WM831X_GPN_POL_SHIFT)
-#define WM831X_GPN_ENA_VAL                   (0x1<<WM831X_GPN_ENA_SHIFT)
-
-#define WM831X_GPIO7_8_9_MASK               (WM831X_GPN_DIR_MASK|WM831X_GPN_INT_MODE_MASK|WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_FN_MASK)
-
-
-#define WM831X_GPIO7_VAL                     (WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL|WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_HW_EN)
-#define WM831X_GPIO8_VAL                     (WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL|WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_HW_CTL)
-#define WM831X_GPIO9_VAL                     (WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL|WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_DVS1)
-
-#define WM831X_STATUS_LED_MASK                0xC000
-#define WM831X_STATUS_LED_ON                  (0x1 << 14)
-#define WM831X_STATUS_LED_OFF                 (0x0 << 14)
-
-static int wm8326_post_init(struct wm831x *wm831x)
-{
-	wm831x_set_bits(wm831x, WM831X_DC1_ON_CONFIG, WM831X_DC1_ON_VSEL_MASK, WM831X_DC1_ON_CONFIG_VAL);
-	wm831x_set_bits(wm831x, WM831X_DC2_ON_CONFIG, WM831X_DC2_ON_VSEL_MASK, WM831X_DC2_ON_CONFIG_VAL);
-	wm831x_set_bits(wm831x, WM831X_DC3_ON_CONFIG, WM831X_DC3_ON_VSEL_MASK, WM831X_DC3_ON_CONFIG_VAL);
-
-	wm831x_set_bits(wm831x, WM831X_DC1_DVS_CONTROL, WM831X_DC1_DVS_MASK, WM831X_DC1_DVS_VAL);
-	wm831x_set_bits(wm831x, WM831X_DC2_DVS_CONTROL, WM831X_DC2_DVS_MASK, WM831X_DC2_DVS_VAL);
-
-	wm831x_set_bits(wm831x, WM831X_GPIO7_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO7_VAL);
-	wm831x_set_bits(wm831x, WM831X_GPIO8_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO8_VAL);
-	wm831x_set_bits(wm831x, WM831X_GPIO9_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO9_VAL);
-
-    wm831x_set_bits(wm831x, WM831X_STATUS_LED_1 , WM831X_STATUS_LED_MASK, WM831X_STATUS_LED_OFF);
-    wm831x_set_bits(wm831x, WM831X_STATUS_LED_2 , WM831X_STATUS_LED_MASK, WM831X_STATUS_LED_ON);
-	return 0;
-}
-
-static struct wm831x_pdata hdmidongle_wm8326_pdata = {
-	.post_init = wm8326_post_init,
-};
-#endif
-
-static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
-	{
-#ifdef CONFIG_MFD_WM831X
-	I2C_BOARD_INFO("wm8326", 0x34),
-	.platform_data = &hdmidongle_wm8326_pdata,
-#endif
-	},
-};
-
-static struct spi_board_info wm8326_spi1_board_info[] __initdata = {
-#if defined(CONFIG_MFD_WM831X_SPI)
-	{
-	/* The modalias must be the same as spi device driver name */
-	.modalias	= "wm8326",
-	.max_speed_hz	= 20000000,
-	.bus_num	= 1,
-	.chip_select	= 0,
-	},
-#endif
-};
-
-static void spi_device_init(void)
-{
-	spi_register_board_info(wm8326_spi1_board_info,
-				ARRAY_SIZE(wm8326_spi1_board_info));
-}
-
 static struct imxi2c_platform_data mx6q_hdmidongle_i2c_data = {
 	.bitrate = 100000,
 };
@@ -431,6 +321,18 @@ static struct imx_ipuv3_platform_data ipu_data[] = {
 	},
 };
 
+static struct ion_platform_data imx_ion_data = {
+	.nr = 1,
+	.heaps = {
+		{
+		.id = 0,
+		.type = ION_HEAP_TYPE_CARVEOUT,
+		.name = "vpu_ion",
+		.size = SZ_64M,
+		},
+	},
+};
+
 static void hdmidongle_suspend_enter(void)
 {
 	/* suspend preparation */
@@ -534,7 +436,8 @@ static void __init imx6q_add_device_buttons(void) {}
 
 static struct mxc_dvfs_platform_data hdmidongle_dvfscore_data = {
 	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
-	.reg_id = "VDDCORE",
+	.reg_id = "VDDCORE_DCDC1",
+	.soc_id = "VDDSOC_DCDC2",
 	#else
 	.reg_id = "cpu_vddgp",
 	.soc_id = "cpu_vddsoc",
@@ -632,7 +535,6 @@ static void __init mx6_hdmidongle_board_init(void)
 
 	gp_reg_id = hdmidongle_dvfscore_data.reg_id;
 	soc_reg_id = hdmidongle_dvfscore_data.soc_id;
-	pu_reg_id = hdmidongle_dvfscore_data.pu_id;
 	mx6q_hdmidongle_init_uart();
 
 	/*
@@ -665,14 +567,7 @@ static void __init mx6_hdmidongle_board_init(void)
 	i2c_register_board_info(1, mxc_i2c1_board_info,
 			ARRAY_SIZE(mxc_i2c1_board_info));
 
-
-	i2c_register_board_info(2, mxc_i2c2_board_info,
-			ARRAY_SIZE(mxc_i2c2_board_info));
-
-
-	/* SPI */
-	imx6q_add_ecspi(1, &mx6q_hdmidongle_spi_data);
-	spi_device_init();
+	mx6q_hdmidongle_init_wm8326();
 
 	imx6q_add_mxc_hdmi(&hdmi_data);
 
@@ -707,6 +602,9 @@ static void __init mx6_hdmidongle_board_init(void)
 	mx6_cpu_regulator_init();
 	#endif
 
+	imx6q_add_ion(0, &imx_ion_data,
+		sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
+
 	imx6q_add_device_buttons();
 
 	imx6q_add_hdmi_soc();
@@ -716,19 +614,19 @@ static void __init mx6_hdmidongle_board_init(void)
 		gpio_request(HDMIDONGLE_BT_RST, "bt_reset");
 		gpio_direction_output(HDMIDONGLE_BT_RST, 1);
 		gpio_set_value(HDMIDONGLE_BT_RST, 1);
-		msleep(1000);
+		mdelay(1000);
 		gpio_request(HDMIDONGLE_BT_EN, "bt_en");
 		gpio_direction_output(HDMIDONGLE_BT_EN, 1);
 		gpio_set_value(HDMIDONGLE_BT_EN, 1);
 
-		msleep(1000);
+		mdelay(1000);
 		gpio_request(HDMIDONGLE_WL_EN, "wl_en");
 		gpio_direction_output(HDMIDONGLE_WL_EN, 1);
 		gpio_set_value(HDMIDONGLE_WL_EN, 1);
-		msleep(1000);
+		mdelay(1000);
+#ifdef CONFIG_IMX_PCIE
 	} else if (board_is_mx6_revb() || board_is_mx6_revc()) {
 		/* Add PCIe RC interface support */
-#ifdef CONFIG_IMX_PCIE
 		imx6q_add_pcie(&mx6_hdmidongle_pcie_data);
 #endif
 	}
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index fb590f576a0d..45f4af592ab9 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -46,6 +46,7 @@
 #include <linux/fec.h>
 #include <linux/memblock.h>
 #include <linux/gpio.h>
+#include <linux/ion.h>
 #include <linux/etherdevice.h>
 #include <linux/regulator/anatop-regulator.h>
 #include <linux/regulator/consumer.h>
@@ -92,7 +93,7 @@
 #define SABREAUTO_USB_OTG_OC		IMX_GPIO_NR(2, 8)
 #define SABREAUTO_LDB_BACKLIGHT3	IMX_GPIO_NR(2, 9)
 #define SABREAUTO_LDB_BACKLIGHT4	IMX_GPIO_NR(2, 10)
-#define SABREAUTO_ANDROID_MENU		IMX_GPIO_NR(2, 12)
+#define SABREAUTO_ANDROID_POWER		IMX_GPIO_NR(2, 12)
 #define SABREAUTO_ANDROID_VOLUP		IMX_GPIO_NR(2, 15)
 #define SABREAUTO_CAP_TCH_INT		IMX_GPIO_NR(2, 28)
 #define SABREAUTO_eCOMPASS_INT		IMX_GPIO_NR(2, 29)
@@ -201,9 +202,9 @@ enum sd_pad_mode {
 static struct gpio_keys_button ard_buttons[] = {
 	GPIO_BUTTON(SABREAUTO_ANDROID_HOME,    KEY_HOME,       1, "home",        0),
 	GPIO_BUTTON(SABREAUTO_ANDROID_BACK,    KEY_BACK,       1, "back",        0),
-	GPIO_BUTTON(SABREAUTO_ANDROID_MENU,    KEY_MENU,       1, "menu",        0),
 	GPIO_BUTTON(SABREAUTO_ANDROID_VOLUP,   KEY_VOLUMEUP,   1, "volume-up",   0),
 	GPIO_BUTTON(SABREAUTO_ANDROID_VOLDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
+	GPIO_BUTTON(SABREAUTO_ANDROID_POWER,   KEY_POWER,      1, "power-key",   1),
 };
 
 static struct gpio_keys_platform_data ard_android_button_data = {
@@ -296,12 +297,16 @@ static const struct esdhc_platform_data mx6q_sabreauto_sd3_data __initconst = {
 	.support_8bit		= 1,
 	.delay_line		= 0,
 	.platform_pad_change	= plt_sd_pad_change,
+	.cd_type = ESDHC_CD_CONTROLLER,
+	.runtime_pm = 1,
 };
 
 static const struct esdhc_platform_data mx6q_sabreauto_sd1_data __initconst = {
 	.cd_gpio = SABREAUTO_SD1_CD,
 	.wp_gpio = SABREAUTO_SD1_WP,
 	.keep_power_at_suspend = 1,
+	.cd_type = ESDHC_CD_CONTROLLER,
+	.runtime_pm = 1,
 };
 
 
@@ -873,7 +878,7 @@ static void __init imx6q_sabreauto_init_usb(void)
 }
 
 static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
-	.reserved_mem_size = SZ_128M,
+	.reserved_mem_size = SZ_128M + SZ_64M,
 };
 
 /* HW Initialization, if return 0, initialization is successful. */
@@ -1014,6 +1019,8 @@ static struct ipuv3_fb_platform_data sabr_fb_data[] = {
 static void hdmi_init(int ipu_id, int disp_id)
 {
 	int hdmi_mux_setting;
+	char ipu_di_clk[] = "ipu1_di0_clk";
+	struct clk *di_clk, *pll5_clk;
 
 	if ((ipu_id > 1) || (ipu_id < 0)) {
 		printk(KERN_ERR"Invalid IPU select for HDMI: %d. Set to 0\n",
@@ -1036,6 +1043,16 @@ static void hdmi_init(int ipu_id, int disp_id)
 	/* Set HDMI event as SDMA event2 while Chip version later than TO1.2 */
 	if (hdmi_SDMA_check())
 		mxc_iomux_set_gpr_register(0, 0, 1, 1);
+
+	ipu_di_clk[3] += ipu_id;
+	ipu_di_clk[7] += disp_id;
+	di_clk = clk_get(NULL, ipu_di_clk);
+	if (IS_ERR(di_clk))
+		printk(KERN_ERR "Cannot get %s clock\n", ipu_di_clk);
+	pll5_clk = clk_get(NULL, "pll5");
+	if (IS_ERR(pll5_clk))
+		printk(KERN_ERR "Cannot get pll5 clock\n");
+	clk_set_parent(di_clk, pll5_clk);
 }
 
 /* On mx6x sabreauto board i2c2 iomux with hdmi ddc,
@@ -1106,6 +1123,17 @@ static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data3 = {
 	.pwm_period_ns		= 50000,
 };
 
+static struct ion_platform_data imx_ion_data = {
+	.nr = 1,
+	.heaps = {
+		{
+		.type = ION_HEAP_TYPE_CARVEOUT,
+		.name = "vpu_ion",
+		.size = SZ_64M,
+		},
+	},
+};
+
 /* Backlight PWM for Main board lvds*/
 static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data4 = {
 	.pwm_id			= 3,
@@ -1402,6 +1430,34 @@ static struct mxc_dvfs_platform_data sabreauto_dvfscore_data = {
 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
+	char *str;
+	struct tag *t;
+	int i = 0;
+	struct ipuv3_fb_platform_data *pdata_fb = sabr_fb_data;
+
+	for_each_tag(t, tags) {
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "fbmem=");
+			if (str != NULL) {
+				str += 6;
+				pdata_fb[i++].res_size[0] = memparse(str, &str);
+				while (*str == ',' &&
+					i < ARRAY_SIZE(sabr_fb_data)) {
+					str++;
+					pdata_fb[i++].res_size[0] = memparse(str, &str);
+				}
+			}
+			/* GPU reserved memory */
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "gpumem=");
+			if (str != NULL) {
+				str += 7;
+				imx6q_gpu_pdata.reserved_mem_size = memparse(str, &str);
+			}
+			break;
+		}
+	}
 }
 
 static int __init early_enable_mipi_sensor(char *p)
@@ -1736,6 +1792,8 @@ static void __init mx6_board_init(void)
 
 	imx6q_add_dvfs_core(&sabreauto_dvfscore_data);
 
+	imx6q_add_ion(0, &imx_ion_data,
+		sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
 	imx6q_add_mxc_pwm(2);
 	imx6q_add_mxc_pwm(3);
 	imx6q_add_mxc_pwm_backlight(2, &mx6_arm2_pwm_backlight_data3);
@@ -1767,6 +1825,14 @@ static void __init mx6_board_init(void)
 	imx6q_add_perfmon(0);
 	imx6q_add_perfmon(1);
 	imx6q_add_perfmon(2);
+
+	/* acquire this irq is want to let touch driver failed to
+	 * request this irq gpio, and the driver will disable suspend
+	 * funtion, to workaround sabreauto board have isssue on gpio
+	 * of touch use. */
+	gpio_request(SABREAUTO_CAP_TCH_INT, "touch irq");
+	gpio_direction_input(SABREAUTO_CAP_TCH_INT);
+
 }
 
 extern void __iomem *twd_base;
@@ -1789,9 +1855,34 @@ static struct sys_timer mxc_timer = {
 
 static void __init mx6q_reserve(void)
 {
-#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	phys_addr_t phys;
+	int i, fb0_reserved = 0, fb_array_size;
 
+	/*
+	 * Reserve primary framebuffer memory if its base address
+	 * is set by kernel command line.
+	 */
+	fb_array_size = ARRAY_SIZE(sabr_fb_data);
+	if (fb_array_size > 0 && sabr_fb_data[0].res_base[0] &&
+	    sabr_fb_data[0].res_size[0]) {
+		memblock_reserve(sabr_fb_data[0].res_base[0],
+				 sabr_fb_data[0].res_size[0]);
+		memblock_remove(sabr_fb_data[0].res_base[0],
+				sabr_fb_data[0].res_size[0]);
+		sabr_fb_data[0].late_init = true;
+		ipu_data[ldb_data.ipu_id].bypass_reset = true;
+		fb0_reserved = 1;
+	}
+	for (i = fb0_reserved; i < fb_array_size; i++)
+		if (sabr_fb_data[i].res_size[0]) {
+			/* Reserve for other background buffer. */
+			phys = memblock_alloc(sabr_fb_data[i].res_size[0],
+						SZ_4K);
+			memblock_remove(phys, sabr_fb_data[i].res_size[0]);
+			sabr_fb_data[i].res_base[0] = phys;
+		}
+
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	if (imx6q_gpu_pdata.reserved_mem_size) {
 		phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
 			SZ_4K, SZ_2G);
@@ -1799,6 +1890,15 @@ static void __init mx6q_reserve(void)
 		imx6q_gpu_pdata.reserved_mem_base = phys;
 	}
 #endif
+
+#if defined(CONFIG_ION)
+	if (imx_ion_data.heaps[0].size) {
+		phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K);
+		memblock_free(phys, imx_ion_data.heaps[0].size);
+		memblock_remove(phys, imx_ion_data.heaps[0].size);
+		imx_ion_data.heaps[0].base = phys;
+	}
+#endif
 }
 
 MACHINE_START(MX6Q_SABREAUTO, "Freescale i.MX 6Quad/DualLite/Solo Sabre Auto Board")
diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
index e1075fec4b68..338c16ab6a52 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
@@ -45,6 +45,7 @@
 #include <linux/fec.h>
 #include <linux/memblock.h>
 #include <linux/gpio.h>
+#include <linux/ion.h>
 #include <linux/etherdevice.h>
 #include <linux/regulator/anatop-regulator.h>
 #include <linux/regulator/consumer.h>
@@ -791,7 +792,7 @@ static const struct flexcan_platform_data
 };
 
 static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
-	.reserved_mem_size = SZ_128M,
+	.reserved_mem_size = SZ_128M + SZ_64M,
 };
 
 static struct imx_asrc_platform_data imx_asrc_data = {
@@ -904,6 +905,17 @@ static struct imx_ipuv3_platform_data ipu_data[] = {
 	},
 };
 
+static struct ion_platform_data imx_ion_data = {
+	.nr = 1,
+	.heaps = {
+		{
+		.type = ION_HEAP_TYPE_CARVEOUT,
+		.name = "vpu_ion",
+		.size = SZ_64M,
+		},
+	},
+};
+
 static struct fsl_mxc_capture_platform_data capture_data[] = {
 	{
 		.csi = 0,
@@ -1128,6 +1140,34 @@ static struct mxc_dvfs_platform_data sabrelite_dvfscore_data = {
 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
+	char *str;
+	struct tag *t;
+	int i = 0;
+	struct ipuv3_fb_platform_data *pdata_fb = sabrelite_fb_data;
+
+	for_each_tag(t, tags) {
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "fbmem=");
+			if (str != NULL) {
+				str += 6;
+				pdata_fb[i++].res_size[0] = memparse(str, &str);
+				while (*str == ',' &&
+					i < ARRAY_SIZE(sabrelite_fb_data)) {
+					str++;
+					pdata_fb[i++].res_size[0] = memparse(str, &str);
+				}
+			}
+			/* GPU reserved memory */
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "gpumem=");
+			if (str != NULL) {
+				str += 7;
+				imx6q_gpu_pdata.reserved_mem_size = memparse(str, &str);
+			}
+			break;
+		}
+	}
 }
 
 static struct mipi_csi2_platform_data mipi_csi2_pdata = {
@@ -1139,6 +1179,26 @@ static struct mipi_csi2_platform_data mipi_csi2_pdata = {
 	.pixel_clk = "emi_clk",
 };
 
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+static struct resource ram_console_resource = {
+	.name = "android ram console",
+	.flags = IORESOURCE_MEM,
+};
+
+static struct platform_device android_ram_console = {
+	.name = "ram_console",
+	.num_resources = 1,
+	.resource = &ram_console_resource,
+};
+
+static int __init imx6x_add_ram_console(void)
+{
+	return platform_device_register(&android_ram_console);
+}
+#else
+#define imx6x_add_ram_console() do {} while (0)
+#endif
+
 static int __init caam_setup(char *__unused)
 {
 	caam_enabled = 1;
@@ -1253,6 +1313,9 @@ static void __init mx6_sabrelite_board_init(void)
 
 	imx6q_add_dvfs_core(&sabrelite_dvfscore_data);
 
+	imx6q_add_ion(0, &imx_ion_data,
+		sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
+
 	sabrelite_add_device_buttons();
 
 	imx6q_add_hdmi_soc();
@@ -1304,9 +1367,18 @@ static struct sys_timer mx6_sabrelite_timer = {
 
 static void __init mx6q_sabrelite_reserve(void)
 {
-#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	phys_addr_t phys;
+	int i;
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+	phys = memblock_alloc_base(SZ_128K, SZ_4K, SZ_1G);
+	memblock_remove(phys, SZ_128K);
+	memblock_free(phys, SZ_128K);
+	ram_console_resource.start = phys;
+	ram_console_resource.end   = phys + SZ_128K - 1;
+#endif
 
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	if (imx6q_gpu_pdata.reserved_mem_size) {
 		phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
 					   SZ_4K, SZ_1G);
@@ -1314,6 +1386,23 @@ static void __init mx6q_sabrelite_reserve(void)
 		imx6q_gpu_pdata.reserved_mem_base = phys;
 	}
 #endif
+
+#if defined(CONFIG_ION)
+	if (imx_ion_data.heaps[0].size) {
+		phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K);
+		memblock_remove(phys, imx_ion_data.heaps[0].size);
+		imx_ion_data.heaps[0].base = phys;
+	}
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(sabrelite_fb_data); i++)
+		if (sabrelite_fb_data[i].res_size[0]) {
+			/* reserve for background buffer */
+			phys = memblock_alloc(sabrelite_fb_data[i].res_size[0],
+						SZ_4K);
+			memblock_remove(phys, sabrelite_fb_data[i].res_size[0]);
+			sabrelite_fb_data[i].res_base[0] = phys;
+		}
 }
 
 /*
diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
index ac9b8f8391d9..9971ff55a765 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
@@ -45,6 +45,7 @@
 #include <linux/fec.h>
 #include <linux/memblock.h>
 #include <linux/gpio.h>
+#include <linux/ion.h>
 #include <linux/etherdevice.h>
 #include <linux/power/sabresd_battery.h>
 #include <linux/regulator/anatop-regulator.h>
@@ -82,8 +83,10 @@
 #include "cpu_op-mx6.h"
 #include "board-mx6q_sabresd.h"
 #include "board-mx6dl_sabresd.h"
+#include <mach/imx_rfkill.h>
 
 #define SABRESD_USR_DEF_GRN_LED	IMX_GPIO_NR(1, 1)
+#define SABRESD_BT_RESET	IMX_GPIO_NR(1, 2)
 #define SABRESD_USR_DEF_RED_LED	IMX_GPIO_NR(1, 2)
 #define SABRESD_VOLUME_UP	IMX_GPIO_NR(1, 4)
 #define SABRESD_VOLUME_DN	IMX_GPIO_NR(1, 5)
@@ -207,10 +210,11 @@
 
 static struct clk *sata_clk;
 static struct clk *clko;
-static int mma8451_position = 1;
-static int mag3110_position = 2;
+static int mma8451_position;
+static int mag3110_position = 1;
 static int max11801_mode = 1;
 static int caam_enabled;
+static int uart5_enabled;
 
 extern char *gp_reg_id;
 extern char *soc_reg_id;
@@ -226,6 +230,7 @@ static const struct esdhc_platform_data mx6q_sabresd_sd2_data __initconst = {
 	.support_8bit = 1,
 	.delay_line = 0,
 	.cd_type = ESDHC_CD_CONTROLLER,
+	.runtime_pm = 1,
 };
 
 static const struct esdhc_platform_data mx6q_sabresd_sd3_data __initconst = {
@@ -235,6 +240,7 @@ static const struct esdhc_platform_data mx6q_sabresd_sd3_data __initconst = {
 	.support_8bit = 1,
 	.delay_line = 0,
 	.cd_type = ESDHC_CD_CONTROLLER,
+	.runtime_pm = 1,
 };
 
 static const struct esdhc_platform_data mx6q_sabresd_sd4_data __initconst = {
@@ -250,6 +256,12 @@ static const struct anatop_thermal_platform_data
 		.name = "anatop_thermal",
 };
 
+static const struct imxuart_platform_data mx6q_sd_uart5_data __initconst = {
+	.flags      = IMXUART_HAVE_RTSCTS,
+	.dma_req_rx = MX6Q_DMA_REQ_UART5_RX,
+	.dma_req_tx = MX6Q_DMA_REQ_UART5_TX,
+};
+
 static inline void mx6q_sabresd_init_uart(void)
 {
 	imx6q_add_imx_uart(2, NULL);
@@ -851,6 +863,10 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 		I2C_BOARD_INFO("elan-touch", 0x10),
 		.irq = gpio_to_irq(SABRESD_ELAN_INT),
 	},
+	{
+		I2C_BOARD_INFO("mxc_ldb_i2c", 0x50),
+		.platform_data = (void *)1,	/* lvds port1 */
+	},
 };
 
 static int epdc_get_pins(void)
@@ -1244,7 +1260,7 @@ static const struct flexcan_platform_data
 };
 
 static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
-	.reserved_mem_size = SZ_128M,
+	.reserved_mem_size = SZ_128M + SZ_64M - SZ_16M,
 };
 
 static struct imx_asrc_platform_data imx_asrc_data = {
@@ -1283,22 +1299,16 @@ static struct ipuv3_fb_platform_data sabresd_fb_data[] = {
 	.int_clk = false,
 	.late_init = false,
 	}, {
-	.disp_dev = "ldb",
-	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
-	.mode_str = "LDB-XGA",
-	.default_bpp = 16,
-	.int_clk = false,
-	}, {
-	.disp_dev = "lcd",
-	.interface_pix_fmt = IPU_PIX_FMT_RGB565,
-	.mode_str = "CLAA-WVGA",
-	.default_bpp = 16,
+	.disp_dev = "hdmi",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB24,
+	.mode_str = "1920x1080M@60",
+	.default_bpp = 32,
 	.int_clk = false,
 	.late_init = false,
 	}, {
 	.disp_dev = "ldb",
 	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
-	.mode_str = "LDB-VGA",
+	.mode_str = "LDB-XGA",
 	.default_bpp = 16,
 	.int_clk = false,
 	.late_init = false,
@@ -1361,7 +1371,7 @@ static struct fsl_mxc_hdmi_platform_data hdmi_data = {
 };
 
 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
-	.ipu_id = 0,
+	.ipu_id = 1,
 	.disp_id = 0,
 };
 
@@ -1372,11 +1382,11 @@ static struct fsl_mxc_lcd_platform_data lcdif_data = {
 };
 
 static struct fsl_mxc_ldb_platform_data ldb_data = {
-	.ipu_id = 1,
+	.ipu_id = 0,
 	.disp_id = 1,
 	.ext_ref = 1,
 	.mode = LDB_SEP1,
-	.sec_ipu_id = 1,
+	.sec_ipu_id = 0,
 	.sec_disp_id = 0,
 };
 
@@ -1410,6 +1420,19 @@ static struct imx_ipuv3_platform_data ipu_data[] = {
 	},
 };
 
+static struct ion_platform_data imx_ion_data = {
+	.nr = 1,
+	.heaps = {
+		{
+		.id = 0,
+		.type = ION_HEAP_TYPE_CARVEOUT,
+		.name = "vpu_ion",
+		.size = SZ_16M,
+		.cacheable = 1,
+		},
+	},
+};
+
 static struct fsl_mxc_capture_platform_data capture_data[] = {
 	{
 		.csi = 0,
@@ -1424,7 +1447,33 @@ static struct fsl_mxc_capture_platform_data capture_data[] = {
 	},
 };
 
+static void mx6q_sd_bt_reset(void)
+{
+	printk(KERN_INFO "mx6q_sd_bt_reset");
+	gpio_request(SABRESD_BT_RESET, "bt-reset");
+	gpio_direction_output(SABRESD_BT_RESET, 0);
+	/* pull down reset pin at least >5ms */
+	mdelay(6);
+	/* pull up after power supply BT */
+	gpio_direction_output(SABRESD_BT_RESET, 1);
+	gpio_free(SABRESD_BT_RESET);
+	msleep(100);
+}
+
+static int mx6q_sd_bt_power_change(int status)
+{
+	if (status)
+		mx6q_sd_bt_reset();
+	return 0;
+}
 
+static struct platform_device mxc_bt_rfkill = {
+	.name = "mxc_bt_rfkill",
+};
+
+static struct imx_bt_rfkill_platform_data mxc_bt_rfkill_data = {
+	.power_change = mx6q_sd_bt_power_change,
+};
 static void sabresd_suspend_enter(void)
 {
 	/* suspend preparation */
@@ -1490,31 +1539,6 @@ static int __init imx6q_init_audio(void)
 	return 0;
 }
 
-#ifndef CONFIG_IMX_PCIE
-static void pcie_3v3_power(void)
-{
-	/* disable PCIE_3V3 first */
-	gpio_request(SABRESD_PCIE_PWR_EN, "pcie_3v3_en");
-	gpio_direction_output(SABRESD_PCIE_PWR_EN, 0);
-	mdelay(10);
-	/* enable PCIE_3V3 again */
-	gpio_set_value(SABRESD_PCIE_PWR_EN, 1);
-	gpio_free(SABRESD_PCIE_PWR_EN);
-}
-
-static void pcie_3v3_reset(void)
-{
-	/* reset miniPCIe */
-	gpio_request(SABRESD_PCIE_RST_B_REVB, "pcie_reset_rebB");
-	gpio_direction_output(SABRESD_PCIE_RST_B_REVB, 0);
-	/* The PCI Express Mini CEM specification states that PREST# is
-	deasserted minimum 1ms after 3.3vVaux has been applied and stable*/
-	mdelay(1);
-	gpio_set_value(SABRESD_PCIE_RST_B_REVB, 1);
-	gpio_free(SABRESD_PCIE_RST_B_REVB);
-}
-#endif
-
 static void gps_power_on(bool on)
 {
 	/* Enable/disable aux_3v15 */
@@ -1571,9 +1595,13 @@ static struct platform_device imx6q_gpio_led_device = {
 	}
 };
 
+/* For BT_PWD_L is conflict with charger's LED trigger gpio on sabresd_revC.
+ * add mutual exclusion here to be decided which one to be used by board config
+ */
 static void __init imx6q_add_device_gpio_leds(void)
 {
-	platform_device_register(&imx6q_gpio_led_device);
+	if (!uart5_enabled)
+		platform_device_register(&imx6q_gpio_led_device);
 }
 #else
 static void __init imx6q_add_device_gpio_leds(void) {}
@@ -1591,29 +1619,65 @@ static void __init imx6q_add_device_gpio_leds(void) {}
 	.debounce_interval = debounce,				\
 }
 
-static struct gpio_keys_button imx6q_buttons[] = {
+static struct gpio_keys_button sabresd_buttons[] = {
+	GPIO_BUTTON(SABRESD_VOLUME_UP, KEY_VOLUMEUP, 1, "volume-up", 0, 1),
+	GPIO_BUTTON(SABRESD_VOLUME_DN, KEY_POWER, 1, "volume-down", 1, 1),
+};
+
+static struct gpio_keys_platform_data sabresd_button_data = {
+	.buttons	= sabresd_buttons,
+	.nbuttons	= ARRAY_SIZE(sabresd_buttons),
+};
+
+static struct gpio_keys_button new_sabresd_buttons[] = {
 	GPIO_BUTTON(SABRESD_VOLUME_UP, KEY_VOLUMEUP, 1, "volume-up", 0, 1),
 	GPIO_BUTTON(SABRESD_VOLUME_DN, KEY_VOLUMEDOWN, 1, "volume-down", 0, 1),
-	GPIO_BUTTON(SABRESD_POWER_OFF, KEY_POWER, 1, "power", 1, 1),
+	GPIO_BUTTON(SABRESD_POWER_OFF, KEY_POWER, 1, "power-key", 1, 1),
 };
 
-static struct gpio_keys_platform_data imx6q_button_data = {
-	.buttons	= imx6q_buttons,
-	.nbuttons	= ARRAY_SIZE(imx6q_buttons),
+static struct gpio_keys_platform_data new_sabresd_button_data = {
+	.buttons	= new_sabresd_buttons,
+	.nbuttons	= ARRAY_SIZE(new_sabresd_buttons),
 };
 
-static struct platform_device imx6q_button_device = {
+static struct platform_device sabresd_button_device = {
 	.name		= "gpio-keys",
 	.id		= -1,
 	.num_resources  = 0,
-	.dev		= {
-		.platform_data = &imx6q_button_data,
-	}
 };
 
 static void __init imx6q_add_device_buttons(void)
 {
-	platform_device_register(&imx6q_button_device);
+	/* fix me */
+	/* For new sabresd(RevB4 ane above) change the
+	 * ONOFF key(SW1) design, the SW1 now connect
+	 * to GPIO_3_29, it can be use as a general power
+	 * key that Android reuired. But those old sabresd
+	 * such as RevB or older could not support this
+	 * change, so it needs a way to distinguish different
+	 * boards. Before board id/rev are defined cleary,
+	 * there is a simple way to achive this, that is using
+	 * SOC revison to identify differnt board revison.
+	 *
+	 * With the new sabresd change and SW mapping the
+	 * SW1 as power key, below function related to power
+	 * key are OK on new sabresd board(B4 or above).
+	 * 	1 Act as power button to power on the device when device is power off
+	 * 	2 Act as power button to power on the device(need keep press SW1 >5s)
+	 *	3 Act as power key to let device suspend/resume
+	 *	4 Act screenshort(hold power key and volume down key for 2s)
+	 */
+	if (mx6q_revision() >= IMX_CHIP_REVISION_1_2 ||
+			mx6dl_revision() >= IMX_CHIP_REVISION_1_1)
+		platform_device_add_data(&sabresd_button_device,
+				&new_sabresd_button_data,
+				sizeof(new_sabresd_button_data));
+	else
+		platform_device_add_data(&sabresd_button_device,
+				&sabresd_button_data,
+				sizeof(sabresd_button_data));
+
+	platform_device_register(&sabresd_button_device);
 }
 #else
 static void __init imx6q_add_device_buttons(void) {}
@@ -1653,6 +1717,49 @@ static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
+	char *str;
+	struct tag *t;
+	int i = 0;
+	struct ipuv3_fb_platform_data *pdata_fb = sabresd_fb_data;
+
+	for_each_tag(t, tags) {
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "fbmem=");
+			if (str != NULL) {
+				str += 6;
+				pdata_fb[i++].res_size[0] = memparse(str, &str);
+				while (*str == ',' &&
+					i < ARRAY_SIZE(sabresd_fb_data)) {
+					str++;
+					pdata_fb[i++].res_size[0] = memparse(str, &str);
+				}
+			}
+			/* ION reserved memory */
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "ionmem=");
+			if (str != NULL) {
+				str += 7;
+				imx_ion_data.heaps[0].size = memparse(str, &str);
+			}
+			/* Primary framebuffer base address */
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "fb0base=");
+			if (str != NULL) {
+				str += 8;
+				pdata_fb[0].res_base[0] =
+						simple_strtol(str, &str, 16);
+			}
+			/* GPU reserved memory */
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "gpumem=");
+			if (str != NULL) {
+				str += 7;
+				imx6q_gpu_pdata.reserved_mem_size = memparse(str, &str);
+			}
+			break;
+		}
+	}
 }
 
 static struct mipi_csi2_platform_data mipi_csi2_pdata = {
@@ -1687,8 +1794,65 @@ static const struct imx_pcie_platform_data mx6_sabresd_pcie_data __initconst = {
 	.pcie_rst	= SABRESD_PCIE_RST_B_REVB,
 	.pcie_wake_up	= SABRESD_PCIE_WAKE_B,
 	.pcie_dis	= SABRESD_PCIE_DIS_B,
+	.pcie_power_always_on = 1,
+};
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+static struct resource ram_console_resource = {
+	.name = "android ram console",
+	.flags = IORESOURCE_MEM,
 };
 
+static struct platform_device android_ram_console = {
+	.name = "ram_console",
+	.num_resources = 1,
+	.resource = &ram_console_resource,
+};
+
+static int __init imx6x_add_ram_console(void)
+{
+	return platform_device_register(&android_ram_console);
+}
+#else
+#define imx6x_add_ram_console() do {} while (0)
+#endif
+
+static iomux_v3_cfg_t mx6q_uart5_pads[] = {
+	MX6Q_PAD_KEY_ROW1__UART5_RXD,
+	MX6Q_PAD_KEY_COL1__UART5_TXD,
+	MX6Q_PAD_KEY_COL4__UART5_RTS,
+	MX6Q_PAD_KEY_ROW4__UART5_CTS,
+	/* gpio for reset */
+	MX6Q_PAD_GPIO_2__GPIO_1_2,
+};
+
+static iomux_v3_cfg_t mx6dl_uart5_pads[] = {
+	MX6DL_PAD_KEY_ROW1__UART5_RXD,
+	MX6DL_PAD_KEY_COL1__UART5_TXD,
+	MX6DL_PAD_KEY_COL4__UART5_RTS,
+	MX6DL_PAD_KEY_ROW4__UART5_CTS,
+	/* gpio for reset */
+	MX6DL_PAD_GPIO_2__GPIO_1_2,
+};
+static int __init uart5_setup(char * __unused)
+{
+	uart5_enabled = 1;
+	return 1;
+}
+__setup("bluetooth", uart5_setup);
+
+static void __init uart5_init(void)
+{
+	printk(KERN_INFO "uart5 is added\n");
+	if (cpu_is_mx6q())
+		mxc_iomux_v3_setup_multiple_pads(mx6q_uart5_pads,
+				ARRAY_SIZE(mx6q_uart5_pads));
+	else if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_uart5_pads,
+				ARRAY_SIZE(mx6dl_uart5_pads));
+	imx6q_add_imx_uart(4, &mx6q_sd_uart5_data);
+}
+
 /*!
  * Board specific initialization.
  */
@@ -1720,7 +1884,13 @@ static void __init mx6_sabresd_board_init(void)
 	gp_reg_id = sabresd_dvfscore_data.reg_id;
 	soc_reg_id = sabresd_dvfscore_data.soc_id;
 	mx6q_sabresd_init_uart();
+	imx6x_add_ram_console();
 
+	/*add bt support*/
+	if (uart5_enabled) {
+		uart5_init();
+		mxc_register_device(&mxc_bt_rfkill, &mxc_bt_rfkill_data);
+	}
 	/*
 	 * MX6DL/Solo only supports single IPU
 	 * The following codes are used to change ipu id
@@ -1730,6 +1900,11 @@ static void __init mx6_sabresd_board_init(void)
 	 */
 	if (cpu_is_mx6dl()) {
 		ldb_data.ipu_id = 0;
+		ldb_data.disp_id = 1;
+		hdmi_core_data.ipu_id = 0;
+		hdmi_core_data.disp_id = 0;
+		mipi_dsi_pdata.ipu_id = 0;
+		mipi_dsi_pdata.disp_id = 1;
 		ldb_data.sec_ipu_id = 0;
 	}
 	imx6q_add_mxc_hdmi_core(&hdmi_core_data);
@@ -1802,8 +1977,8 @@ static void __init mx6_sabresd_board_init(void)
 	   Mfgtools want emmc is mmcblk0 and other sd card is mmcblk1.
 	*/
 	imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabresd_sd4_data);
-	imx6q_add_sdhci_usdhc_imx(1, &mx6q_sabresd_sd2_data);
 	imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabresd_sd3_data);
+	imx6q_add_sdhci_usdhc_imx(1, &mx6q_sabresd_sd2_data);
 	imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
 	imx6q_sabresd_init_usb();
 	/* SATA is not supported by MX6DL/Solo */
@@ -1845,6 +2020,11 @@ static void __init mx6_sabresd_board_init(void)
 	imx6q_add_dma();
 
 	imx6q_add_dvfs_core(&sabresd_dvfscore_data);
+
+	if (imx_ion_data.heaps[0].size)
+		imx6q_add_ion(0, &imx_ion_data,
+			sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
+
 	imx6q_add_device_buttons();
 
 	/* enable sensor 3v3 and 1v8 */
@@ -1901,21 +2081,17 @@ static void __init mx6_sabresd_board_init(void)
 	gpio_direction_output(SABRESD_AUX_5V_EN, 1);
 	gpio_set_value(SABRESD_AUX_5V_EN, 1);
 
-#ifndef CONFIG_IMX_PCIE
-	/* enable pcie 3v3 power without pcie driver */
-	pcie_3v3_power();
-	mdelay(10);
-	pcie_3v3_reset();
-#endif
-
 	gps_power_on(true);
 	/* Register charger chips */
 	platform_device_register(&sabresd_max8903_charger_1);
 	pm_power_off = mx6_snvs_poweroff;
 	imx6q_add_busfreq();
 
-	/* Add PCIe RC interface support */
-	imx6q_add_pcie(&mx6_sabresd_pcie_data);
+	/* Add PCIe RC interface support
+	 * uart5 has pin mux with pcie. or you will use uart5 or use pcie
+	 */
+	if (!uart5_enabled)
+		imx6q_add_pcie(&mx6_sabresd_pcie_data);
 	if (cpu_is_mx6dl()) {
 		mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_elan_pads,
 						ARRAY_SIZE(mx6dl_arm2_elan_pads));
@@ -1962,9 +2138,42 @@ static struct sys_timer mx6_sabresd_timer = {
 
 static void __init mx6q_sabresd_reserve(void)
 {
-#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	phys_addr_t phys;
+	int i, fb0_reserved = 0, fb_array_size;
 
+	/*
+	 * Reserve primary framebuffer memory if its base address
+	 * is set by kernel command line.
+	 */
+	fb_array_size = ARRAY_SIZE(sabresd_fb_data);
+	if (fb_array_size > 0 && sabresd_fb_data[0].res_base[0] &&
+	    sabresd_fb_data[0].res_size[0]) {
+		memblock_reserve(sabresd_fb_data[0].res_base[0],
+				 sabresd_fb_data[0].res_size[0]);
+		memblock_remove(sabresd_fb_data[0].res_base[0],
+				sabresd_fb_data[0].res_size[0]);
+		sabresd_fb_data[0].late_init = true;
+		ipu_data[ldb_data.ipu_id].bypass_reset = true;
+		fb0_reserved = 1;
+	}
+	for (i = fb0_reserved; i < fb_array_size; i++)
+		if (sabresd_fb_data[i].res_size[0]) {
+			/* Reserve for other background buffer. */
+			phys = memblock_alloc(sabresd_fb_data[i].res_size[0],
+						SZ_4K);
+			memblock_remove(phys, sabresd_fb_data[i].res_size[0]);
+			sabresd_fb_data[i].res_base[0] = phys;
+		}
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE
+	phys = memblock_alloc_base(SZ_128K, SZ_4K, SZ_1G);
+	memblock_remove(phys, SZ_128K);
+	memblock_free(phys, SZ_128K);
+	ram_console_resource.start = phys;
+	ram_console_resource.end   = phys + SZ_128K - 1;
+#endif
+
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
 	if (imx6q_gpu_pdata.reserved_mem_size) {
 		phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
 					   SZ_4K, SZ_1G);
@@ -1972,6 +2181,14 @@ static void __init mx6q_sabresd_reserve(void)
 		imx6q_gpu_pdata.reserved_mem_base = phys;
 	}
 #endif
+
+#if defined(CONFIG_ION)
+	if (imx_ion_data.heaps[0].size) {
+		phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K);
+		memblock_remove(phys, imx_ion_data.heaps[0].size);
+		imx_ion_data.heaps[0].base = phys;
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index 66868c614e82..cd21b37a6885 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -1125,7 +1125,7 @@ static int mx6sl_arm2_keymap[] = {
 
 	KEY(1, 0, KEY_F3),
 	KEY(1, 1, KEY_F4),
-	KEY(1, 2, KEY_F5),
+	KEY(1, 2, KEY_POWER),
 	KEY(1, 3, KEY_MENU),
 
 	KEY(2, 0, KEY_PREVIOUS),
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 412423dd7879..574b142eb758 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -25,6 +25,7 @@
 #include <linux/clkdev.h>
 #include <linux/regulator/consumer.h>
 #include <asm/div64.h>
+#include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/clock.h>
@@ -5404,16 +5405,34 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 	/* Disable un-necessary PFDs & PLLs */
 	if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q())
 		pll2_pfd_400M.disable(&pll2_pfd_400M);
+#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+	/*
+	 * Bootloader may use pll2_pfd_352M to drive ldb_di1_clk
+	 * to support splashimage so we should not disable the
+	 * clock to keep the display running.
+	 */
 	pll2_pfd_352M.disable(&pll2_pfd_352M);
+#endif
 	pll2_pfd_594M.disable(&pll2_pfd_594M);
 
 #if !defined(CONFIG_FEC_1588)
 	pll3_pfd_454M.disable(&pll3_pfd_454M);
 	pll3_pfd_508M.disable(&pll3_pfd_508M);
-	pll3_pfd_540M.disable(&pll3_pfd_540M);
 	pll3_pfd_720M.disable(&pll3_pfd_720M);
-
-	pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
+	if (cpu_is_mx6q()) {
+		pll3_pfd_540M.disable(&pll3_pfd_540M);
+		pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
+	} else if (cpu_is_mx6dl()) {
+#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+		/*
+		 * Bootloader may use pll3_pfd_540M to drive ipu1_clk
+		 * to support splashimage so we should not disable the
+		 * clock to keep the display running.
+		 */
+		pll3_pfd_540M.disable(&pll3_pfd_540M);
+		pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
+#endif
+	}
 #endif
 	pll4_audio_main_clk.disable(&pll4_audio_main_clk);
 	pll5_video_main_clk.disable(&pll5_video_main_clk);
@@ -5428,8 +5447,16 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 	clk_set_rate(&pll4_audio_main_clk, 176000000);
 	clk_set_rate(&pll5_video_main_clk, 650000000);
 
+	/*
+	 * We don't set ipu1_di_clk[1]'s parent clock to
+	 * pll5_video_main_clk as bootloader may need
+	 * the parent to be ldb_di1_clk to support LVDS
+	 * panel splashimage.
+	 */
 	clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
+#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
 	clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
+#endif
 	clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
 	clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
 
@@ -5474,7 +5501,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 	/* Need to keep PLL3_PFD_540M enabled until AXI is sourced from it. */
 	clk_enable(&axi_clk);
 
-	if (cpu_is_mx6q() && (mx6q_revision() > IMX_CHIP_REVISION_1_1))
+	if (cpu_is_mx6q())
 		clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk);
 
 	clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);
@@ -5526,8 +5553,28 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 		     1 << MXC_CCM_CCGRx_CG13_OFFSET |
 		     3 << MXC_CCM_CCGRx_CG12_OFFSET |
 		     1 << MXC_CCM_CCGRx_CG11_OFFSET |
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+		     /*
+		      * We use IPU1 DI1 to do bootloader splashimage by
+		      * default, so we need to enable the clocks to
+		      * keep the display running.
+		      */
+		     3 << MXC_CCM_CCGRx_CG7_OFFSET |	/* ldb_di1_clk */
+		     3 << MXC_CCM_CCGRx_CG2_OFFSET |	/* ipu1_di1_clk */
+		     3 << MXC_CCM_CCGRx_CG0_OFFSET |	/* ipu1_clk */
+#endif
 		     3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
 	__raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+			/*
+			 * We use pwm1 to drive LVDS panel pwm backlight
+			 * to support bootloader splashimage by default,
+			 * so we need to enable the clock to keep the
+			 * backlight on.
+			 */
+			(machine_is_mx6q_sabresd() ?
+			(3 << MXC_CCM_CCGRx_CG8_OFFSET) : 0) | /* pwm1_clk */
+#endif
 			1 << MXC_CCM_CCGRx_CG6_OFFSET |
 			1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
 	__raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index f7ad317a4fe3..4525e29a472a 100644
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -246,6 +246,10 @@ extern const struct imx_pcie_data imx6q_pcie_data __initconst;
 
 #define imx6q_add_busfreq(pdata)	imx_add_busfreq(pdata)
 
+#define imx6q_add_ion(id, pdata, size)	\
+	platform_device_register_resndata(NULL, "ion-mxc",\
+			id, NULL, 0, pdata, size);
+
 extern const struct imx_imx_keypad_data imx6sl_imx_keypad_data;
 #define imx6sl_add_imx_keypad(pdata)	\
 	imx_add_imx_keypad(&imx6sl_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx6/devices.c b/arch/arm/mach-mx6/devices.c
index 3eab54de33c8..29becab0d430 100644
--- a/arch/arm/mach-mx6/devices.c
+++ b/arch/arm/mach-mx6/devices.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/arch/arm/mach-mx6/irq.c b/arch/arm/mach-mx6/irq.c
index d0bde950a377..96f512ef1b8b 100644
--- a/arch/arm/mach-mx6/irq.c
+++ b/arch/arm/mach-mx6/irq.c
@@ -58,15 +58,15 @@ static struct irq_tuner mxc_irq_tuner[] = {
 	{
 	 .irq_number = 41, /* GPU 3D */
 	 .up_threshold = 0,
-	 .enable = 1,},
+	 .enable = 0,},
 	{
 	 .irq_number = 42, /* GPU 2D */
 	 .up_threshold = 40,
-	 .enable = 1,},
+	 .enable = 0,},
 	{
 	 .irq_number = 43, /* GPU VG */
 	 .up_threshold = 0,
-	 .enable = 1,},
+	 .enable = 0,},
 	{
 	 .irq_number = 54, /* uSDHC1 */
 	 .up_threshold = 4,
diff --git a/arch/arm/mach-mx6/mx6q_hdmidongle_pmic_wm831x.c b/arch/arm/mach-mx6/mx6q_hdmidongle_pmic_wm831x.c
new file mode 100644
index 000000000000..86e13a46c364
--- /dev/null
+++ b/arch/arm/mach-mx6/mx6q_hdmidongle_pmic_wm831x.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_MFD_WM831X
+#include <linux/mfd/wm831x/core.h>
+#include <linux/mfd/wm831x/pdata.h>
+#include <linux/mfd/wm831x/regulator.h>
+#include <linux/mfd/wm831x/gpio.h>
+#include <linux/mfd/wm831x/status.h>
+#include <mach/system.h>
+
+extern u32 enable_ldo_mode;
+
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+/* 1.3, 1.3 1.5 */
+#define WM831X_DC1_ON_CONFIG_VAL            (0x40<<WM831X_DC1_ON_VSEL_SHIFT)
+#define WM831X_DC2_ON_CONFIG_VAL            (0x40<<WM831X_DC2_ON_VSEL_SHIFT)
+#define WM831X_DC3_ON_CONFIG_VAL            (0x1A<<WM831X_DC3_ON_VSEL_SHIFT)
+#else
+/* 1.375, 1.375. 1.5 */
+
+#define WM831X_DC1_ON_CONFIG_VAL            (0x44<<WM831X_DC1_ON_VSEL_SHIFT)
+#define WM831X_DC2_ON_CONFIG_VAL            (0x44<<WM831X_DC2_ON_VSEL_SHIFT)
+#define WM831X_DC3_ON_CONFIG_VAL            (0x1A<<WM831X_DC3_ON_VSEL_SHIFT)
+
+#endif
+
+#define WM831X_DC1_DVS_MODE_VAL	(0x02<<WM831X_DC1_DVS_SRC_SHIFT)
+#define WM831X_DC2_DVS_MODE_VAL	(0x02<<WM831X_DC2_DVS_SRC_SHIFT)
+
+#define WM831X_DC1_DVS_CONTROL_VAL	(0x20<<WM831X_DC1_DVS_VSEL_SHIFT)
+#define WM831X_DC2_DVS_CONTROL_VAL	(0x20<<WM831X_DC2_DVS_VSEL_SHIFT)
+
+#define WM831X_DC1_DVS_MASK	(WM831X_DC1_DVS_SRC_MASK|WM831X_DC1_DVS_VSEL_MASK)
+#define WM831X_DC2_DVS_MASK	(WM831X_DC2_DVS_SRC_MASK|WM831X_DC1_DVS_VSEL_MASK)
+
+#define WM831X_DC1_DVS_VAL	(WM831X_DC1_DVS_MODE_VAL|WM831X_DC1_DVS_CONTROL_VAL)
+#define WM831X_DC2_DVS_VAL                   (WM831X_DC2_DVS_MODE_VAL|WM831X_DC2_DVS_CONTROL_VAL)
+
+#define WM831X_GPN_FN_VAL_HW_EN	(0x0A<<WM831X_GPN_FN_SHIFT)
+#define WM831X_GPN_FN_VAL_HW_CTL	(0x0C<<WM831X_GPN_FN_SHIFT)
+#define WM831X_GPN_FN_VAL_DVS1	(0x08<<WM831X_GPN_FN_SHIFT)
+
+#define WM831X_GPN_DIR_VAL	(0x1<<WM831X_GPN_DIR_SHIFT)
+#define WM831X_GPN_PULL_VAL	(0x3<<WM831X_GPN_PULL_SHIFT)
+#define WM831X_GPN_INT_MODE_VAL	(0x1<<WM831X_GPN_INT_MODE_SHIFT)
+#define WM831X_GPN_POL_VAL	(0x1<<WM831X_GPN_POL_SHIFT)
+#define WM831X_GPN_ENA_VAL	(0x1<<WM831X_GPN_ENA_SHIFT)
+
+#define WM831X_GPIO7_8_9_MASK	(WM831X_GPN_DIR_MASK|WM831X_GPN_INT_MODE_MASK| \
+						WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_FN_MASK)
+
+
+#define WM831X_GPIO7_VAL	(WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL| \
+						WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_HW_EN)
+#define WM831X_GPIO8_VAL	(WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL| \
+						WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_HW_CTL)
+#define WM831X_GPIO9_VAL	(WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL| \
+						WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_DVS1)
+
+#define WM831X_STATUS_LED_ON                  (0x1 << WM831X_LED_SRC_SHIFT)
+#define WM831X_STATUS_LED_OFF                 (0x0 << WM831X_LED_SRC_SHIFT)
+
+static int wm8326_post_init(struct wm831x *wm831x)
+{
+	wm831x_set_bits(wm831x, WM831X_DC1_ON_CONFIG, WM831X_DC1_ON_VSEL_MASK, WM831X_DC1_ON_CONFIG_VAL);
+	wm831x_set_bits(wm831x, WM831X_DC2_ON_CONFIG, WM831X_DC2_ON_VSEL_MASK, WM831X_DC2_ON_CONFIG_VAL);
+	wm831x_set_bits(wm831x, WM831X_DC3_ON_CONFIG, WM831X_DC3_ON_VSEL_MASK, WM831X_DC3_ON_CONFIG_VAL);
+
+	wm831x_set_bits(wm831x, WM831X_DC1_DVS_CONTROL, WM831X_DC1_DVS_MASK, WM831X_DC1_DVS_VAL);
+	wm831x_set_bits(wm831x, WM831X_DC2_DVS_CONTROL, WM831X_DC2_DVS_MASK, WM831X_DC2_DVS_VAL);
+
+	wm831x_set_bits(wm831x, WM831X_GPIO7_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO7_VAL);
+	wm831x_set_bits(wm831x, WM831X_GPIO8_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO8_VAL);
+	wm831x_set_bits(wm831x, WM831X_GPIO9_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO9_VAL);
+
+	wm831x_set_bits(wm831x, WM831X_STATUS_LED_1 , WM831X_LED_SRC_MASK, WM831X_STATUS_LED_OFF);
+	wm831x_set_bits(wm831x, WM831X_STATUS_LED_2 , WM831X_LED_SRC_MASK, WM831X_STATUS_LED_ON);
+
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	if (enable_ldo_mode == LDO_MODE_DEFAULT)
+		enable_ldo_mode = LDO_MODE_BYPASSED;
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_REGULATOR
+/* ARM core */
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+static struct regulator_consumer_supply hdmidongle_vddarm_consumers[] = {
+	{
+		.supply     = "VDDCORE_DCDC1",
+	}
+};
+
+static struct regulator_consumer_supply hdmidongle_vddsoc_consumers[] = {
+	{
+		.supply     = "VDDSOC_DCDC2",
+	}
+};
+#endif
+
+static struct regulator_init_data hdmidongle_vddarm_dcdc1 = {
+	.constraints = {
+		.name = "vdd_arm",
+		.min_uV = 100000,
+		.max_uV = 1500000,
+		.min_uA = 0,
+		.max_uA = 4000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+	},
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.num_consumer_supplies = ARRAY_SIZE(hdmidongle_vddarm_consumers),
+	.consumer_supplies = hdmidongle_vddarm_consumers,
+#endif
+};
+
+
+static struct regulator_init_data hdmidongle_vddsoc_dcdc2 = {
+	.constraints = {
+		.name = "vdd_soc",
+		.min_uV = 100000,
+		.max_uV = 1500000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+	},
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.num_consumer_supplies = ARRAY_SIZE(hdmidongle_vddsoc_consumers),
+	.consumer_supplies = hdmidongle_vddsoc_consumers,
+#endif
+};
+
+
+
+static struct regulator_init_data hdmidongle_vddmem_1v5_dcdc3 = {
+	.constraints = {
+		.name = "vdd_mem_1v5",
+		.min_uV = 1400000,
+		.max_uV = 1500000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	},
+};
+#endif
+
+static struct wm831x_pdata hdmidongle_wm8326_pdata = {
+#ifdef CONFIG_REGULATOR
+	.dcdc = {
+		&hdmidongle_vddarm_dcdc1,  /* DCDC1 */
+		&hdmidongle_vddsoc_dcdc2,  /* DCDC2 */
+	},
+#endif
+	.post_init = wm8326_post_init,
+};
+
+static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+	{
+	I2C_BOARD_INFO("wm8326", 0x34),
+	.platform_data = &hdmidongle_wm8326_pdata,
+	},
+};
+
+int __init mx6q_hdmidongle_init_wm8326(void)
+{
+	return i2c_register_board_info(2, mxc_i2c2_board_info,
+			ARRAY_SIZE(mxc_i2c2_board_info));
+}
+#else
+int __init mx6q_hdmidongle_init_wm8326(void) {};
+#endif
+
diff --git a/arch/arm/mach-mx6/pcie.c b/arch/arm/mach-mx6/pcie.c
index c4e8f7d922c9..e6b77ae9e750 100644
--- a/arch/arm/mach-mx6/pcie.c
+++ b/arch/arm/mach-mx6/pcie.c
@@ -746,7 +746,8 @@ static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base,
 		spin_lock_init(&pp->conf_lock);
 		memset(pp->res, 0, sizeof(pp->res));
 	} else {
-		pr_info("IMX PCIe port: link down!\n");
+		pr_info("IMX PCIe port: link down with power supply %d!\n",
+				pdata->pcie_power_always_on);
 		/* Release the clocks, and disable the power */
 
 		pcie_clk = clk_get(NULL, "pcie_clk");
@@ -759,11 +760,13 @@ static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base,
 		imx_pcie_clrset(IOMUXC_GPR1_PCIE_REF_CLK_EN, 0 << 16,
 				IOMUXC_GPR1);
 
-		/* Disable PCIE power */
-		gpio_request(pdata->pcie_pwr_en, "PCIE POWER_EN");
+		if (!pdata->pcie_power_always_on) {
+			/* Disable PCIE power */
+			gpio_request(pdata->pcie_pwr_en, "PCIE POWER_EN");
 
-		/* activate PCIE_PWR_EN */
-		gpio_direction_output(pdata->pcie_pwr_en, 0);
+			/* activate PCIE_PWR_EN */
+			gpio_direction_output(pdata->pcie_pwr_en, 0);
+		}
 
 		imx_pcie_clrset(IOMUXC_GPR1_TEST_POWERDOWN, 1 << 18,
 				IOMUXC_GPR1);