diff options
Diffstat (limited to 'arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h')
| -rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h | 2349 |
1 files changed, 2277 insertions, 72 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h index 50d90ea1b136..d21b85f19542 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h @@ -1,7 +1,7 @@ /* - * stmp378x: PINCTRL register definitions + * STMP PINCTRL Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,74 +17,2279 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) -#define REGS_PINCTRL_PHYS 0x80018000 -#define REGS_PINCTRL_SIZE 0x2000 - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x400 -#define HW_PINCTRL_PULL1 0x410 -#define HW_PINCTRL_PULL2 0x420 -#define HW_PINCTRL_PULL3 0x430 - -#define HW_PINCTRL_DOUT0 0x500 -#define HW_PINCTRL_DOUT1 0x510 -#define HW_PINCTRL_DOUT2 0x520 - -#define HW_PINCTRL_DIN0 0x600 -#define HW_PINCTRL_DIN1 0x610 -#define HW_PINCTRL_DIN2 0x620 - -#define HW_PINCTRL_DOE0 0x700 -#define HW_PINCTRL_DOE1 0x710 -#define HW_PINCTRL_DOE2 0x720 - -#define HW_PINCTRL_PIN2IRQ0 0x800 -#define HW_PINCTRL_PIN2IRQ1 0x810 -#define HW_PINCTRL_PIN2IRQ2 0x820 - -#define HW_PINCTRL_IRQEN0 0x900 -#define HW_PINCTRL_IRQEN1 0x910 -#define HW_PINCTRL_IRQEN2 0x920 - -#define HW_PINCTRL_IRQLEVEL0 0xA00 -#define HW_PINCTRL_IRQLEVEL1 0xA10 -#define HW_PINCTRL_IRQLEVEL2 0xA20 - -#define HW_PINCTRL_IRQPOL0 0xB00 -#define HW_PINCTRL_IRQPOL1 0xB10 -#define HW_PINCTRL_IRQPOL2 0xB20 - -#define HW_PINCTRL_IRQSTAT0 0xC00 -#define HW_PINCTRL_IRQSTAT1 0xC10 -#define HW_PINCTRL_IRQSTAT2 0xC20 - -#endif + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H 1 + +#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) +#define REGS_PINCTRL_PHYS (0x80018000) +#define REGS_PINCTRL_SIZE 0x00002000 + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) +#define HW_PINCTRL_CTRL_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL) +#define HW_PINCTRL_CTRL_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL_SET) +#define HW_PINCTRL_CTRL_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR) +#define HW_PINCTRL_CTRL_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL_TOG) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 28 +#define BM_PINCTRL_CTRL_RSRVD2 0x30000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT3 0x08000000 +#define BM_PINCTRL_CTRL_PRESENT2 0x04000000 +#define BM_PINCTRL_CTRL_PRESENT1 0x02000000 +#define BM_PINCTRL_CTRL_PRESENT0 0x01000000 +#define BP_PINCTRL_CTRL_RSRVD1 3 +#define BM_PINCTRL_CTRL_RSRVD1 0x00FFFFF8 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 3) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) +#define HW_PINCTRL_MUXSEL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0) +#define HW_PINCTRL_MUXSEL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_SET) +#define HW_PINCTRL_MUXSEL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_CLR) +#define HW_PINCTRL_MUXSEL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_TOG) + +#define BP_PINCTRL_MUXSEL0_BANK0_PIN15 30 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL0_BANK0_PIN15) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN14 28 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL0_BANK0_PIN14) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN13 26 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL0_BANK0_PIN13) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN12 24 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL0_BANK0_PIN12) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN11 22 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL0_BANK0_PIN11) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN10 20 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL0_BANK0_PIN10) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN09 18 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL0_BANK0_PIN09) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN08 16 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_BANK0_PIN08) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) +#define HW_PINCTRL_MUXSEL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1) +#define HW_PINCTRL_MUXSEL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1_SET) +#define HW_PINCTRL_MUXSEL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1_CLR) +#define HW_PINCTRL_MUXSEL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1_TOG) + +#define BP_PINCTRL_MUXSEL1_BANK0_PIN31 30 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL1_BANK0_PIN31) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN30 28 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL1_BANK0_PIN30) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN29 26 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_BANK0_PIN29) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) +#define HW_PINCTRL_MUXSEL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2) +#define HW_PINCTRL_MUXSEL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2_SET) +#define HW_PINCTRL_MUXSEL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2_CLR) +#define HW_PINCTRL_MUXSEL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2_TOG) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) +#define HW_PINCTRL_MUXSEL3_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3) +#define HW_PINCTRL_MUXSEL3_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_SET) +#define HW_PINCTRL_MUXSEL3_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_CLR) +#define HW_PINCTRL_MUXSEL3_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_TOG) + +#define BP_PINCTRL_MUXSEL3_RSRVD0 30 +#define BM_PINCTRL_MUXSEL3_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL3_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_RSRVD0) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) +#define HW_PINCTRL_MUXSEL4_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4) +#define HW_PINCTRL_MUXSEL4_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_SET) +#define HW_PINCTRL_MUXSEL4_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR) +#define HW_PINCTRL_MUXSEL4_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_TOG) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN11 22 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_BANK2_PIN11) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) +#define HW_PINCTRL_MUXSEL5_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5) +#define HW_PINCTRL_MUXSEL5_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_SET) +#define HW_PINCTRL_MUXSEL5_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR) +#define HW_PINCTRL_MUXSEL5_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_TOG) + +#define BP_PINCTRL_MUXSEL5_BANK2_PIN31 30 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL5_BANK2_PIN31) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN30 28 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL5_BANK2_PIN30) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN29 26 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL5_BANK2_PIN29) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN28 24 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_BANK2_PIN28) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN23 14 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL5_BANK2_PIN23) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN22 12 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_BANK2_PIN22) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) +#define HW_PINCTRL_MUXSEL6_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6) +#define HW_PINCTRL_MUXSEL6_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_SET) +#define HW_PINCTRL_MUXSEL6_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR) +#define HW_PINCTRL_MUXSEL6_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_TOG) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) +#define HW_PINCTRL_MUXSEL7_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7) +#define HW_PINCTRL_MUXSEL7_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_SET) +#define HW_PINCTRL_MUXSEL7_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR) +#define HW_PINCTRL_MUXSEL7_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_TOG) + +#define BP_PINCTRL_MUXSEL7_RSRVD0 12 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0xFFFFF000 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN19 6 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_BANK3_PIN19) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000200) +#define HW_PINCTRL_DRIVE0_SET (0x00000204) +#define HW_PINCTRL_DRIVE0_CLR (0x00000208) +#define HW_PINCTRL_DRIVE0_TOG (0x0000020c) +#define HW_PINCTRL_DRIVE0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0) +#define HW_PINCTRL_DRIVE0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0_SET) +#define HW_PINCTRL_DRIVE0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0_CLR) +#define HW_PINCTRL_DRIVE0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0_TOG) + +#define BP_PINCTRL_DRIVE0_RSRVD7 30 +#define BM_PINCTRL_DRIVE0_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE0_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE0_RSRVD7) +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BP_PINCTRL_DRIVE0_RSRVD6 26 +#define BM_PINCTRL_DRIVE0_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE0_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE0_RSRVD6) +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BP_PINCTRL_DRIVE0_RSRVD5 22 +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE0_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE0_RSRVD5) +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BP_PINCTRL_DRIVE0_RSRVD4 18 +#define BM_PINCTRL_DRIVE0_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE0_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE0_RSRVD4) +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BP_PINCTRL_DRIVE0_RSRVD3 14 +#define BM_PINCTRL_DRIVE0_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE0_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE0_RSRVD3) +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BP_PINCTRL_DRIVE0_RSRVD2 10 +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE0_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE0_RSRVD2) +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BP_PINCTRL_DRIVE0_RSRVD1 6 +#define BM_PINCTRL_DRIVE0_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE0_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE0_RSRVD1) +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BP_PINCTRL_DRIVE0_RSRVD0 2 +#define BM_PINCTRL_DRIVE0_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE0_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE0_RSRVD0) +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000210) +#define HW_PINCTRL_DRIVE1_SET (0x00000214) +#define HW_PINCTRL_DRIVE1_CLR (0x00000218) +#define HW_PINCTRL_DRIVE1_TOG (0x0000021c) +#define HW_PINCTRL_DRIVE1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1) +#define HW_PINCTRL_DRIVE1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1_SET) +#define HW_PINCTRL_DRIVE1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1_CLR) +#define HW_PINCTRL_DRIVE1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1_TOG) + +#define BP_PINCTRL_DRIVE1_RSRVD7 30 +#define BM_PINCTRL_DRIVE1_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE1_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE1_RSRVD7) +#define BP_PINCTRL_DRIVE1_BANK0_PIN15_MA 28 +#define BM_PINCTRL_DRIVE1_BANK0_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE1_BANK0_PIN15_MA) +#define BP_PINCTRL_DRIVE1_RSRVD6 26 +#define BM_PINCTRL_DRIVE1_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE1_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE1_RSRVD6) +#define BP_PINCTRL_DRIVE1_BANK0_PIN14_MA 24 +#define BM_PINCTRL_DRIVE1_BANK0_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE1_BANK0_PIN14_MA) +#define BP_PINCTRL_DRIVE1_RSRVD5 22 +#define BM_PINCTRL_DRIVE1_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE1_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE1_RSRVD5) +#define BP_PINCTRL_DRIVE1_BANK0_PIN13_MA 20 +#define BM_PINCTRL_DRIVE1_BANK0_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE1_BANK0_PIN13_MA) +#define BP_PINCTRL_DRIVE1_RSRVD4 18 +#define BM_PINCTRL_DRIVE1_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE1_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE1_RSRVD4) +#define BP_PINCTRL_DRIVE1_BANK0_PIN12_MA 16 +#define BM_PINCTRL_DRIVE1_BANK0_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE1_BANK0_PIN12_MA) +#define BP_PINCTRL_DRIVE1_RSRVD3 14 +#define BM_PINCTRL_DRIVE1_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE1_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE1_RSRVD3) +#define BP_PINCTRL_DRIVE1_BANK0_PIN11_MA 12 +#define BM_PINCTRL_DRIVE1_BANK0_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE1_BANK0_PIN11_MA) +#define BP_PINCTRL_DRIVE1_RSRVD2 10 +#define BM_PINCTRL_DRIVE1_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE1_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE1_RSRVD2) +#define BP_PINCTRL_DRIVE1_BANK0_PIN10_MA 8 +#define BM_PINCTRL_DRIVE1_BANK0_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE1_BANK0_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE1_BANK0_PIN10_MA) +#define BP_PINCTRL_DRIVE1_RSRVD1 6 +#define BM_PINCTRL_DRIVE1_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE1_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE1_RSRVD1) +#define BP_PINCTRL_DRIVE1_BANK0_PIN09_MA 4 +#define BM_PINCTRL_DRIVE1_BANK0_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE1_BANK0_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE1_BANK0_PIN09_MA) +#define BP_PINCTRL_DRIVE1_RSRVD0 2 +#define BM_PINCTRL_DRIVE1_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE1_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE1_RSRVD0) +#define BP_PINCTRL_DRIVE1_BANK0_PIN08_MA 0 +#define BM_PINCTRL_DRIVE1_BANK0_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE1_BANK0_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE1_BANK0_PIN08_MA) + +#define HW_PINCTRL_DRIVE2 (0x00000220) +#define HW_PINCTRL_DRIVE2_SET (0x00000224) +#define HW_PINCTRL_DRIVE2_CLR (0x00000228) +#define HW_PINCTRL_DRIVE2_TOG (0x0000022c) +#define HW_PINCTRL_DRIVE2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2) +#define HW_PINCTRL_DRIVE2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2_SET) +#define HW_PINCTRL_DRIVE2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2_CLR) +#define HW_PINCTRL_DRIVE2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2_TOG) + +#define BP_PINCTRL_DRIVE2_RSRVD7 30 +#define BM_PINCTRL_DRIVE2_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE2_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE2_RSRVD7) +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BP_PINCTRL_DRIVE2_RSRVD6 26 +#define BM_PINCTRL_DRIVE2_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE2_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE2_RSRVD6) +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BP_PINCTRL_DRIVE2_RSRVD5 22 +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE2_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE2_RSRVD5) +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BP_PINCTRL_DRIVE2_RSRVD4 18 +#define BM_PINCTRL_DRIVE2_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE2_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE2_RSRVD4) +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BP_PINCTRL_DRIVE2_RSRVD3 14 +#define BM_PINCTRL_DRIVE2_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE2_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE2_RSRVD3) +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BP_PINCTRL_DRIVE2_RSRVD2 10 +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE2_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE2_RSRVD2) +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BP_PINCTRL_DRIVE2_RSRVD1 6 +#define BM_PINCTRL_DRIVE2_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE2_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE2_RSRVD1) +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BP_PINCTRL_DRIVE2_RSRVD0 2 +#define BM_PINCTRL_DRIVE2_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE2_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE2_RSRVD0) +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000230) +#define HW_PINCTRL_DRIVE3_SET (0x00000234) +#define HW_PINCTRL_DRIVE3_CLR (0x00000238) +#define HW_PINCTRL_DRIVE3_TOG (0x0000023c) +#define HW_PINCTRL_DRIVE3_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3) +#define HW_PINCTRL_DRIVE3_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3_SET) +#define HW_PINCTRL_DRIVE3_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3_CLR) +#define HW_PINCTRL_DRIVE3_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3_TOG) + +#define BP_PINCTRL_DRIVE3_RSRVD7 30 +#define BM_PINCTRL_DRIVE3_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE3_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE3_RSRVD7) +#define BP_PINCTRL_DRIVE3_BANK0_PIN31_MA 28 +#define BM_PINCTRL_DRIVE3_BANK0_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE3_BANK0_PIN31_MA) +#define BP_PINCTRL_DRIVE3_RSRVD6 26 +#define BM_PINCTRL_DRIVE3_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE3_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE3_RSRVD6) +#define BP_PINCTRL_DRIVE3_BANK0_PIN30_MA 24 +#define BM_PINCTRL_DRIVE3_BANK0_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE3_BANK0_PIN30_MA) +#define BP_PINCTRL_DRIVE3_RSRVD5 22 +#define BM_PINCTRL_DRIVE3_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BP_PINCTRL_DRIVE3_BANK0_PIN29_MA 20 +#define BM_PINCTRL_DRIVE3_BANK0_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_BANK0_PIN29_MA) +#define BP_PINCTRL_DRIVE3_RSRVD4 18 +#define BM_PINCTRL_DRIVE3_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE3_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE3_RSRVD4) +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BP_PINCTRL_DRIVE3_RSRVD3 14 +#define BM_PINCTRL_DRIVE3_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE3_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE3_RSRVD3) +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BP_PINCTRL_DRIVE3_RSRVD2 10 +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE3_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE3_RSRVD2) +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BP_PINCTRL_DRIVE3_RSRVD1 6 +#define BM_PINCTRL_DRIVE3_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE3_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE3_RSRVD1) +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BP_PINCTRL_DRIVE3_RSRVD0 2 +#define BM_PINCTRL_DRIVE3_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE3_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE3_RSRVD0) +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000240) +#define HW_PINCTRL_DRIVE4_SET (0x00000244) +#define HW_PINCTRL_DRIVE4_CLR (0x00000248) +#define HW_PINCTRL_DRIVE4_TOG (0x0000024c) +#define HW_PINCTRL_DRIVE4_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4) +#define HW_PINCTRL_DRIVE4_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4_SET) +#define HW_PINCTRL_DRIVE4_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4_CLR) +#define HW_PINCTRL_DRIVE4_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4_TOG) + +#define BP_PINCTRL_DRIVE4_RSRVD7 30 +#define BM_PINCTRL_DRIVE4_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE4_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE4_RSRVD7) +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BP_PINCTRL_DRIVE4_RSRVD6 26 +#define BM_PINCTRL_DRIVE4_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE4_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE4_RSRVD6) +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BP_PINCTRL_DRIVE4_RSRVD5 22 +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE4_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE4_RSRVD5) +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BP_PINCTRL_DRIVE4_RSRVD4 18 +#define BM_PINCTRL_DRIVE4_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE4_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE4_RSRVD4) +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BP_PINCTRL_DRIVE4_RSRVD3 14 +#define BM_PINCTRL_DRIVE4_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE4_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE4_RSRVD3) +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BP_PINCTRL_DRIVE4_RSRVD2 10 +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE4_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE4_RSRVD2) +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BP_PINCTRL_DRIVE4_RSRVD1 6 +#define BM_PINCTRL_DRIVE4_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE4_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE4_RSRVD1) +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BP_PINCTRL_DRIVE4_RSRVD0 2 +#define BM_PINCTRL_DRIVE4_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE4_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE4_RSRVD0) +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000250) +#define HW_PINCTRL_DRIVE5_SET (0x00000254) +#define HW_PINCTRL_DRIVE5_CLR (0x00000258) +#define HW_PINCTRL_DRIVE5_TOG (0x0000025c) +#define HW_PINCTRL_DRIVE5_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5) +#define HW_PINCTRL_DRIVE5_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5_SET) +#define HW_PINCTRL_DRIVE5_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5_CLR) +#define HW_PINCTRL_DRIVE5_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5_TOG) + +#define BP_PINCTRL_DRIVE5_RSRVD7 30 +#define BM_PINCTRL_DRIVE5_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE5_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE5_RSRVD7) +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BP_PINCTRL_DRIVE5_RSRVD6 26 +#define BM_PINCTRL_DRIVE5_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE5_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE5_RSRVD6) +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BP_PINCTRL_DRIVE5_RSRVD5 22 +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE5_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE5_RSRVD5) +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BP_PINCTRL_DRIVE5_RSRVD4 18 +#define BM_PINCTRL_DRIVE5_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE5_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE5_RSRVD4) +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BP_PINCTRL_DRIVE5_RSRVD3 14 +#define BM_PINCTRL_DRIVE5_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE5_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE5_RSRVD3) +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BP_PINCTRL_DRIVE5_RSRVD2 10 +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE5_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE5_RSRVD2) +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BP_PINCTRL_DRIVE5_RSRVD1 6 +#define BM_PINCTRL_DRIVE5_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE5_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE5_RSRVD1) +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BP_PINCTRL_DRIVE5_RSRVD0 2 +#define BM_PINCTRL_DRIVE5_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE5_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE5_RSRVD0) +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000260) +#define HW_PINCTRL_DRIVE6_SET (0x00000264) +#define HW_PINCTRL_DRIVE6_CLR (0x00000268) +#define HW_PINCTRL_DRIVE6_TOG (0x0000026c) +#define HW_PINCTRL_DRIVE6_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6) +#define HW_PINCTRL_DRIVE6_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6_SET) +#define HW_PINCTRL_DRIVE6_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6_CLR) +#define HW_PINCTRL_DRIVE6_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6_TOG) + +#define BP_PINCTRL_DRIVE6_RSRVD7 30 +#define BM_PINCTRL_DRIVE6_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE6_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE6_RSRVD7) +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BP_PINCTRL_DRIVE6_RSRVD6 26 +#define BM_PINCTRL_DRIVE6_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE6_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE6_RSRVD6) +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BP_PINCTRL_DRIVE6_RSRVD5 22 +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE6_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE6_RSRVD5) +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BP_PINCTRL_DRIVE6_RSRVD4 18 +#define BM_PINCTRL_DRIVE6_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE6_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE6_RSRVD4) +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BP_PINCTRL_DRIVE6_RSRVD3 14 +#define BM_PINCTRL_DRIVE6_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE6_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE6_RSRVD3) +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BP_PINCTRL_DRIVE6_RSRVD2 10 +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE6_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE6_RSRVD2) +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BP_PINCTRL_DRIVE6_RSRVD1 6 +#define BM_PINCTRL_DRIVE6_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE6_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE6_RSRVD1) +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BP_PINCTRL_DRIVE6_RSRVD0 2 +#define BM_PINCTRL_DRIVE6_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE6_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE6_RSRVD0) +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000270) +#define HW_PINCTRL_DRIVE7_SET (0x00000274) +#define HW_PINCTRL_DRIVE7_CLR (0x00000278) +#define HW_PINCTRL_DRIVE7_TOG (0x0000027c) +#define HW_PINCTRL_DRIVE7_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7) +#define HW_PINCTRL_DRIVE7_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7_SET) +#define HW_PINCTRL_DRIVE7_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7_CLR) +#define HW_PINCTRL_DRIVE7_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7_TOG) + +#define BP_PINCTRL_DRIVE7_RSRVD7 28 +#define BM_PINCTRL_DRIVE7_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE7_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_RSRVD7) +#define BP_PINCTRL_DRIVE7_RSRVD6 26 +#define BM_PINCTRL_DRIVE7_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE7_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE7_RSRVD6) +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BP_PINCTRL_DRIVE7_RSRVD5 22 +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE7_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE7_RSRVD5) +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BP_PINCTRL_DRIVE7_RSRVD4 18 +#define BM_PINCTRL_DRIVE7_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE7_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE7_RSRVD4) +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BP_PINCTRL_DRIVE7_RSRVD3 14 +#define BM_PINCTRL_DRIVE7_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE7_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE7_RSRVD3) +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BP_PINCTRL_DRIVE7_RSRVD2 10 +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE7_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE7_RSRVD2) +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BP_PINCTRL_DRIVE7_RSRVD1 6 +#define BM_PINCTRL_DRIVE7_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE7_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE7_RSRVD1) +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BP_PINCTRL_DRIVE7_RSRVD0 2 +#define BM_PINCTRL_DRIVE7_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE7_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE7_RSRVD0) +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000280) +#define HW_PINCTRL_DRIVE8_SET (0x00000284) +#define HW_PINCTRL_DRIVE8_CLR (0x00000288) +#define HW_PINCTRL_DRIVE8_TOG (0x0000028c) +#define HW_PINCTRL_DRIVE8_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8) +#define HW_PINCTRL_DRIVE8_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8_SET) +#define HW_PINCTRL_DRIVE8_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8_CLR) +#define HW_PINCTRL_DRIVE8_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8_TOG) + +#define BP_PINCTRL_DRIVE8_RSRVD7 30 +#define BM_PINCTRL_DRIVE8_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE8_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE8_RSRVD7) +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BP_PINCTRL_DRIVE8_RSRVD6 26 +#define BM_PINCTRL_DRIVE8_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE8_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE8_RSRVD6) +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BP_PINCTRL_DRIVE8_RSRVD5 22 +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE8_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE8_RSRVD5) +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BP_PINCTRL_DRIVE8_RSRVD4 18 +#define BM_PINCTRL_DRIVE8_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE8_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE8_RSRVD4) +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BP_PINCTRL_DRIVE8_RSRVD3 14 +#define BM_PINCTRL_DRIVE8_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE8_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE8_RSRVD3) +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BP_PINCTRL_DRIVE8_RSRVD2 10 +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE8_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE8_RSRVD2) +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BP_PINCTRL_DRIVE8_RSRVD1 6 +#define BM_PINCTRL_DRIVE8_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE8_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE8_RSRVD1) +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BP_PINCTRL_DRIVE8_RSRVD0 2 +#define BM_PINCTRL_DRIVE8_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE8_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE8_RSRVD0) +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000290) +#define HW_PINCTRL_DRIVE9_SET (0x00000294) +#define HW_PINCTRL_DRIVE9_CLR (0x00000298) +#define HW_PINCTRL_DRIVE9_TOG (0x0000029c) +#define HW_PINCTRL_DRIVE9_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9) +#define HW_PINCTRL_DRIVE9_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9_SET) +#define HW_PINCTRL_DRIVE9_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9_CLR) +#define HW_PINCTRL_DRIVE9_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9_TOG) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BM_PINCTRL_DRIVE9_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN11_MA 12 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_BANK2_PIN11_MA) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BP_PINCTRL_DRIVE9_RSRVD0 2 +#define BM_PINCTRL_DRIVE9_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE9_RSRVD0) +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000002a0) +#define HW_PINCTRL_DRIVE10_SET (0x000002a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000002a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000002ac) +#define HW_PINCTRL_DRIVE10_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10) +#define HW_PINCTRL_DRIVE10_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10_SET) +#define HW_PINCTRL_DRIVE10_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10_CLR) +#define HW_PINCTRL_DRIVE10_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10_TOG) + +#define BM_PINCTRL_DRIVE10_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN23_MA 28 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE10_BANK2_PIN23_MA) +#define BM_PINCTRL_DRIVE10_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN22_MA 24 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_BANK2_PIN22_MA) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000002b0) +#define HW_PINCTRL_DRIVE11_SET (0x000002b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000002b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000002bc) +#define HW_PINCTRL_DRIVE11_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11) +#define HW_PINCTRL_DRIVE11_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11_SET) +#define HW_PINCTRL_DRIVE11_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11_CLR) +#define HW_PINCTRL_DRIVE11_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11_TOG) + +#define BM_PINCTRL_DRIVE11_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN31_MA 28 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE11_BANK2_PIN31_MA) +#define BM_PINCTRL_DRIVE11_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN30_MA 24 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE11_BANK2_PIN30_MA) +#define BM_PINCTRL_DRIVE11_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN29_MA 20 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE11_BANK2_PIN29_MA) +#define BP_PINCTRL_DRIVE11_RSRVD4 18 +#define BM_PINCTRL_DRIVE11_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BP_PINCTRL_DRIVE11_BANK2_PIN28_MA 16 +#define BM_PINCTRL_DRIVE11_BANK2_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_BANK2_PIN28_MA) +#define BP_PINCTRL_DRIVE11_RSRVD3 14 +#define BM_PINCTRL_DRIVE11_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE11_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE11_RSRVD3) +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000002c0) +#define HW_PINCTRL_DRIVE12_SET (0x000002c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000002c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000002cc) +#define HW_PINCTRL_DRIVE12_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12) +#define HW_PINCTRL_DRIVE12_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12_SET) +#define HW_PINCTRL_DRIVE12_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12_CLR) +#define HW_PINCTRL_DRIVE12_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12_TOG) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000002d0) +#define HW_PINCTRL_DRIVE13_SET (0x000002d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000002d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000002dc) +#define HW_PINCTRL_DRIVE13_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13) +#define HW_PINCTRL_DRIVE13_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13_SET) +#define HW_PINCTRL_DRIVE13_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13_CLR) +#define HW_PINCTRL_DRIVE13_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13_TOG) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000002e0) +#define HW_PINCTRL_DRIVE14_SET (0x000002e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000002e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000002ec) +#define HW_PINCTRL_DRIVE14_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14) +#define HW_PINCTRL_DRIVE14_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14_SET) +#define HW_PINCTRL_DRIVE14_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14_CLR) +#define HW_PINCTRL_DRIVE14_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14_TOG) + +#define BP_PINCTRL_DRIVE14_RSRVD6 24 +#define BM_PINCTRL_DRIVE14_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE14_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_RSRVD6) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BM_PINCTRL_DRIVE14_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN19_MA 12 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_BANK3_PIN19_MA) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_PULL0 (0x00000400) +#define HW_PINCTRL_PULL0_SET (0x00000404) +#define HW_PINCTRL_PULL0_CLR (0x00000408) +#define HW_PINCTRL_PULL0_TOG (0x0000040c) +#define HW_PINCTRL_PULL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0) +#define HW_PINCTRL_PULL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0_SET) +#define HW_PINCTRL_PULL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0_CLR) +#define HW_PINCTRL_PULL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0_TOG) + +#define BM_PINCTRL_PULL0_BANK0_PIN31 0x80000000 +#define BM_PINCTRL_PULL0_BANK0_PIN30 0x40000000 +#define BM_PINCTRL_PULL0_BANK0_PIN29 0x20000000 +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BP_PINCTRL_PULL0_RSRVD2 23 +#define BM_PINCTRL_PULL0_RSRVD2 0x03800000 +#define BF_PINCTRL_PULL0_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL0_RSRVD2) +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BP_PINCTRL_PULL0_RSRVD1 16 +#define BM_PINCTRL_PULL0_RSRVD1 0x00030000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 16) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN15 0x00008000 +#define BP_PINCTRL_PULL0_RSRVD0 12 +#define BM_PINCTRL_PULL0_RSRVD0 0x00007000 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN11 0x00000800 +#define BM_PINCTRL_PULL0_BANK0_PIN10 0x00000400 +#define BM_PINCTRL_PULL0_BANK0_PIN09 0x00000200 +#define BM_PINCTRL_PULL0_BANK0_PIN08 0x00000100 +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000410) +#define HW_PINCTRL_PULL1_SET (0x00000414) +#define HW_PINCTRL_PULL1_CLR (0x00000418) +#define HW_PINCTRL_PULL1_TOG (0x0000041c) +#define HW_PINCTRL_PULL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1) +#define HW_PINCTRL_PULL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1_SET) +#define HW_PINCTRL_PULL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1_CLR) +#define HW_PINCTRL_PULL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1_TOG) + +#define BP_PINCTRL_PULL1_RSRVD3 29 +#define BM_PINCTRL_PULL1_RSRVD3 0xE0000000 +#define BF_PINCTRL_PULL1_RSRVD3(v) \ + (((v) << 29) & BM_PINCTRL_PULL1_RSRVD3) +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BP_PINCTRL_PULL1_RSRVD2 23 +#define BM_PINCTRL_PULL1_RSRVD2 0x0F800000 +#define BF_PINCTRL_PULL1_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL1_RSRVD2) +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BP_PINCTRL_PULL1_RSRVD1 19 +#define BM_PINCTRL_PULL1_RSRVD1 0x00380000 +#define BF_PINCTRL_PULL1_RSRVD1(v) \ + (((v) << 19) & BM_PINCTRL_PULL1_RSRVD1) +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BP_PINCTRL_PULL1_RSRVD0 0 +#define BM_PINCTRL_PULL1_RSRVD0 0x0003FFFF +#define BF_PINCTRL_PULL1_RSRVD0(v) \ + (((v) << 0) & BM_PINCTRL_PULL1_RSRVD0) + +#define HW_PINCTRL_PULL2 (0x00000420) +#define HW_PINCTRL_PULL2_SET (0x00000424) +#define HW_PINCTRL_PULL2_CLR (0x00000428) +#define HW_PINCTRL_PULL2_TOG (0x0000042c) +#define HW_PINCTRL_PULL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2) +#define HW_PINCTRL_PULL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2_SET) +#define HW_PINCTRL_PULL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR) +#define HW_PINCTRL_PULL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2_TOG) + +#define BP_PINCTRL_PULL2_RSRVD2 29 +#define BM_PINCTRL_PULL2_RSRVD2 0xE0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 29) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN28 0x10000000 +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BP_PINCTRL_PULL2_RSRVD1 9 +#define BM_PINCTRL_PULL2_RSRVD1 0x07FFFE00 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 9) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BP_PINCTRL_PULL2_RSRVD0 6 +#define BM_PINCTRL_PULL2_RSRVD0 0x000000C0 +#define BF_PINCTRL_PULL2_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_PULL2_RSRVD0) +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000430) +#define HW_PINCTRL_PULL3_SET (0x00000434) +#define HW_PINCTRL_PULL3_CLR (0x00000438) +#define HW_PINCTRL_PULL3_TOG (0x0000043c) +#define HW_PINCTRL_PULL3_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3) +#define HW_PINCTRL_PULL3_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3_SET) +#define HW_PINCTRL_PULL3_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3_CLR) +#define HW_PINCTRL_PULL3_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3_TOG) + +#define BP_PINCTRL_PULL3_RSRVD0 18 +#define BM_PINCTRL_PULL3_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_PULL3_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_PULL3_RSRVD0) +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000500) +#define HW_PINCTRL_DOUT0_SET (0x00000504) +#define HW_PINCTRL_DOUT0_CLR (0x00000508) +#define HW_PINCTRL_DOUT0_TOG (0x0000050c) +#define HW_PINCTRL_DOUT0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0) +#define HW_PINCTRL_DOUT0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0_SET) +#define HW_PINCTRL_DOUT0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0_CLR) +#define HW_PINCTRL_DOUT0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0_TOG) + +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) (v) + +#define HW_PINCTRL_DOUT1 (0x00000510) +#define HW_PINCTRL_DOUT1_SET (0x00000514) +#define HW_PINCTRL_DOUT1_CLR (0x00000518) +#define HW_PINCTRL_DOUT1_TOG (0x0000051c) +#define HW_PINCTRL_DOUT1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1) +#define HW_PINCTRL_DOUT1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1_SET) +#define HW_PINCTRL_DOUT1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1_CLR) +#define HW_PINCTRL_DOUT1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1_TOG) + +#define BM_PINCTRL_DOUT1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT1_DOUT) + +#define HW_PINCTRL_DOUT2 (0x00000520) +#define HW_PINCTRL_DOUT2_SET (0x00000524) +#define HW_PINCTRL_DOUT2_CLR (0x00000528) +#define HW_PINCTRL_DOUT2_TOG (0x0000052c) +#define HW_PINCTRL_DOUT2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2) +#define HW_PINCTRL_DOUT2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2_SET) +#define HW_PINCTRL_DOUT2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2_CLR) +#define HW_PINCTRL_DOUT2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2_TOG) + +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) (v) + +#define HW_PINCTRL_DIN0 (0x00000600) +#define HW_PINCTRL_DIN0_SET (0x00000604) +#define HW_PINCTRL_DIN0_CLR (0x00000608) +#define HW_PINCTRL_DIN0_TOG (0x0000060c) +#define HW_PINCTRL_DIN0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0) +#define HW_PINCTRL_DIN0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0_SET) +#define HW_PINCTRL_DIN0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0_CLR) +#define HW_PINCTRL_DIN0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0_TOG) + +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) (v) + +#define HW_PINCTRL_DIN1 (0x00000610) +#define HW_PINCTRL_DIN1_SET (0x00000614) +#define HW_PINCTRL_DIN1_CLR (0x00000618) +#define HW_PINCTRL_DIN1_TOG (0x0000061c) +#define HW_PINCTRL_DIN1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1) +#define HW_PINCTRL_DIN1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1_SET) +#define HW_PINCTRL_DIN1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1_CLR) +#define HW_PINCTRL_DIN1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1_TOG) + +#define BM_PINCTRL_DIN1_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN1_DIN) + +#define HW_PINCTRL_DIN2 (0x00000620) +#define HW_PINCTRL_DIN2_SET (0x00000624) +#define HW_PINCTRL_DIN2_CLR (0x00000628) +#define HW_PINCTRL_DIN2_TOG (0x0000062c) +#define HW_PINCTRL_DIN2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2) +#define HW_PINCTRL_DIN2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2_SET) +#define HW_PINCTRL_DIN2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2_CLR) +#define HW_PINCTRL_DIN2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2_TOG) + +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) (v) + +#define HW_PINCTRL_DOE0 (0x00000700) +#define HW_PINCTRL_DOE0_SET (0x00000704) +#define HW_PINCTRL_DOE0_CLR (0x00000708) +#define HW_PINCTRL_DOE0_TOG (0x0000070c) +#define HW_PINCTRL_DOE0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0) +#define HW_PINCTRL_DOE0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0_SET) +#define HW_PINCTRL_DOE0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0_CLR) +#define HW_PINCTRL_DOE0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0_TOG) + +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) (v) + +#define HW_PINCTRL_DOE1 (0x00000710) +#define HW_PINCTRL_DOE1_SET (0x00000714) +#define HW_PINCTRL_DOE1_CLR (0x00000718) +#define HW_PINCTRL_DOE1_TOG (0x0000071c) +#define HW_PINCTRL_DOE1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1) +#define HW_PINCTRL_DOE1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1_SET) +#define HW_PINCTRL_DOE1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1_CLR) +#define HW_PINCTRL_DOE1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1_TOG) + +#define BM_PINCTRL_DOE1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE1_DOE) + +#define HW_PINCTRL_DOE2 (0x00000720) +#define HW_PINCTRL_DOE2_SET (0x00000724) +#define HW_PINCTRL_DOE2_CLR (0x00000728) +#define HW_PINCTRL_DOE2_TOG (0x0000072c) +#define HW_PINCTRL_DOE2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2) +#define HW_PINCTRL_DOE2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2_SET) +#define HW_PINCTRL_DOE2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2_CLR) +#define HW_PINCTRL_DOE2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2_TOG) + +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) (v) + +#define HW_PINCTRL_PIN2IRQ0 (0x00000800) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00000804) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00000808) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000080c) +#define HW_PINCTRL_PIN2IRQ0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0) +#define HW_PINCTRL_PIN2IRQ0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0_SET) +#define HW_PINCTRL_PIN2IRQ0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0_CLR) +#define HW_PINCTRL_PIN2IRQ0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0_TOG) + +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ1 (0x00000810) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00000814) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00000818) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000081c) +#define HW_PINCTRL_PIN2IRQ1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1) +#define HW_PINCTRL_PIN2IRQ1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1_SET) +#define HW_PINCTRL_PIN2IRQ1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1_CLR) +#define HW_PINCTRL_PIN2IRQ1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1_TOG) + +#define BM_PINCTRL_PIN2IRQ1_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ1_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ2 (0x00000820) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00000824) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00000828) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000082c) +#define HW_PINCTRL_PIN2IRQ2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2) +#define HW_PINCTRL_PIN2IRQ2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2_SET) +#define HW_PINCTRL_PIN2IRQ2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2_CLR) +#define HW_PINCTRL_PIN2IRQ2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2_TOG) + +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) (v) + +#define HW_PINCTRL_IRQEN0 (0x00000900) +#define HW_PINCTRL_IRQEN0_SET (0x00000904) +#define HW_PINCTRL_IRQEN0_CLR (0x00000908) +#define HW_PINCTRL_IRQEN0_TOG (0x0000090c) +#define HW_PINCTRL_IRQEN0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0) +#define HW_PINCTRL_IRQEN0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0_SET) +#define HW_PINCTRL_IRQEN0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0_CLR) +#define HW_PINCTRL_IRQEN0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0_TOG) + +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN1 (0x00000910) +#define HW_PINCTRL_IRQEN1_SET (0x00000914) +#define HW_PINCTRL_IRQEN1_CLR (0x00000918) +#define HW_PINCTRL_IRQEN1_TOG (0x0000091c) +#define HW_PINCTRL_IRQEN1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1) +#define HW_PINCTRL_IRQEN1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1_SET) +#define HW_PINCTRL_IRQEN1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1_CLR) +#define HW_PINCTRL_IRQEN1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1_TOG) + +#define BM_PINCTRL_IRQEN1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN1_IRQEN) + +#define HW_PINCTRL_IRQEN2 (0x00000920) +#define HW_PINCTRL_IRQEN2_SET (0x00000924) +#define HW_PINCTRL_IRQEN2_CLR (0x00000928) +#define HW_PINCTRL_IRQEN2_TOG (0x0000092c) +#define HW_PINCTRL_IRQEN2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2) +#define HW_PINCTRL_IRQEN2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2_SET) +#define HW_PINCTRL_IRQEN2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2_CLR) +#define HW_PINCTRL_IRQEN2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2_TOG) + +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) (v) + +#define HW_PINCTRL_IRQLEVEL0 (0x00000a00) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00000a04) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00000a08) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x00000a0c) +#define HW_PINCTRL_IRQLEVEL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0) +#define HW_PINCTRL_IRQLEVEL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0_SET) +#define HW_PINCTRL_IRQLEVEL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0_CLR) +#define HW_PINCTRL_IRQLEVEL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0_TOG) + +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL1 (0x00000a10) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00000a14) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00000a18) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x00000a1c) +#define HW_PINCTRL_IRQLEVEL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1) +#define HW_PINCTRL_IRQLEVEL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1_SET) +#define HW_PINCTRL_IRQLEVEL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1_CLR) +#define HW_PINCTRL_IRQLEVEL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1_TOG) + +#define BM_PINCTRL_IRQLEVEL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL1_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL2 (0x00000a20) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00000a24) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00000a28) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x00000a2c) +#define HW_PINCTRL_IRQLEVEL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2) +#define HW_PINCTRL_IRQLEVEL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2_SET) +#define HW_PINCTRL_IRQLEVEL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2_CLR) +#define HW_PINCTRL_IRQLEVEL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2_TOG) + +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQPOL0 (0x00000b00) +#define HW_PINCTRL_IRQPOL0_SET (0x00000b04) +#define HW_PINCTRL_IRQPOL0_CLR (0x00000b08) +#define HW_PINCTRL_IRQPOL0_TOG (0x00000b0c) +#define HW_PINCTRL_IRQPOL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0) +#define HW_PINCTRL_IRQPOL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0_SET) +#define HW_PINCTRL_IRQPOL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0_CLR) +#define HW_PINCTRL_IRQPOL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0_TOG) + +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL1 (0x00000b10) +#define HW_PINCTRL_IRQPOL1_SET (0x00000b14) +#define HW_PINCTRL_IRQPOL1_CLR (0x00000b18) +#define HW_PINCTRL_IRQPOL1_TOG (0x00000b1c) +#define HW_PINCTRL_IRQPOL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1) +#define HW_PINCTRL_IRQPOL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1_SET) +#define HW_PINCTRL_IRQPOL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1_CLR) +#define HW_PINCTRL_IRQPOL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1_TOG) + +#define BM_PINCTRL_IRQPOL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL1_IRQPOL) + +#define HW_PINCTRL_IRQPOL2 (0x00000b20) +#define HW_PINCTRL_IRQPOL2_SET (0x00000b24) +#define HW_PINCTRL_IRQPOL2_CLR (0x00000b28) +#define HW_PINCTRL_IRQPOL2_TOG (0x00000b2c) +#define HW_PINCTRL_IRQPOL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2) +#define HW_PINCTRL_IRQPOL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2_SET) +#define HW_PINCTRL_IRQPOL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2_CLR) +#define HW_PINCTRL_IRQPOL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2_TOG) + +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQSTAT0 (0x00000c00) +#define HW_PINCTRL_IRQSTAT0_SET (0x00000c04) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00000c08) +#define HW_PINCTRL_IRQSTAT0_TOG (0x00000c0c) +#define HW_PINCTRL_IRQSTAT0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0) +#define HW_PINCTRL_IRQSTAT0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0_SET) +#define HW_PINCTRL_IRQSTAT0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0_CLR) +#define HW_PINCTRL_IRQSTAT0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0_TOG) + +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT1 (0x00000c10) +#define HW_PINCTRL_IRQSTAT1_SET (0x00000c14) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00000c18) +#define HW_PINCTRL_IRQSTAT1_TOG (0x00000c1c) +#define HW_PINCTRL_IRQSTAT1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1) +#define HW_PINCTRL_IRQSTAT1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1_SET) +#define HW_PINCTRL_IRQSTAT1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1_CLR) +#define HW_PINCTRL_IRQSTAT1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1_TOG) + +#define BM_PINCTRL_IRQSTAT1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT1_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT2 (0x00000c20) +#define HW_PINCTRL_IRQSTAT2_SET (0x00000c24) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00000c28) +#define HW_PINCTRL_IRQSTAT2_TOG (0x00000c2c) +#define HW_PINCTRL_IRQSTAT2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2) +#define HW_PINCTRL_IRQSTAT2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2_SET) +#define HW_PINCTRL_IRQSTAT2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2_CLR) +#define HW_PINCTRL_IRQSTAT2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2_TOG) + +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) (v) +#endif /* __ARCH_ARM___PINCTRL_H */ |