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-rw-r--r--arch/arm/mach-tegra/platsmp.c1
-rw-r--r--arch/arm/mach-tegra/pm.c14
-rw-r--r--arch/arm/mach-tegra/pm.h14
-rw-r--r--arch/arm/mach-tegra/sleep.h46
4 files changed, 40 insertions, 35 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 5d150cb1907b..b67a32680395 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -29,6 +29,7 @@
#include "pm.h"
#include "clock.h"
+#include "sleep.h"
#define EVP_CPU_RESET_VECTOR \
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 62317b15d506..6a74589720db 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -138,20 +138,6 @@ struct suspend_context tegra_sctx;
#define CLK_RESET_CCLK_BURST_POLICY_PLLM 3
#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-#define FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
-#define FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
-#define FLOW_CTRL_CSR_WFI_BITMAP 0
-#else
-#define FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
-#define FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
-#define FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
-#endif
-
-#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
-#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
-#define FLOW_CTRL_CSR_ENABLE (1 << 0)
-
#define EMC_MRW_0 0x0e8
#define EMC_MRW_DEV_SELECTN 30
#define EMC_MRW_DEV_NONE (3 << EMC_MRW_DEV_SELECTN)
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 926e85183715..b64de7e41aea 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -59,11 +59,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode);
#define TEGRA_POWER_CLUSTER_IMMEDIATE 0x4000 /* Immediate wake */
#define TEGRA_POWER_CLUSTER_FORCE 0x8000 /* Force switch */
-#define FLOW_CTRL_HALT_CPU(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \
- ((cpu) == 0 ? 0x0 : 0x14 + ((cpu) - 1) * 0x8))
-#define FLOW_CTRL_CPU_CSR(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \
- ((cpu) == 0 ? 0x8 : 0x18 + ((cpu) - 1) * 0x8))
-
#define FLOW_CTRL_CLUSTER_CONTROL \
(IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c)
#define FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE (1<<3)
@@ -199,13 +194,4 @@ static inline void tegra_cluster_switch_set_parameters(
{ }
#endif
-static inline void flowctrl_writel(unsigned long val, void __iomem *addr)
-{
- writel(val, addr);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- wmb();
-#endif
- (void)__raw_readl(addr);
-}
-
#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2332e6f2c574..78325f49b85e 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -39,18 +39,50 @@
#define CPU_RESETTABLE_SOON 1
#define CPU_NOT_RESETTABLE 0
-#define FLOW_CTRL_WAITEVENT (2 << 29)
-#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
-#define FLOW_CTRL_JTAG_RESUME (1 << 28)
-#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
-#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
+#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
+#define FLOW_CTRL_WAITEVENT (2 << 29)
+#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
+#define FLOW_CTRL_JTAG_RESUME (1 << 28)
+#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
+#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
+#define FLOW_CTRL_CPU0_CSR 0x8
+#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
+#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
+#define FLOW_CTRL_CSR_ENABLE (1 << 0)
+#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
+#define FLOW_CTRL_CPU1_CSR 0x18
-#define FLOW_CTRL_CSR_INTR_FLAG (1<<15)
-#define FLOW_CTRL_CSR_EVENT_FLAG (1<<14)
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
+#define FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
+#define FLOW_CTRL_CSR_WFI_BITMAP 0
+#else
+#define FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
+#define FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
+#define FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
+#endif
#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT)
#ifndef __ASSEMBLY__
+
+#define FLOW_CTRL_HALT_CPU(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \
+ ((cpu) ? (FLOW_CTRL_HALT_CPU1_EVENTS + 8 * ((cpu) - 1)) : \
+ FLOW_CTRL_HALT_CPU0_EVENTS))
+
+#define FLOW_CTRL_CPU_CSR(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \
+ ((cpu) ? (FLOW_CTRL_CPU1_CSR + 8 * ((cpu) - 1)) : \
+ FLOW_CTRL_CPU0_CSR))
+
+static inline void flowctrl_writel(unsigned long val, void __iomem *addr)
+{
+ writel(val, addr);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+ wmb();
+#endif
+ (void)__raw_readl(addr);
+}
+
void tegra_pen_lock(void);
void tegra_pen_unlock(void);
void tegra_cpu_wfi(void);