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-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h50
-rw-r--r--arch/arm/plat-mxc/include/mach/mmc.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx5x.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_dvfs.h21
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h3
6 files changed, 42 insertions, 99 deletions
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 6beaf8cd69b5..7cd84547658f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,31 +68,33 @@ struct pad_desc {
/*
* Use to set PAD control
*/
+#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0
+#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_HYS (1 << 8)
+#define PAD_CTL_NO_HYSTERESIS 0
+#define PAD_CTL_HYSTERESIS 1
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4)
-#define PAD_CTL_PUS_360K_DOWN (0 << 4)
-#define PAD_CTL_PUS_47K_UP (1 << 4)
-#define PAD_CTL_PUS_75K_UP (1 << 4)
-#define PAD_CTL_PUS_100K_UP (2 << 4)
-#define PAD_CTL_PUS_22K_UP (3 << 4)
+#define PAD_CTL_PULL_DISABLED 0x0
+#define PAD_CTL_PULL_KEEPER 0xa
+#define PAD_CTL_PULL_DOWN_100K 0xc
+#define PAD_CTL_PULL_UP_47K 0xd
+#define PAD_CTL_PULL_UP_100K 0xe
+#define PAD_CTL_PULL_UP_22K 0xf
-#define PAD_CTL_ODE (1 << 3)
+#define PAD_CTL_OUTPUT_CMOS 0
+#define PAD_CTL_OUTPUT_OPEN_DRAIN 1
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_NORM 0
+#define PAD_CTL_DRIVE_STRENGTH_HIGH 1
+#define PAD_CTL_DRIVE_STRENGTH_MAX 2
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
+#define PAD_CTL_SLEW_RATE_SLOW 0
+#define PAD_CTL_SLEW_RATE_FAST 1
/*
- * setups a single pad in the iomuxer
+ * setups a single pad:
+ * - reserves the pad so that it is not claimed by another driver
+ * - setups the iomux according to the configuration
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
@@ -103,9 +105,17 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
/*
- * Initialise the iomux controller
+ * releases a single pad:
+ * - make it available for a future use by another driver
+ * - DOES NOT reconfigure the IOMUX in its reset state
*/
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
+void mxc_iomux_v3_release_pad(struct pad_desc *pad);
+
+/*
+ * releases multiple pads
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index 7be75bd5756e..d563c157bad7 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -40,9 +40,6 @@ struct mxc_mmc_platform_data {
unsigned int min_clk;
unsigned int max_clk;
unsigned int clk_flg; /* 1 clock enable, 0 not */
- unsigned int clk_always_on; /* Needed by SDIO cards and etc */
- unsigned int dll_override_en; /* Enable dll override delay line */
- unsigned int dll_delay_cells; /* The number of delay cells (0-0x3f) */
unsigned int reserved:16;
unsigned int card_fixed:1;
unsigned int card_inserted_state:1;
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 0e25133736d2..fd3bbefdd292 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -134,31 +134,6 @@
*/
#define MX53_SATA_BASE_ADDR 0x10000000
-/*
- * Databahn MX50
- */
-#define MX50_DATABAHN_BASE_ADDR 0x14000000
-#define DATABAHN_CTL_REG19 0x4c
-#define DATABAHN_CTL_REG20 0x50
-#define DATABAHN_CTL_REG21 0x54
-#define DATABAHN_CTL_REG22 0x58
-#define DATABAHN_CTL_REG23 0x5c
-#define DATABAHN_CTL_REG42 0xa8
-#define DATABAHN_CTL_REG43 0xac
-#define DATABAHN_CTL_REG55 0xdc
-#define DATABAHN_CTL_REG63 0xFC
-#define LOWPOWER_CONTROL_MASK 0x1F
-#define LOWPOWER_AUTOENABLE_MASK 0x1F
-#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16)
-#define LOWPOWER_EXTERNAL_CNT_OFFSET 16
-#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8)
-#define LOWPOWER_INTERNAL_CNT_OFFSET 8
-#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16)
-#define LOWPOWER_REFRESH_ENABLE_OFFSET 16
-#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF
-#define LOWPOWER_REFRESH_HOLD_OFFSET 0
-
-
#define DEBUG_BASE_ADDR 0x40000000
/*MX53 + 0x2000000 */
#define DEBUG_SIZE SZ_1M
@@ -171,7 +146,7 @@
#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
-#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
+#define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000)
#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000)
#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000)
@@ -262,7 +237,6 @@
#define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
-#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */
#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180)
#define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 808adf67552d..fc466b1c76c3 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -235,7 +235,6 @@ struct mxc_ipu_config {
int rev;
void (*reset) (void);
struct clk *di_clk[2];
- struct clk *csi_clk[2];
};
struct mxc_ir_platform_data {
@@ -326,29 +325,6 @@ struct ccwmx51_lcd_pdata {
void (*bl_enable) (int, int);
};
-struct mxc_epdc_fb_mode {
- struct fb_videomode *vmode;
- int vscan_holdoff;
- int sdoed_width;
- int sdoed_delay;
- int sdoez_width;
- int sdoez_delay;
- int gdclk_hp_offs;
- int gdsp_offs;
- int gdoe_offs;
- int gdclk_offs;
- int num_ce;
-};
-
-struct mxc_epdc_fb_platform_data {
- struct mxc_epdc_fb_mode *epdc_mode;
- int num_modes;
- void (*get_pins) (void);
- void (*put_pins) (void);
- void (*enable_pins) (void);
- void (*disable_pins) (void);
-};
-
struct mxc_tsc_platform_data {
char *vdd_reg;
int penup_threshold;
@@ -634,18 +610,6 @@ struct mxc_sim_platform_data {
unsigned int detect; /* 1 have detect pin, 0 not */
};
-struct fsl_otp_data {
- char **fuse_name;
- char *regulator_name;
- unsigned int fuse_num;
-};
-
-struct mxs_dma_plat_data {
- unsigned int burst8:1;
- unsigned int burst:1;
- unsigned int chan_base;
- unsigned int chan_num;
-};
#endif /* __ASSEMBLY__ */
#define MUX_IO_P 29
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
index 05c6ea4bda77..43bcd2f7043a 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -35,7 +35,6 @@
#include <linux/device.h>
extern void __iomem *gpc_base;
-extern void __iomem *ccm_base;
#define MXC_GPCCNTR_GPCIRQ2M (1 << 25)
#define MXC_GPCCNTR_GPCIRQ2 (1 << 24)
@@ -144,16 +143,16 @@ struct mxc_dvfs_platform_data {
void __iomem *membase;
/* The interrupt number used by the DVFS core */
int irq;
- /* GPC control reg offset */
- int gpc_cntr_offset;
- /* GPC voltage counter reg offset */
- int gpc_vcr_offset;
- /* CCM DVFS control reg offset */
- int ccm_cdcr_offset;
- /* CCM ARM clock root reg offset */
- int ccm_cacrr_offset;
- /* CCM divider handshake in-progress reg offset */
- int ccm_cdhipr_offset;
+ /* GPC control reg address */
+ void __iomem *gpc_cntr_reg_addr;
+ /* GPC voltage counter reg address */
+ void __iomem *gpc_vcr_reg_addr;
+ /* CCM DVFS control reg address */
+ void __iomem *ccm_cdcr_reg_addr;
+ /* CCM ARM clock root reg address */
+ void __iomem *ccm_cacrr_reg_addr;
+ /* CCM divider handshake in-progree reg address */
+ void __iomem *ccm_cdhipr_reg_addr;
/* PREDIV mask */
u32 prediv_mask;
/* PREDIV offset */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 604abbc77da0..126bc8713159 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,5 @@
extern void arch_idle(void);
void arch_reset(char mode, const char *cmd);
-int mxs_reset_block(void __iomem *hwreg, int just_enable);
#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */